JPH0459712B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to semiconductor memory devices, particularly high S/N
The present invention relates to a semiconductor memory device suitable for increasing speed and speed.

[Prior art]

As a conventional means for achieving S/N ratio, there is, for example, Japanese Patent Application No. 56-81042. That is, as shown in FIG. 1, a plurality of first data lines, for example, D ₀₀ , D ₀₁ , D ₀₂ , D ₀₃ or D ₁₀ , D ₁₁ , D ₁₂ ,
D divided into ₁₃ and these divided data lines,
2nd data line I/O (0), I/O (1), I/O (2), I/O via switch SW ₀₀ etc.
(3) This is a method for exchanging data. In this method, since the first data line is subdivided, the load capacitance seen from the memory cell is reduced accordingly, making it possible to achieve a high S/N or high speed. However, in this method, the second data line I/O
(0), I/O (1), I/O (2), and I/O (3) are connected to many transistors related to many switches, so the load capacitance of these second data lines is becomes large, so there is a limit to increasing the S/N and speed.

In addition, W is word line, XDEC/DR and
YDEC・DR is the X decoder, drive circuit and Y
A decoder and a drive circuit, RWC is a read line controller, MC is a memory cell, WE is a write enable signal, D _i is input data, and D _put is output data. The same applies to the following numbers.

Further, FIG. 2 shows another conventional example. In other words, the second data lines I/O(0) and I/O(1) are
Divided first data lines D ₀₀ , D ₀₁ , D ₀₂ , D ₀₃
etc. are arranged in parallel. By doing this, the load capacity of I/O (0) and I/O (1) is
Since only transistors related to a small number of switches corresponding to the number of divisions of one data line are connected, the size is significantly smaller than that in FIG. 1. Therefore, for example, signals taken out at high speed to I/O (0) and I/O (1) by switches SW ₀₀ , SW ₁₀ , etc. are sent to the switches controlled by YDEC/DR.
Either SW _Y0 or SW _Y1 is selected and output to the third data line I/O, and the read/write control circuit
Data output is D _put by RWC. However, even if the load capacitance of the I/O (0) and I/O (1) lines per unit length is smaller in Figure 2, depending on the configuration of the memory array, the I/O ( 0), I/O
There is a drawback that the length of (1) becomes sufficiently long and the load capacity of the entire I/O line becomes larger than in the case of FIG. 1, which becomes a problem.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that does not have the above drawbacks and is suitable for high S/N and high speed.

[Summary of the invention]

A semiconductor memory device according to a typical embodiment disclosed in this application includes a plurality of word lines W 0 to W 3 whose length direction is arranged substantially parallel to the first direction, and a plurality of word lines W ₀ to _{W 3} whose length direction is arranged in the first direction. The second direction that intersects the first direction
a plurality of first data line groups D ₀₀ to _{D 31} arranged substantially parallel to the direction of the plurality of first data lines D 00 to D ₃₁ ; a plurality of first switches SW ₀ ; A plurality of second data line groups i/o(0,0)~connected to the line groups _D00 ~ _D31 and arranged with their lengths substantially parallel to the first direction.
i/o(1,1), a plurality of second switches _SW1 , and the plurality of second data line groups i/o(0,0) to i via the plurality of second switches _SW1 . /o(1,
1) and the plurality of third data lines I/O(0) to I/O(1) whose length directions are arranged substantially parallel to the second direction; and the plurality of word lines. W ₀ to W ₃ and the first of the above
a plurality of memory cells MC arranged at desired intersections with the data line groups D ₀₀ to D ₃₁ ; and a plurality of word lines W ₀ to _{W 3} and the plurality of second
1st selection means for selecting switch SW ₁
XDEC/DR, and a second switch that selects the first switch SW ₀ of the above plurality.
the plurality of third data lines I/O(0) to I/O;
(1) The plurality of second data line groups i/o(0,0)~
I/O(1,1) is divided in the first direction, and the plurality of second data line groups I/O(0,0) to
The plurality of first data line groups D ₀₀ to D ₃₁ sandwich at least one data line of i/o (1, 1).
is characterized in that it is divided in the second direction.

According to such representative embodiments, a plurality of third
A plurality of second data line groups I/O sandwich one data line of data lines I/O(0) to I/O(1).
(0,0) to i/o(1,1) are divided in the first direction, so the second data line group i/o(0,0)
The distributed load capacitance and distributed resistance of the ~i/o (1, 1) wiring can be reduced, making it possible to increase the speed and increase the S/N.

According to a more preferred embodiment of the present application, the first selection means XDEC/DR selects one word line W ₀ from the plurality of word lines W ₀ to _{W 3} and the plurality of second switches.
Two second switches SW ₁ arranged along the first direction are selected from among SW ₁ , and the second selection means
The YEDC/DR is characterized in that it selects two switches SW ₀ arranged along the first direction from among the plurality of first switches SW ₀ .

According to this preferred embodiment, two memory cells MC arranged along the first direction are selected, and these two memory cells are connected to the two first data lines.
D ₀₀ , D ₂₀ , the two selected first switches
SW ₀ , two second data lines i/o(0,0), i/
o(1,0), the two selected second switches
two third data lines i/o(0) via SW ₁ ,
Since it is connected to i/o (1), the read information of the two selected memory cells MC can be read out in parallel to the two third data lines i/o (0) and i/o (1). This makes it possible to configure a memory XSI with a multi-bit configuration.

Other objects and features of the invention will become apparent from the following examples.

[Embodiments of the invention]

FIG. 3 is a schematic circuit diagram of a semiconductor memory device as an embodiment of the present invention. For example, one data line is divided into two (D ₀₀ , D _{01 ,} etc.) to form a first data line group, and a second data line group i/orthogonal to the data line is connected via a first switch SW ₀ . o(0,
0), i/o (0, 1), i/o (1, 0), i/o
(1, 1), and further a third data line group I/O(0), I/O(1) parallel to the first data line group is arranged via the second switch _SW1 . do. Control signal output from word line W ₀ and YDEC/DR
The memory operation when YC ₀ turns ON is explained below. When W ₀ is turned on, each data line D ₀₀ ,
Among the read signals appearing at D ₁₀ , D ₂₀ , and D ₃₀ ,
Switch SW ₀ is controlled by YC ₀ being ON.
Only the D ₀₀ and D ₂₀ signals are i/o(0,0) and i/o
o(1,0). Furthermore, IOC ₀ controlled by XDEC/DR is turned on and these data are output to I/O (0) and I/O (1), respectively. This data is amplified by the sense amplifier SA, and desired data is selected by the third switch _SW2 and becomes the data output. The write operation is done in the same way, using the data input _D1 and the write control signal.
This is done by WE via the RWC circuit and the drive circuit DRV. In this example, among the four YC lines,
The logic is that two are always selected, but if two address buffers AB are provided, one out of four
You can also select the YC of the book. in this case,
Although the load capacity of the I/O line increases, the I/O (0,
0), i/o (1, 0) can be shared, and I/O
Since only one (0) and I/O (1) is required, SW ₂ is not required, and SA and DRV can be cut in half. In addition, in the embodiment shown in Fig. 3, the data output simultaneously to I/O (0) and I/O (1) is output as multiple data outputs to the outside of the chip without being decoded, that is, without using SW ₂ . You can also. This configuration allows parallel writing for multiple data inputs.
This is convenient for multi-bit configurations such as memory LSIs. Although this embodiment is applicable to various types of memory cells, not limited to those listed, in the following, one
A dynamic memory in which a memory cell is composed of a single MOS transistor and a capacitor will be explained as an example.

FIG. 4 is a schematic circuit diagram of a semiconductor memory device as another embodiment of the present invention, and is an example of dividing data lines into two for a memory cell (hereinafter referred to as a two-intersection cell) in which the data lines are composed of adjacent pairs of lines. be. Said third
The address buffer AB in the figure is omitted for simplicity. Similarly, precharge circuits and sense amplifiers connected to data pairs or I/O and I/O pairs depending on the purpose are omitted.

MC is a memory cell, and DC is a dummy cell that generates a reference voltage for the read signal of the MC and differentially amplifies it with a sense amplifier to discriminate between information "1" and "0". W ₀ , W ₁ , ... are word lines, DW ₀ , DW ₁ are dummy word lines, IOC ₀ ,
IOC ₁ is a switch control signal. Also, SWC is a switch control circuit, and MA is a memory cell array. Note that the YC lines (YC ₀ , YC ₁ ,...) are Al2 in this example.
Although layer wiring is used, the invention is not particularly limited to this. In other words, if you use a memory cell in which the data line is made of a material other than Al, such as poly-Si, there is no need to use a 2-layer Al wiring for the YC line, and a 1-layer Al wiring can be applied in the same way. It was equally effective.

FIG. 5 is a schematic circuit diagram of a semiconductor memory device as yet another embodiment of the present invention. A transistor Q, which functions as a switch, is arranged at both ends of the data pair lines D ₀₀ and ₀₀ , and the gate of the transistor is controlled by YC ₀ and the like. Also the second
One end of the data line I/O (0,0), (0,0), etc. has the role of a switch, and IOC ₀ ,
Transistors Q ₁ and ₁ controlled by IOC ₀ ′ and the like are connected. Here Q ₀ , ₀ are sense amplifiers
A method of arranging it close to SA ₁ is also possible, but this complicates the layout and introduces capacitance imbalance in the data pair lines, which may become a noise source or increase the data line capacity. On the other hand, the embodiment shown in FIG. 5 can be laid out independently of SA ₁ , making the design easier. As a memory cell, for example, Nikkei Electronics August 1982
As described in the 30th issue, p.166, Figure 10,
Memory cells whose data lines are formed using three-layer poly-Si can also be used.

FIG. 6 is a schematic circuit diagram of a semiconductor memory device according to yet another embodiment of the present invention, in which a second data line is connected to a second data line using FIG. This is an example in which the data line 1 is perpendicular to the data line 1. Although the capacitance of the second data line is slightly larger, the area is smaller due to the simpler circuit, and the design is easier. An example in which the above circuit embodiment is arranged on an actual chip will be described below.

FIG. 7 is a layout diagram in which MA etc. are arranged symmetrically with respect to the circuit diagram XDEC/DR of FIG. 4. Usually, the word line of a two-intersection cell is made of relatively high resistance poly-Si or refractory metal silicide. If the shape of the chip CHIP is restricted by the part gauge dimensions and has to be rectangular as shown in Figure 7, the word line should be arranged in the direction of the short side of the chip and divided to reduce the delay time of the word line. The configuration shown in FIG. 7, which drives from the midpoint of the word line, is desirable. Furthermore, if the YC line is a sufficiently low-resistance wiring such as Al, it can be passed through the plurality of memory cell arrays MA in the long side direction of the chip. Also I/
For ease of layout, it is convenient for the sense amplifiers SA and DRV connected to the O line to be placed on the side of the peripheral circuit group PRC2 opposite to the YDEC and DR. This is because if placed on the peripheral circuit group PRC1 side,
Wiring to SA, DRV, etc. has to pass over YDEC/DR, but this is because the layout is complicated. Furthermore, FIG. 7 can also be applied to the embodiment shown in FIG. However, since the word line of a single-intersection cell is usually made of a low-resistance material such as Al, there is no need to take the trouble to divide the word line.
XDEC/DR may be placed at the end of the chip in the short side direction.

FIG. 8 is a layout diagram of the circuit diagram of FIG. 6. Since the word lines are arranged in the long side direction of the chip, the word line has a low resistance, which is an advantage of the one-cross point cell. Also YC line
If formed using Al2 layer wiring, the YDEC/DR can be placed at the edge of the chip as shown in the figure, so the drive circuit for the YDEC/DR section only needs to be on one side, and the area can be reduced accordingly. Of course, depending on the design, it is also possible to place YDER/DR in the middle.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor memory device that has a high S/N ratio and is easy to design.

[Brief explanation of the drawing]

1 and 2 are schematic circuit diagrams of a conventional semiconductor memory device, FIG. 3 is a schematic circuit diagram of a semiconductor memory device as an embodiment of the present invention, and FIGS.
The figure is a schematic circuit diagram of a semiconductor memory device as another embodiment of the present invention, and FIGS. 7 and 8 are schematic layout diagrams used in the present invention. D ₀₀ , D ₀₁ , ... data line, W ₀ , W ₁ ... word line,
YC ₀ , YC ₁ ,...control signal, SA...sense amplifier,
AB...Address buffer, SW ₀ , SW ₁ ...Switch, D ₁ ...Data input, WE...Write control signal.

Claims (1)

[Claims] 1. A plurality of word lines whose length direction is arranged substantially parallel to the first direction, and a second word line whose length direction intersects the first direction.
a plurality of first data line groups arranged substantially parallel to the direction of the plurality of first data line groups; a plurality of first switches; and a plurality of first data line groups connected to the plurality of first data line groups through the plurality of first switches. a plurality of second data line groups whose length directions are arranged substantially parallel to the first direction; a plurality of second switches; and a plurality of second switches via the plurality of second switches. a plurality of third data lines connected to the plurality of third data lines and whose length direction is arranged substantially parallel to the second direction, and a plurality of third data lines connected to the plurality of word lines and the plurality of first data line groups at a desired intersection A plurality of arranged memory cells, a first selection means for selecting the plurality of word lines and the plurality of second switches, and a second selection means for selecting the plurality of first switches. The plurality of second data line groups are divided in the first direction so as to sandwich at least one data line of the plurality of third data lines, and at least one of the plurality of second data line groups is divided in the first direction. A semiconductor memory device characterized in that the plurality of first data line groups are divided in the second direction so as to sandwich the data lines of the book. 2 the first selection means selects one word line from the plurality of word lines and two second switches arranged along the first direction from among the plurality of second switches; 2. The semiconductor memory device according to claim 1, wherein said second selection means selects two switches arranged along said first direction from among said plurality of first switches. 3 The plurality of first data line groups, the plurality of second data line groups, and the plurality of third data lines are:
Each of the plurality of pairs of data lines is connected to a plurality of sense amplifiers. semiconductor memory devices. 4. The semiconductor memory device according to any one of claims 1 to 3, wherein a plurality of read amplification means are connected to the plurality of third data lines. 5. The plurality of first data line groups are comprised of folded pair lines, and the two lines constituting the folded pair lines are arranged close to each other. The semiconductor memory device according to any one of items 1 to 4. 6 The pairs of the plurality of first data line groups are each connected to the plurality of sense amplifiers, and the plurality of first data line groups are connected to the plurality of sense amplifiers.
Claim 1, wherein the two lines constituting each pair of the data line group are arranged in a straight line approximately parallel to the second direction with the sense amplifier as the center. 4. The semiconductor memory device according to any one of items 1 to 4. 7 The second selection means has a plurality of control lines for selecting the plurality of first switches, the plurality of control lines are arranged substantially parallel to the second direction, and the plurality of control lines a first data line group, and a plurality of second data line groups.
Claim 1, wherein the data line group and the plurality of third data lines are formed in a first wiring layer, and the plurality of control lines are formed in a second wiring layer. Section 6
3. The semiconductor memory device according to any one of the items. 8. A longitudinal direction of at least one of the first selection means and the second selection means and a longitudinal direction of the other are arranged substantially parallel to the first direction and the second direction, respectively. A semiconductor memory device according to any one of claims 1 to 7. 9. At least one of the first selection means and the second selection means is arranged approximately at the center of the rectangular chip, and the longitudinal direction of the one is approximately parallel to the longitudinal direction of the rectangle. A semiconductor memory device according to any one of claims 1 to 8. 10 Claim 9, wherein the other longitudinal direction of the first selection means and the second selection means is a direction substantially orthogonal to the one longitudinal direction.
The semiconductor memory device described in Section 1. 11. The semiconductor memory according to claim 10, wherein the other of the first selection means and the second selection means is disposed close to one of two short sides of the chip. Device. 12. At least one of the first selection means and the second selection means is disposed close to one of two long sides of a rectangular chip. 9. The semiconductor memory device according to claim 8. 13. Claim 1, characterized in that the other longitudinal direction of the first selection means and the second selection means is a direction substantially perpendicular to the one longitudinal direction.
2. The semiconductor memory device according to item 2. 14. The semiconductor memory according to claim 13, wherein the other of the first selection means and the second selection means is disposed close to one of two short sides of the chip. Device. 15. The first selection means and the second selection means select the plurality of word lines, the plurality of second switches, and the plurality of first switches in response to an address signal. A semiconductor memory device according to any one of claims 1 to 14. 16. The semiconductor memory according to any one of claims 1 to 15, wherein each of the plurality of memory cells is a dynamic memory cell composed of one transistor and one capacitor. Device.