JPH0459716B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gallium arsenide integrated circuit, and particularly to a static RAM using MESFET.

[Conventional technology]

Figure 10 shows, for example, the 1982 GaAsIC Symposium, Technical Digest (GaAs IC
This figure shows the configuration of the conventional gallium arsenide memory element shown in Fig. 1 of Symposium, Technical Digest) pp. 4. In the figure, 1 and 3 are normally-on MESFETs, and 2, 4, 5, and 6 are normally-off MESFETs. V _DD is the positive power supply. B,
B are a bit line and a bit line, respectively. WL
is a word line and is connected to a word line drive circuit composed of a DCFL circuit or a super buffer circuit.

Normally-on type MESFET1 and normally-off type
MESFET2, two normally-on type MESFETs, and normally-off type MESFET4.
A flip-flop circuit is formed by connecting the outputs of DCFL inverters to each other's gates,
Furthermore, these two DCFL inverter outputs are connected to a normally-off MESFET as a transfer gate.
By connecting to the left and right bit lines B and the bit line B via the transistors 5 and 6, a static type memory cell consisting of six transistors is constructed.

This memory cell is a normally-off MESFET
Depending on which of 2 and 4 is in the on state,
It stores information of "1" and "0".

Information is read by setting the word line WL to a high potential, making the transfer gates 5 and 6 conductive, and transmitting the information stored in the memory cell to the bit line pair B and B. Also, to write information,
This is done by making transfer gates 5 and 6 conductive and transmitting input data from the data input buffer to the memory cell via bit line pair B and B.

[Problem to be solved by the invention]

Conventionally, when this memory cell is formed on a gallium arsenide substrate, in a memory cell in which word line WL is in a low potential and in a non-selected state, leakage current flowing through transfer gates 5 and 6 causes the bit line B and There was a problem in that erroneous writing to the memory cells occurred and information in the memory cells was destroyed.

In other words, the internal node of the memory cell in FIG. 10 has a high potential of about 0.6V in the non-selected state;
The low potential side is approximately at ground potential. On the other hand, in a word line drive circuit configured with a DCFL, the low level of the output is approximately the threshold voltage of the MESFET.
Therefore, the gate voltage of the transfer gates 5 and 6 in the non-selected state to which the word line WL is connected is approximately the threshold voltage of the MESFET, and since the low potential side of the memory cell internal node is approximately at ground potential, the gates are forward biased. be in a state of being
In a gallium arsenide MESFET, the drain
The source-to-source current Ids is minimum when the gate-source voltage Vgs is about 0.3V lower than the threshold voltage.
When Vgs is the threshold voltage, a current approximately 10 ³ times or more of the minimum value flows. Therefore, when reading information from a selected memory cell to a bit line, leakage current from other non-selected memory cells causes the bit line on the high potential side of the left and right bit line pair to drop. There was a problem in that the potential decreased and the potential of the bit line on the low potential side increased, resulting in erroneous writing to the selected memory cell.

In order to solve such problems, there is a circuit shown in FIG. 11, for example, in the Semiconductor Transistor Study Group Material SSD84-130, pp65 of the Institute of Electronics and Communication Engineers, as shown in FIG. By using a level shift circuit, the low level of the word line potential in the non-selected state is set to a deep negative value, and the transfer gates 5, 6
The leakage current is reduced by placing the gate voltage in a deep reverse bias state. However, the level shift circuit had the drawback of requiring two positive and negative power supplies.

This invention was made in order to solve the above problems, and it is a gallium arsenide integrated circuit that can reduce the leakage current of the transfer gate, prevent erroneous writing to memory cells, and achieve stable operation. The purpose is to obtain.

[Means to solve the problem]

In the gallium arsenide integrated circuit according to the present invention, the static memory cell is configured by a flip-flop circuit, and the transfer gate driven by a word line is configured as a normally-off type.
In a semiconductor memory device configured with MESFETs, clamping means is provided for clamping the low-potential side internal node of the memory cell to a potential higher by a predetermined amount than when the word line is selected when the word line is not selected. The gate voltage of the transfer gate is placed in a deep reverse bias state.

[Effect]

In this invention, when a word line is not selected, a clamping means is provided for clamping the low potential side internal node of the memory cell to a potential higher by a predetermined amount than when the word line is selected. Since the gate voltage of the transfer gate is set to a deep reverse bias state, the transfer gate can be put into a stronger off state than the normal off state of the MESFET when the above clamping is not performed. Therefore, it is possible to reduce the current flowing through the transfer gate of the non-selected memory cell and prevent erroneous writing.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a gallium arsenide integrated circuit according to a first embodiment of the present invention. In the figure, 1 and 3 are normally-on MESFETs, and 2, 4, 5, and 6 are normally-off MESFETs. V _DD is the positive power supply. B, are a bit line and a bit line, respectively. WL is a word line, which is connected to a word line drive circuit composed of a DCFL circuit or a super buffer circuit. 7 is a normally-off MESFET, and 8 is a Schottky diode. One normally-off type MESFET and one shortcut diode 8 are provided in each row, and the drain of the normally-off type MESFET 7 and the anode of the shortcut diode 8 are connected to the first node connecting the sources of the memory cell driver MESFETs 2 and 4. 20. The source of the normally-off MESFET 7 and the cathode of the Schottky diode 8 are connected to the ground potential. RS is a row selection signal that changes at the same level or in phase with WL.

Next, the operation will be explained.

Assume that 1.5V is applied to V _DD . In the selected state, the word line WL has a high potential of about 0.6V, which is applied to the gates of transfer gates 5 and 6. At the same time, the row selection signal RS, which is the same or in-phase signal as WL, is normally off type.
Applied to the gate of MESFET7, this MESFET
7 is made conductive to lower the drain voltage to approximately ground potential. Since the drain of the normally-off MESFET 7 is connected to the first node 20, the high potential side of the internal node of the memory cell is 0.6V.
The low potential side is approximately the ground potential, and this potential is read out to the bit line through the transfer gate, or writing is performed by transferring the bit line potential to the internal node of the memory cell.

In the case of a non-selection signal, both the bit line WL and the row selection signal RS have a low potential of about 0.1V. At this time, normally-off type MESFET 7 becomes non-conductive, and the drain voltage is changed to short-circuit diode 8.
It is clamped to a potential of about 0.6V by . Therefore, the high potential side of the internal node of the memory cell is
The potential is about 1.2V, and the low potential side is about 0.6V.
Also, regarding the bit line, depending on the bit line load (not shown), the high potential side is about 0.6V and the low potential side is about 0.6V.
The potential is about 0.4V.

Therefore, in this embodiment, even when a potential of about 0.1V is applied to the gates of transfer gates 5 and 6, the low potential side of the internal node of the memory cell is clamped to a potential of about 0.6V by the Schottky diode 8. As a result, the gate is placed in a deep reverse bias state, leakage current can be sufficiently reduced, and erroneous writing to the memory cell can be prevented.

FIG. 2 shows a second embodiment of the invention, in which a resistive element 8' is used in place of the shotgun diode in FIG.

FIG. 3 shows a third embodiment of the present invention, in which one normally-off MESFET 7 is provided per row, and a shot diode 8 is connected to each memory cell.
This is an example in which each one is provided separately. Further, FIG. 4 shows a fourth embodiment in which a resistance element 8' is used in place of the shotgun diode 8 in FIG.

FIG. 5 shows a fifth embodiment of the present invention, in which one shotgun diode 8 is provided in each row, and one normally-off type MESFET 7 is provided in each memory cell. Also, Figure 6 shows the 5th
This is a sixth embodiment in which a resistive element 8' is used in place of the Schottky diode shown in the figure.

FIG. 7 shows a seventh embodiment of the present invention, in which both a normally-off type MESFET 7 and a Schottky diode 8 are provided in each memory cell. FIG. 8 shows an eighth embodiment in which a resistance element 8' is used in place of the shotgun diode in FIG.

FIG. 9 shows a ninth embodiment of the present invention, which is an example in which the present invention is applied to a circuit that operates with a single negative power supply. In addition, to replace the positive power supply and negative power supply,
This is also possible in the second to eighth embodiments.

The second to ninth embodiments also provide the same effects as the first embodiment.

In the first to ninth embodiments described above, Schottky diodes are used as diodes, but the same effect can be achieved even if PN diodes are used as diodes.

〔Effect of the invention〕

As described above, according to the gallium arsenide integrated circuit according to the present invention, clamp means is provided for clamping the low potential side internal node of the memory cell to a potential higher by a predetermined amount than when the word line is selected when the word line is not selected, Normally off type when word line is not selected
Since the gate voltage of the transfer gate formed by the MESFET is set to a deep reverse bias state, the transfer gate can be brought into a stronger OFF state than the normal MESFET OFF state when the above-mentioned clamping is not performed. This has the effect of reducing the current flowing through the transfer gate of a non-selected memory cell and preventing erroneous writing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a gallium arsenide integrated circuit according to a first embodiment of the present invention, and FIGS.
The figure is a circuit diagram showing gallium arsenide integrated circuits according to second to ninth embodiments of the present invention, and FIGS. 10 and 11 are circuit diagrams showing conventional gallium arsenide integrated circuits, respectively. In the figure, 1 and 3 are normally on type
MESFETs, 2, 4, 5, 6, and 7 are normally-off MESFETs, 8 is a shotgun diode, 8' is a resistive element, 20 is a first node, B is a bit line,
B is a bit line, RS is a row selection signal, WL is a word line, and V _DD is a positive power supply. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A static memory cell consisting of a flip-flop circuit formed on a gallium arsenide substrate, and a static memory cell formed on the substrate and connected between each node of the memory cell and a pair of bit lines. In a gallium arsenide integrated circuit having a transfer gate consisting of a normally-off MESFET, clamping means is provided for clamping the low potential side internal node of the memory cell to a potential higher by a predetermined amount than when the word line is selected when the word line is not selected. A gallium arsenide integrated circuit, characterized in that the gate voltage of the transfer gate is in a deep reverse bias state when the word line is not selected.