JPH045994B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic performance device that performs automatic performance based on performance information set in a memory by a user.

Conventionally, an automatic performance device has been developed in which one or more melodies are preset by a manufacturer in one memory, and these melodies are automatically played selectively (see Japanese Patent Laid-Open No. 43697/1983). . However, automatic performance using only melodies tends to lack variety in the performance, making it difficult to enjoy a rich variety of automatic performances.

This invention was made against the background of the above-mentioned circumstances, and its purpose is to realize an automatic performance device that uses a small memory capacity to enjoy a wide variety of automatic performances consisting of multiple parts set by the user. It is to be.

In order to achieve the above object, the present invention provides an automatic performance device capable of performing automatic performance based on performance information of a plurality of parts set by a user. When inputting one part at a time and storing it in the storage means, when the storage of the performance information of the first part is completed, the address of the storage means at that time is stored. The performance information of the second part is stored sequentially from the address corresponding to the stored address of the storage means. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an external view of an electronic musical instrument 1 equipped with an automatic performance function using melodies and chords.
This electronic musical instrument 1 has a keyboard 2, a control switch section 3, a display section 4, and a sound emitting section 5 on the top surface of the case, and inside the case are provided LSI components, speakers, etc. that constitute the circuit shown in FIG. There is. Note that the keyboard 2 and the control switch section 8 are both referred to as a switch input section 6.

Next, referring to FIG. 2, the control switch section 3
The configuration of the autoplay control switch section 3A and the display section 4 provided on the right side of FIG. 1 will be specifically explained. Note that the other configurations of the control switch unit 3 (the group of control switches provided on the left half in FIG. 1) are not related to the gist of the present invention, and therefore their description will be omitted.

In FIG. 2, a memory play switch 8 is a switch that reads out melodies and chords preset in RAM (random access memory), which will be described later, and switches to an automatic playing mode, and a bar code input switch 9 is a switch that reads out melodies and chords preset in RAM (random access memory), which will be described later, and switches to an automatic playing mode. This is a switch for reading the melody and chord information on the barcode reader and storing it in the RAM. The backward switch 10 and the forward switch 11 are switches for moving the address of the RAM backward or forward, respectively.
Also, the daily switch 12 is a switch that deletes data stored in RAM, and the reset switch 13 is a switch that deletes data stored in RAM.
This is a switch that initializes various registers of the RAM and a CPU (central processing unit), which will be described later, when writing data to the RAM. The repeat switch 14 is a switch for inputting the number of times the automatic performance is to be performed, and the automatic performance of the music set is repeated the number of times corresponding to the number of times of operation. The memory play start/stop switch 15 is a start/stop switch for auto play.
Further, return switches 16A and 16B are switches for executing return performance, respectively.
When writing melody or chord information to the RAM, input for the start and end measures between measures to be played repeatedly. The synchro start switch 17 is a switch that is turned on at any point when writing melody information to the RAM. By turning on the synchro start switch 17, the synchro start mark written to the RAM is read out from the RAM during automatic performance. RAM since
At the same time, reading of chord information is started, and the chords are played along with the melody. A rest switch 18 and an end switch 19 are switches for writing a rest mark and an end mark in the RAM, respectively. Note that each of the switches 16A to 19 is provided with one display element (for example, a light emitting diode) 20.
-1 to 20-5 are provided, and are lit when each switch is turned on or when the corresponding data is read during automatic performance.

The record code switch 21 and the record melody switch 22 are switches for specifying a mode for writing chords or melodies into the RAM, respectively.
The play switch 23 is a switch for specifying a play mode other than the write mode, and the melody guide switch 24 is a switch for specifying a mode of a navigation function for practice performance (details omitted).

One-key play switches 25A and 25B are switches for performing one-key play (details omitted). By operating the one-key play switches 25A and 25B, the tone length data in the melody and chord information preset in the RAM can be input. The unit length of the chord is 1/2 measure, and the one-key play switch is 25.
The length is set according to the number of operations of A and 25B.

The display section 4 digitally displays 8-digit numerical values and is composed of, for example, a liquid crystal display device. Therefore, this display section 4
When presetting the melody and chord in the RAM, the current number of write steps in the RAM is displayed. For example, if the storage capacity of the above RAM is 0~
Assuming that there are 999 steps (1000 steps in total), the display section 4 always shows the current number of steps as 3.
Displayed by digits.

Next, the circuit configuration of the electronic musical instrument 1 will be explained with reference to FIG. The CPU 30 is a circuit that controls all operations related to musical tone generation in the electronic musical instrument 1, and is, for example, a microprocessor.
As shown in the figure, inside this CPU 30,
Melody timer 31, chord timer 32,
MS, ME, MC, MR register, CS, CE, CC,
It has registers such as CR register, FS register, FE register, etc.

The CPU 30 outputs a key scan signal to the switch input section 6, and in response, the switch input section 6 detects the on/off state of each key of the keyboard 2, each control switch of the auto play control switch section 3A, etc. and the detection data is
given to CPU30. Based on the detected data, the CPU 30 controls reading and writing of data to and from the RAM 33, controls performance (manual performance, automatic performance) by the melody sound generation section 34 and the accompaniment sound generation section 35, and the like.

That is, the CPU 30 provides the address data AD and the read/write signal R/W to the RAM 33 to transmit data DATA between the CPU 30 and the RAM 33.
Read and write.

Further, the CPU 30 provides the melody sound generating section 34 and the accompaniment sound generating section 35 with an octave code and a scale code for the musical tone of the melody sound or accompaniment sound (chord) to be generated, respectively. At the same time, the CPU 30 outputs an attack (ATT) signal at the start of the envelope of the musical tone, and a release (REL) signal at the start of the release, which are applied to the melody sound generation section 34 and the accompaniment sound generation section 35. The melody sound generation section 34 and the accompaniment sound generation section 35 create melody sounds and accompaniment sounds, respectively, and these are transmitted to the speaker 3 via the acoustic conversion section 36.
7, and the sound is emitted from the sound emitting section 5.

Further, the CPU 30 executes a display control operation for the display section 4 and provides the data to the display section 4.

Note that the melody sound generation section 34 and the accompaniment sound generation section 3
No. 5 employs a time-division multiplex processing method, and has, for example, four time-division processing channels, and therefore generates a total of eight musical tones at the same time. For example, as such a musical tone generating circuit, it is possible to utilize Japanese Patent Application No. 56-130875 (filed on August 21, 1988, ``Electronic Musical Instrument'') previously filed by the present applicant.

Next, referring to Figures 4 to 8, the RAM 33
The configuration and the uses and configurations of each of the above-mentioned registers will be explained. FIG. 4 conceptually shows the configuration of the RAM 33. As mentioned above, when the total storage capacity of the RAM 33 is 1000 steps, each step stores one word (W) of data, and one word is made up of 16 bits. Addresses from 0 to 999 are assigned corresponding to the 0 to 999 steps, and an end mark (END) is always written at the end of the melody information and chord information.

FIG. 5 shows the data structure (one word) of melody information stored in the RAM 33. As mentioned above, one word consists of 16 bits.
The upper four bits (15th to 12th bits) store the pitch name of the musical tone or special mark data (described later). The next four bits (11th to 8th bits) store range data (described later). Furthermore, note length data is stored in the next lower 8 bits (7th to 0th bits).

FIG. 6A shows the data of the note names (note names C to B). Figure 6B shows the range, in this case the first octave (note names C ₀ to B ₀ ) to the eighth octave (note names C ₇
~B ₇ ) shows the range data for 8 octaves.
FIG. 6C shows tone length data. That is, data for 16 types of note lengths are shown. Figure 6D shows the data of special marks, in this case rest marks, return marks, synchronized start marks,
This is data for each mark of the end mark.

FIG. 7 shows the data structure (for one word) of code information stored in the RAM 33, and one word of this code information also has a 16-bit structure. The upper 4 bits (15 to 12 bits) contain the pitch name of the root note (according to Figure 6 A) or a special mark (Figure 6 D).
by. However, the synchro start mark becomes a synchro start command for starting the melody. ) data is stored. The next 4 bits (11th to 8th bits) store data on the type of code (described later). And the lower 8 bits (7th to 0th bits)
The tone length data is stored in . For example, the note length is data that specifies how many measures the chord should last (details are omitted).

FIG. 8 shows data representing types of chords, and eight types of chords are considered for one root note.

Next, the functions of the registers in the CPU 30 will be explained. The MS, ME, MC, and MR registers are registers for melody information, and the CS,
The CE, CC, and CR registers are registers for code information.

That is, the MS register and the ME register are registers that respectively store the start address and end address of the RAM 33 where melody information is stored. The MC register is a register that stores the address (current address) of the musical tone data of the melody information currently being played during automatic performance based on the melody information. The MR register is a register that stores a return address for automatic performance based on melody information.

The functions of the CS, CE, CC, and CR registers are listed above.
The functions are the same as those of the MS, ME, MC, and MR registers.

Furthermore, the FS register and FE register are RAM
33 free area management registers, RAM
The start and end addresses of the 33 free areas are stored respectively.

Next, the operation will be explained with reference to FIGS. 9 to 16. First, with reference to FIG. 9, a description will begin with a general description of the main operations of the electronic musical instrument 1, ie, normal (manual) performance, automatic performance, and storage of melody information and chord information.

In the case of normal performance, after the power switch is turned on, the keyboard 2 and control switch section 3 are operated to perform the performance. After turning on the power switch, step _S1 of the flowchart in Fig. 9 is executed.
The following process is executed, and each register in the CPU 30 is initialized. In this case, the MS to MR registers and the CS to CR registers are both cleared, while the FS register contains RAM as shown in Figure 10.
Address 0 of RAM 33 is set, and address 999 of RAM 33 is set in the FE register. That is,
Generally, after power-on, all of the RAM 33 is considered to be a free area.

After step S ₁ , step S ₂ via “LOOP”
key sampling processing is executed. That is,
The CPU 30 outputs a key scan signal to the switch input section 6, and the CPU 30 also inputs detection data for the key scan signal from the switch input section 6, and performs the process of determining whether or not the key is on in step _S3 .

If the memory play switch 8 is not operated, that is, if the automatic performance mode is not performed, for example, if the keyboard 1 is operated, the step will start.
The normal performance processing of step _S7 can be executed via _S4 , _S5 , and _S6 , respectively. That is, in response to key operations on the keyboard 2 and switch operations on the control switch section 3, the CPU 30 controls the melody sound generation section 34 and the accompaniment sound generation section 35 to supply octave chords, scale chords, attack signals, and release signals. . In response to this, the melody sound generator 3
A melody sound is generated from 4, and an accompaniment sound generator 3
5 generates accompaniment sound, and the sound is emitted from the sound emitting section 5.

When performing automatic performance using the melody information and chord information already preset in the RAM 33, after turning on the power switch, turn on the memory play switch 8 and then turn on the play switch 23. After each of the processes in steps _S1 to _S6 , the automatic performance process in step _S8 is executed. That is, melody information and chord information are read from the RAM 33, and automatic performance is executed. The specific operation of this automatic performance will be described in detail later.

When presetting melody information and chord information in the RAM 33, both melody information and chord information are initially data excluding note length data, that is, note name (special mark), range data or root note (special mark), and type information. Enter each data. After turning on the power switch and memory play switch 8, the record melody switch 22 or the record code switch 21 is turned on. Next, the above data is inputted by key operations on the keyboard 2 and switch operations on the auto-play control switch section 3. For this reason, data for the melody is preset in steps S ₁ to S ₄ and further in steps S ₉ and S ₁₀ , and in steps S ₁ to _{S 4} and further in steps S 9 and S ₁₀ .
Data for the code is preset in _S11 .

After inputting the note name of the melody and the root note of the chord as described above, the tone length data for both the melody and the chord are input. In this case, one-key play switches 25A and 25B are turned on and off alternately, for example, note length data is input, and data is sequentially input from address 0 of RAM 33 to the address where data such as the corresponding note name inputted earlier is stored. to be memorized. Then, the tone length data of the melody is stored in steps S ₁ to S ₅ and further in steps S ₁₂ and S ₁₃ , and in steps S ₁ to _{S 5} and further in steps S 12 and S ₁₃ .
The tone length data of the chord is stored in _S14 .

Next, referring to the flowchart in Figure 11,
The operation when inputting each data of note name (special mark) and pitch range of the melody information to the RAM 33 will be explained in detail. That is, FIG. 11 specifically shows the contents of step _S10 in FIG.

First, steps S ₂₁ and S ₂₂ are executed, respectively, and the FS
The data 0 address in the register is transferred to the MS register, and then the data 0 address in the MS register is transferred to the ME register. As a result, the 12th
As shown in Figure A, the MS, ME, and FS registers all store data 0, which specifies address 0 of the RAM 33, and the FE register stores data 999, which specifies address 999, as described above. has been done.

Further, the step display initialization process in step _S23 is executed, and the 0th step is displayed on the display section 4.

Next, key sampling processing in step _S24 is executed via LOOP1, and as a result, it is determined in step _S25 whether or not the key is on.

Now, if we input a scale by operating the keys on keyboard 2, the process will proceed from step _S26 to step _S27.
processing is executed. That is, the CPU 30 determines the operation keys on the keyboard and outputs the scale data.
The data is divided into 4-bit pitch name data and 4-bit range data according to FIGS. 6A and 6B, and these data are sent to the RAM 33.

Further, in step _S28 , the 0th step of the RAM 33 in which the scale has been written is displayed on the display section 4.

Next, in the process of step _S29 , the magnitude relationship between the data in the ME register and the data in the FE register is compared, and it is determined whether or not the RAM 33 has caused a memory overflow, that is, the current step has exceeded the 999th step, which is the maximum step. It is determined whether or not. Note that in the event of memory overflow, a message will be displayed to alert you.

The memory is not over, so next step _S30 is to move the note name data and range data to the RAM 33 specified by the ME register.
, that is, the upper 8 bits of address 0.

Then, in step _S31 , the ME register is incremented to address 1, and the process returns to LOOP1.

When inputting a scale by key operation on the keyboard 2, the above-mentioned steps _S24 to _S31 are executed, and the obtained note name data and range data are
It is stored in the upper 8 bits of the RAM 33 address specified by the ME register. In that case, the current number of steps is displayed on the display section 4, allowing the user to know the current number of steps and, therefore, the number of remaining steps. After storing the note name data and range data, the ME register is incremented and moved to the next address.

When inputting a return mark, which is a special mark, the return switch 16A or 16B is turned on. In this case, after the processing of steps _S24 to _S26 , input of a return mark is determined by the processing of step _S32 , and the process proceeds to step _S33 . Then, according to Figure 6D, 4-bit data "1101"
is obtained. However, there is currently no range data, and, for example, invalid data "1111" is used as the range data. Next, steps _S28 to _S31 are executed, and the ME
Data "1101" indicating the return mark and range data "1111" are stored in the upper eight bits of the address specified by the register. As a result, return performance based on melody information can be executed during automatic performance.

To input a rest, turn on the rest switch 18. In this case, the return switch 16
Steps _S24 to _S26 similar to when A and 16B are turned on,
Each process of S ₃₂ , S ₃₄ , S ₃₅ , and S ₂₈ to S ₃₁ is executed.
As a result, the data "1100" obtained according to FIG. 6D is stored in the upper 8 bits of the designated address of the RAM 33.

When storing a synchronized start mark for starting a chord performance in the middle of melody information, a synchronized start switch 17 is turned on. In this case as well, the same processing as when inputting special marks such as return and rest described above is executed, and data "1110" obtained from FIG. 6D is stored in the upper 8 bits of the specified address. Note that this processing step is the first
It is omitted in Figure 1.

FIG. 12B shows the state of the RAM 33 when melody information has already been stored in multiple steps as described above.
It also shows the status of the RAM 33 and the relationship between the RAM 33 and each register. That is, the MS register (address 0) and
Melody information is already stored in the area of the ME register up to the address one address before the current address. The area from address 0 to the current address is the illustrated melody area, and the area from the address next to the current address to address 999 is an empty area. Furthermore
The FS register and FE register are at addresses 0 and 999, respectively.
I remember the address.

On the other hand, after entering all the melody information,
Finally, turn on the end switch 19 and write an end mark at the end of the melody information. That is,
In this case, after each of steps _S24 to _S26 , _S32 , and _S34 , the process advances to step _S36 , where it is determined whether an end mark has been input. The process then proceeds to step _S33 via step _S37 , and the end mark data "1111" obtained from FIG. 6D is stored in the upper 8 bits of the address specified in the ME register. Next, step _S39 increments the ME register and transfers the data to the FS register.
Next, the process advances to LOOP in the flowchart of FIG. 9, and the writing process of the note name (special mark) and pitch range data in the melody information is completed.

FIG. 12C shows the status of the RAM 33 and the contents of each register at this point. That is, the MS register stores address 0, and the ME register stores the address where the end mark END is stored, and the area between these addresses forms a melody area where melody information is stored. Furthermore, the FS register stores the address next to the address where the end mark is stored by the process of step _S39 , and the FE register is at address 999. The area between these addresses is a vacant area.

Next, referring to the flowchart in FIG. 13, we will explain in detail the operation when inputting the root note (special mark) and type data in the chord information to the empty area following the melody information stored in the RAM 33. Explain in detail. That is, the flowchart of FIG. 13 shows the contents of step _S11 in FIG.

First, steps S ₄₁ and S ₄₂ are executed, and the FS
The data in the register is transferred to the CS register,
The data in this CS register is then transferred to the CE register. As a result, as shown in FIG. 14A, data indicating the address next to the address where the end mark END for the melody information is stored is stored in the CS, CE, and FS registers, and
Address 999 is stored in the FE register.

Further, the step display initialization process in step _S43 is executed, but in this case, the display contents of the display section 4 up to that point are maintained, that is, the address next to the end mark END is displayed.

Next, the key sampling process of step _S44 is performed via LOOP2, and as a result, the next step
The presence or absence of key-on by _S45 is determined.

When the root note and its type are input by operating the keys on the keyboard 2, the process proceeds to step _S47 via step _S46 , and the root note of each 4 bit is input according to the steps shown in FIGS. 6A and 8. You get data and that type of data. And then the steps mentioned above
Each process of steps _S48 to _S51 corresponding to _S28 to _S31 is executed.

That is, the current step number is displayed at step _S48 , and the CE register and FE register are displayed at step _S49 .
Each data in the register is compared and it is determined whether the memory is over. Furthermore, in Step S ₅₀ , the above
Current address of RAM, i.e. end mark above
The root note and its type data are stored in the upper bits of the address next to END, and then the CE register is incremented by step _S51 .
Return to LOOP2.

When inputting the data of the root note and its type, the processes of steps _S44 to _S51 described above are executed in the same way.

On the other hand, when inputting the return mark to return the chord information, the return switches 16A and 16B are turned on, as described above. At this time, the steps S ₂₄ to _{S 26} described above,
Steps _S44 to _S46 corresponding to _S32 , _S33 , _S28 to _S31 ,
Each of the processes S ₅₂ , S ₅₃ , S ₄₈ to _{S 51} is executed, and the data of the return mark is stored in the upper 8 bits of the address.

To input a rest, do the same thing in step S ₄₄ .
~ _S46 , _S52 , _S54 , _S55 , _S48 ~ _S51 are executed.
As a result, the data for the rest is stored within the upper 8 bits.

FIG. 14B shows the state of the RAM 33 in which code information has already been stored in a plurality of steps as described above, and the contents of each register. That is,
The contents of the MS, ME, CS, FS, and FE registers are unchanged from those in FIG. 14A, but the CE register holds the address where the next data will be stored. and
The area between the CS and CE register addresses indicates a code area where code information is already stored, and the area from the address next to the CE register address to address 999 indicates an empty area.

On the other hand, when all the code information has been input, the end switch 19 is turned on and the end mark is input at the end. In this case, the above steps _S24 to _S26 ,
Steps _S44 to _S46 corresponding to _S32 , _S34 , _S36 to _S39 ,
Each process of _S52 , _S54 , _S56 to _S59 is executed, and an end mark is stored at the next address following the last data of the code information. Then, through the processing in step _S59 , the CE register is incremented and the data is transferred to the FS register, and the process then proceeds to LOOP in the flowchart of FIG. This completes the writing process of the root note (special mark) in the chord information and its type of data to the RAM 33.

FIG. 14C shows the state of the RAM 33 and the contents of each register at this point. In this case, there is still an empty area, and the RAM 33 is not used until address 999.

Melody information is transferred to RAM33 as described above.
When the input of a series of data excluding each tone length data of the chord information is completed, the address of the RAM 33 is returned to address 0, and each tone length data of the melody information and chord information is stored in the lower 8 bits of each address. Although a detailed explanation of the operation in this case will be omitted, as mentioned above, the one-key play switches 25A, 25
Use B.

Next, with reference to FIGS. 15 and 16, a detailed explanation will be given of the operation when automatic performance is performed using the melody information and chord information preset in the RAM 33 as described above.

When automatic performance starts, steps _S61 and _S62 of the flowchart shown in Fig. 15 are executed, and the data in the MS register is transferred to the MC register, and the data in the CE register is transferred to the CC register. be done. As mentioned above, address 0 is stored in the MS register (Figure 11, step _S21 ), and the end mark is stored in the CE register.
The address of the RAM 33 where END is stored is stored (FIG. 13, step _S58 ), and as a result, the MC register stores address 0, and the CC register stores the address for the end mark END.

Step S ₆₃ is then executed via LOOP3,
The melody timer 31 is initialized.
That is, the time measured by the melody timer 31 becomes 0. Next, in step _S64 , the RAM 33 is addressed by the data address 0 of the MC register, and the melody information (1 word = 16 bit data) stored at address 0 of the RAM 33 is read out and given to the CPU 30. As a result, the CPU
In step S 30, the judgment process of step S ₆₅ is executed.
It is determined whether the read melody information is data indicating a note name, pitch range, note length, or other special mark data. If the data indicates the note name, range, and note length, the process advances to step _S66 and the CPU
30 outputs a corresponding scale code and gives it to the melody sound generation section 34, and similarly executes steps _S67 and _S68 , and the CPU 30 outputs an octave code and an attack signal, respectively, and gives them to the melody sound generation section 34. As a result, the melody sound generating section 34 starts creating musical tones of the given scale code, and causes the sound emitting section 5 to emit the sound. At the same time, the melody timer 31 in the CPU 30 starts timing.

Thereafter, the CPU 30 performs the process of step _S69 , that is, compares the time measured by the melody timer 31 with the note length data input from the RAM 33, and determines whether or not they match. It is determined whether or not the melody time has elapsed. And until the melody time elapses,
Proceed to step _S70 . That is, the chord automatic performance process shown in the flowchart shown in FIG. 16 is performed,
First, in step _S100 , data at the address indicated by the CC register is read from the RAM 33. Then RAM
33, the end mark END stored at the end of the code information is read out, this is determined in step _S101 , and the process returns to step _S69 .

That is, until the melody time of the musical tone elapses, the steps S ₆₉ , S ₇₀ (S ₁₀₀ , S ₁₀₁ ), S ₆₉ , . . .
Each process is repeated. Then, when the above melody time has elapsed, the CPU ₃₀
outputs a release signal and generates a melody sound generator 34.
give to As a result, the creation of the musical tone is stopped and the tone is muted.

Next, the process proceeds to step _S75 , where the MC register is incremented, and in this case becomes address 1. Next, the process advances to step _S81 , and after the above-mentioned steps _S100 and _S101 are executed, the process returns to LOOP3.

As mentioned above, the note name, range,
If each note length data is read out, and if no code information other than the end mark END is read out at that time, the steps _S63 to _S71 described above are performed.
S ₇₅ , S ₈₁ , S ₆₃ , ... are repeated.

If the rest data is read out from the melody information in the RAM 33 by the processing in step _S64 , the step
The process advances to step _S72 via _S65 , and the rest data is detected. Therefore, the CPU 30 does not output a musical tone generation instruction to the melody sound generating section 34, and at the same time causes the melody timer 31 to start timing operation. Then, by the processing in step _S73 , the CPU 30
is the time measured by the melody timer 31 above.
It compares the rest length data from the RAM 33 and determines whether the rest time has elapsed. If the rest time has not elapsed, proceed to step _S74 ,
Executes automatic chord performance processing.

That is, the process proceeds to step _S100 . If the code information has not yet been read from RAM33, that is, the data in the CC register has reached the end mark.
If the address of END remains, step S ₁₀₀ ,
_S101 is executed and the process returns to step _S73 . Then, until the above rest time has elapsed, the step
The processes of S ₇₃ , S ₇₄ (S ₁₀₀ , S ₁₀₁ ), S ₇₃ , etc. are repeated. Then, when the rest time has elapsed, the above steps will be executed.
The process advances to _S75 and then returns to LOOP3 via step _S81 .

If the rest data is read from the RAM 33 as described above, and if no code information other than the end mark END is read at that time,
The above steps _S63 to _S65 , _S72 to _S75 , and _S81 are executed.

If the synchro start mark is read out from the melody information in the RAM 33 through the processing in step _S64 , the process proceeds to step _S80 via steps _S65 , _S72 , and _S76 .
The synchro start mark is detected. As a result, the process advances to step _S82 and the data in the CS register is transferred to the CC register. That is, RAM33
The start address of the code information within is stored in the CC register. Then proceed to step _S83 ,
Automatic performance based on the chord information starts.

That is, the steps in the flowchart of FIG.
Proceed to _S106 and start the code timer 32 in the CPU 30.
is initialized. Next, in step _S107 , the first data of the code information (1
(words) are read out and given to the CPU 30.
The CPU 30 then executes the process of step _S108 ,
That is, it is determined whether the read data indicates the root note and its type. Assuming that the data indicates the root note and its type, the process proceeds to step _S109 , where the CPU 30 converts the input data into a scale code and an octave code, and then sends the scale code and octave code to the accompaniment sound generator 35. Give (steps S ₁₁₀ , S ₁₁₁ ). Further, an attack signal is outputted and given to the accompaniment sound generation section 35. As a result, accompaniment tones begin to be created and emitted, and the chord timer 32 starts to measure time.

Next, in step _S84 , the MC register is incremented, and then the process returns to step _S63 via LOOP3, where the melody timer 31 is reset. Then, according to the contents of the MC register above,
The next melody information is read from the RAM 33.
Assuming that the melody information is data on the note name, pitch range, and note length, steps _S65 to _S68 are executed to start emitting the melody tones. That is,
This melody sound is emitted along with the accompaniment sound. While it is determined in step _S69 that the melody time has not elapsed, the process proceeds to the next step _S70 .

In this case, if you proceed to step S ₁₀₀ ,
The data in the CC register does not address the end mark END, but the chord information that stores the root note and its type.
The process proceeds to step _S102 via _S101 . In step _S102 , while the CPU 30 determines that the chord time has not elapsed by comparing the time measured by the timer 32 and the note length data inputted together with the root note and its type data, , and then returns to step _S69 .

In this way, while neither the melody time nor the chord time has elapsed, steps S ₆₉ and S ₇₀ are executed.
( _S100 to _S102 ) are repeated, and the melody sound and accompaniment sound are emitted simultaneously. For example, if the melody time has elapsed first, the process proceeds from step _S69 to step _S71 , where the melody sound is muted, and then proceeds to step _S81 via step _S75 . Then, the process returns to step ₆₃ via steps _S100 to _S102 and LOOP3. As a result, the melody timer 31 is reset in preparation for creating the next melody sound, and thereafter steps _S64 , _S65 , etc. are executed.

On the other hand, if the chord time has elapsed while the melody sound and accompaniment sound are being emitted simultaneously, step _S103 is performed next in step _S102 .
Then, it is determined whether the accompaniment tone has actually been emitted up to that point, that is, whether the chord information up to that point is data on the root note, its type, and note length, or a special mark. . Assuming that an accompaniment tone is being emitted, which includes the data of the root tone, its type, and note length, the process proceeds to step _S104 , where the CPU 30 outputs a release signal to the accompaniment tone generator 35.
The above accompaniment sound is muted. Then, in step _S105 , the CC register is incremented to prepare for reading the next code information.

That is, steps _S106 and _S107 are executed, the code timer 32 is reset, and the next code information is
Read from RAM33.

If rest data is read out as chord information in the above-mentioned state, then the above steps are performed.
The process proceeds to step _S113 via _S106 , _S107 , and _S108 .
Then, it is determined that the rest data has been read and the CPU 3
0 does not instruct the accompaniment sound generator 35 to generate musical tones, thus prohibiting the generation of accompaniment sounds, and sets the chord time for rest data to the chord timer 32.
time. Then, for example, when returning to step _S69 , the process continues until the melody time of the melody sound currently being emitted or the chord time of the rest data of _the accompaniment sound elapses.
Repeat S ₇₀ (S ₁₀₀ , S ₁₀₁ , S ₁₀₂ ).

If the chord time for the accompaniment note rest data has elapsed, this is determined in step _S102 , and the process then proceeds to step _S103 . In step _S103 , it is determined that the accompaniment tones thus far have been rest data, and the process immediately proceeds to step _{S105 without going through step S104 ,} where the CC register is incremented. Then, reading of the next code information is started.

When the end mark END is read out as code information in the above state, steps S106 to _S106 are performed.
The process advances to step _S114 via _S108 and _S113 , and reading of the end mark END is detected. As a result, the CPU 30 will no longer instruct the accompaniment sound generating section 30 to generate musical tones, and therefore prohibits creation and emission of accompaniment sounds. And for example step S ₆₉
Then proceed to steps S ₆₉ , S ₇₀ (S ₁₀₀ , S ₁₀₁ )
is repeated, and only the melody sound is emitted.

On the other hand, if the end mark END is read from the melody information, the above steps S ₆₃ , S ₆₄ , S ₆₅ ,
Proceed to step ₆ via S ₇ S ₇₂ and the end mark
Reading of END is determined. And step S ₇₇
Then, it is determined whether the contents of the chord information addressed by the data in the CC register are the root note, its type, and note length data, that is, whether an accompaniment tone is being emitted at that time. For example, if the accompaniment sound has already ended and no sound has been emitted, the process proceeds to step _S2 via LOOP in the flowchart of FIG. 9, and the automatic performance ends. On the other hand, if the accompaniment sound is still being emitted, the step
After the process of _S79 is executed, the CPU 30 outputs a release signal to the accompaniment sound generating section 35 to immediately mute the accompaniment sound. That is, when the melody sound ends before the accompaniment sound, it is designed to prevent only the accompaniment sound from being emitted, giving a sense of discomfort.

In the above description, the melody information is first stored in the RAM 33, and then the chord information is stored next, but the reverse is of course possible. In addition, a synchronized start mark for starting the accompaniment sound is stored in the melody information, so that after the automatic performance starts, the melody sound is emitted first, and the synchronization starts while the melody sound is being emitted. When the mark is read out, the accompaniment sound is started to be emitted from that point and is emitted along with the melody sound, thereby creating a melody-first type, but it is of course possible to use the reverse accompaniment sound-first type. That is, a synchronized start mark for starting the melody sound is stored in the code information, and after reading this synchronized start mark, the emission of the melody sound is started.

Furthermore, without storing any of the above synchronized start marks in the RAM 33, the melody information and chord information are simply stored, and an external operation switch is provided, so that, for example, the melody information is read out and the melody is automatically played. When the external operation switch is turned on during execution, reading of the chord information may be started from that point on, and both the melody tone and the accompaniment tone may be automatically played. Of course, on the contrary, the melody sound may be started when the external operation switch is turned on while the accompaniment sound is being automatically played.

Furthermore, in the above embodiment, only one set of melody information and chord information is stored in the RAM, but the number is not limited to this, and it is of course possible to store two or more sets. etc. may be provided. Further, one piece of chord information may be used in combination with a plurality of pieces of melody information, and of course, the reverse may be used.

As explained above, the present invention provides an automatic performance device capable of performing automatic performance based on performance information of a plurality of parts set by a user, in which performance information of each part of the plurality of parts is inputted one by one by an input means. When the performance information of the first part is input and stored in the storage means, the address of the storage means at that time is stored when the storage of the performance information of the first part is completed, and after that, the address of the performance information of the second part inputted by the input means is stored. Since the performance information is stored sequentially from the address corresponding to the stored address in the storage means, a wide variety of automatic performances consisting of a plurality of parts set by the user can be performed using a memory with a small storage capacity. It is possible to realize an automatic performance device that allows you to enjoy the music.

[Brief explanation of drawings]

FIG. 1 is an external view of an electronic musical instrument according to an embodiment of the present invention, and FIG. 2 is an autoplay control switch section 3A.
3 is a circuit block diagram of the electronic musical instrument, FIG. 4 is a configuration diagram of the RAM 33, FIG. 5 is a data configuration diagram of melody information, and FIGS. 6 A to D show note names, Figure 7 shows the data structure of code information; Figure 8 shows the content of coded data for chord types; Figure 9 is a flowchart explaining the main operating modes of the electronic musical instrument, and Figure 10 shows the initialization state of each register in the flowchart of Figure 9.
11 is a flowchart explaining the writing operation of data excluding note length data in melody information, and FIGS.
13 is a diagram illustrating the write operation of data excluding note length data in chord information, and FIGS. 14 A to C are the flowchart of FIG. 13. Figures 15 and 16, which show various writing states of the RAM 33 when a chart is executed, are flowcharts illustrating operations when performing an automatic performance using melody and chords. 2...Keyboard, 3...Control switch section, 3
A... Auto play control switch section, 4... Display section, 8... Memory play switch, 16A, 1
6B... Return switch, 17... Synchro start switch, 18... Rest switch, 19
...End switch, 21...Record code switch, 22...Record melody switch, 2
5A, 25B...One key play switch, 30
...CPU, 31...Melody timer, 32...
...Chord timer, 33...RAM, 34...Melody sound generation section, 35...Accompaniment sound generation section, 37...
...Speaker, MS, ME, MC, MR, CS, CE,
CC, CR, FS, FE...registers.

Claims (1)

[Scope of Claims] 1. An input means for inputting performance information, a storage means for storing the performance information input from the input means, and the storage means for the performance information of the first part inputted by the input means. address storage means for storing an address of the storage means corresponding to the last performance information among the performance information of the first part when the storage is completed; and a second address inputted from the input means. storage control means for sequentially writing the performance information of the first part and the performance information of the second part from the storage means from the address corresponding to the address stored in the address storage means of the storage means; an automatic performance device that automatically plays a piece of music composed of the first part and the second part by reading performance information in a time-sharing manner. 2. The storage means stores end information as one of the performance information, and the automatic performance means stops reading the performance information of the part to which the read end information belongs when the end information is read. An automatic performance device according to claim 1. 3. The storage means stores synchronization information as one of the performance information, and upon reading the synchronization information, the automatic performance means starts reading performance information of parts other than the parts to which the read synchronization information belongs. An automatic performance device according to claim 1, characterized in that: