JPH0460231B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to semiconductor integrated circuits, particularly digital semiconductor integrated circuits, and relates to functional tests and input DC
Concerning improvements to reduce the time required for testing.

[Technical background of the invention]

Tests to determine the acceptability of digital semiconductor integrated circuits include current consumption tests, input
There are DC tests, output DC tests, functional tests, AC tests, etc. Among these, the input DC test tests the voltage and current characteristics of the input buffer that supplies the signal from the signal input terminal to the inside of the integrated circuit, and the function test tests the logic function of the internal circuit. . Input DC tests on digital semiconductor integrated circuits are performed when the input signal is high level and low level.
It is carried out in two levels.

[Problems with background technology]

As mentioned above, since the signal at the input terminal is set to H level or L level during the input DC test, the internal circuit cannot be functionally tested during this period. Therefore, conventionally input
DC testing and functional testing are performed completely independently.

By the way, the above-mentioned input DC test is to connect the power supply inside the tester to each input terminal, measure the current flowing through this power supply line when the input signal is L level and H level, and check whether the measured value is the specified value. This is a test to see if it is. When this DC test is completed for all input terminals, a functional test is performed next.

The test time in this case is the time required for input DC test 2n・t1 (t1 is the time required for DC test at H level or L level of one input terminal, n is the total number of input terminals) This is the combined time of t2 and the time t2 required for the functional test. Here, if the number of power supplies corresponding to the number of input terminals is prepared on the tester side during the DC test, the time 2n·t1 required for this DC test can be reduced to 2·t1. However, recent ICs have an extremely large number of input terminals, approximately several hundred, and a tester equipped with a corresponding number of power supplies would be extremely expensive and impractical. Therefore, in the past, it was common to test ICs using a tester equipped with one or two or three test power supplies.
Therefore, as the number of input terminals increases, the time required for testing increases.

In this way, in the past, input DC tests were performed independently from functional tests, so
The disadvantage is that the test time, especially the input DC test and functional test, is long.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to shorten the time required for these tests compared to conventional methods by conducting input DC tests and functional tests in parallel. The objective is to provide a semiconductor integrated circuit that can perform

[Summary of the invention]

In order to achieve the above object, this invention includes:
n first input buffers to which a functional test signal of one bit out of n bits or an input DC test signal are respectively supplied, and a first input buffer to which the input DC test signal is supplied. A second input buffer to which a functional test signal of the bit to be supplied is supplied, and either one of the output signals from each of the n first input buffers and the output signal from the second input buffer signal. ,n
It is equipped with n selection circuits that guide the inside of the integrated circuit based on the control signals corresponding to the bits, and the function test signal that should originally be input from the first input buffer where the input DC test is being performed. By inputting from the second input buffer, the input DC test and the functional test can be performed in parallel.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit according to the present invention.
FIG. 2 is a circuit diagram showing the configuration of only an input circuit section. In the figure, 21 ₁ to 21 _o and 22 are signal input terminals, respectively. Corresponding input terminals of inverters 23 ₁ to 23 _o as input buffers are connected to each of the signal input terminals 21 ₁ to 21 _o . Further, an input terminal of an inverter 24 serving as an input buffer is connected to the signal input terminal 22. The output signals of the inverters 23 ₁ to 23 _o are supplied to corresponding selection circuits 25 ₁ to 25 _o , and the output signals of the inverter 24 are supplied in parallel to the selection circuits 25 ₁ to 25 _o .

Each of the selection circuits ₂₅₁ to _25o selects one of the output signals of the inverters ₂₃₁ to _23o and the output signal of the inverter 24, depending on the logic level of the corresponding one of the n-bit test signals 1 to n. These selection circuits 25 each selectively output one of the two.
AND gates 31, 32 and both AND gates 3
It is composed of a NOR gate 33 to which output signals 1 and 32 are supplied in parallel.

One of the AND gates 31 is directly supplied with the output signal of the corresponding inverter 23, and the corresponding one of the n-bit test signals ₁ to n is supplied via each of the n inverters 261 to _26o . The other AND gate 32 is supplied with the output signal of the inverter 24 and corresponding one of the n-bit test signals 1 to n, respectively.

Next, the operation of the circuit configured as described above will be explained using the timing chart shown in FIG.

First, only test signal 1 is set to H level, and the remaining test signals 2 to n are all set to L level.
Since the test signal 1 is at the H level, the output signal of the inverter ₂₆₁ is at the L level. Therefore, in the selection circuit 25 ₁ , the AND gate 31 is disabled and the AND gate 32 is enabled. Therefore, this selection circuit 25 ₁ selectively outputs the output signal from the inverter 24 . On the other hand, since the remaining test signals 2 to n are all set to L level and all the output signals of inverters ₂₆₂ to _26o are set to H level, selection circuit 2
AND gates 31 within 5 ₂ to 25 _o are enabled and AND gates 32 are disabled. Therefore, in these selection circuits 25 ₂ to 25 _o , the output signals from each inverter 23 are selectively output.

In such a state, the input terminal ₂₁₁ has a DC signal which is alternately set to H level and L level.
In addition to supplying test signals, input terminal 2
Corresponding signals from the _2nd bit to the nth bit of the n-bit function test signal are supplied to 1 2 to 21 _o , respectively, and another input terminal 2
2 is supplied with the first bit functional test signal that should originally be supplied to the input terminal ₂₁₁ .

The selection circuit ₂₅₁ selects and outputs the output signal of the inverter 24 to which the 1st bit function test signal is supplied, and the remaining selection circuits ₂₅₁ to _25o select the 2nd to nth function test signals. Since the output signal of the inverter 23 to which the signal is supplied is selectively output, all of the above n-bit function test signals are selectively output by these n selection circuits 251 to _25o , and the system input signals 1 to ₂₅ are selectively output. n to the internal circuit. Therefore, at this time, these system input signals 1
to n can be used to perform a functional test of the internal circuit.

On the other hand, if the DC test signal is alternately set to H level and L level in this state, the input signal of inverter ₂₃₁ as an input buffer is alternately set to H level and L level. Therefore, at this time, in parallel with the above functional test, the tester (not shown) detects that the input signal of the inverter ₂₃₁ is H.
Perform input DC test in level and L level states.

When the DC test of the inverter ₂₃₁ is completed, only test signal 2 is set to H level instead of test signal 1. Test signal 2
is at H level, the selection circuit ₂₅₂ selectively outputs the output signal from the inverter 24. On the other hand, the remaining test signals 1 and 3 to n
are all set to L level, so the selection circuit 25
₁ , ₂₅₃ to _25o , the output signals from each inverter 23 are selectively output.

In this state, the signal input terminal 21 ₂
is set alternately to H level and L level.
In addition to supplying the DC test signal, the signal input terminals 21 ₁ and 21 ₃ to 21 _o are supplied with the corresponding signals from the 1st and 3rd bits to the nth bit of the n-bit functional test signal, respectively. However, to yet another input terminal 22, a signal for the second bit function test, which should originally be supplied to the input terminal ₂₁₂ , is supplied.

The selection circuit ₂₅₂ selects and outputs the output signal of the inverter 24 to which the 2nd bit function test signal is supplied, and the remaining selection circuits ₂₅₁ and _{253 to 25o} select the 1st bit and the 3rd bit to n. Since the output signal of each inverter 23 to which the bit-th function test signal is supplied is selectively output, the n-bit function test signal is selectively output by these n selection circuits ₂₅₁ to _25o , The signals are routed to internal circuits as system input signals 1 to n. Therefore, it is possible to perform a functional test of the internal circuit using these system input signals 1 to n.

Similarly to the above, if the DC test signal is alternately set to H level and L level in this state, the input signal of inverter 23 ₂ as an input buffer is alternately set to H level and L level. Therefore, in parallel with the functional test at this time, a tester (not shown) performs an input test when the input signal of the inverter ₂₃₂ is at H level and L level.
Perform a DC test.

Thereafter, similarly, test signals 3 to n are sequentially set to H level, and a DC test signal is supplied to the input terminal 21 of the bit corresponding to this test signal to perform an input DC test of the inverter 23 of that bit. By supplying the function test signal that should originally be supplied to the input terminal 21 during which the DC test is being performed to the input terminal 22, the n-bit function test signal is supplied to the internal circuit. Perform functional testing in parallel with testing.

When the DC test for the n input terminals 21 is completed, all test signals 1 to n
is set to L level, and the input terminals 21 ₁ to 21
Corresponding signals among the n-bit function test signals are supplied to the input terminal 22, and DC test signals alternately set to H level and L level are supplied to the input terminal 22. As a result, a DC test of the inverter 24 is performed in parallel with the functional test.

If the functional test has not yet been completed at the time when the input DC test on all inverters 23 and 24 has been completed, then only the functional test is performed as shown in the timing chart of FIG. Furthermore, if the functional test has already been completed when the DC test is completed, the DC test and functional test are completed at this point.

In this way, in the IC of this embodiment, when performing a DC test on one of the n input terminals 21, the function test signal that should originally be input from this input terminal 21 is replaced with an extra pre-provided signal. Since the n-bit system input signal is output from one input terminal 22 and is always supplied to the internal circuit, the input DC test can be performed in parallel with the functional test. Therefore, the time required for the test can be the longer of the functional test and the input DC test.If the time required for the functional test and the input DC test are the same, the test time is It can be approximately half the size of conventional ICs.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications are possible. For example, in the above embodiment circuit, the selection circuit 2
Although the case where the circuit 5 is configured with AND gates and NOR gates has been described, it goes without saying that this may be configured using other gate circuits.
Further, in the above embodiment, a case has been described in which the DC test of the inverter 24 is performed after the inverter 23, but the test sequence may be such that the DC test is performed before the inverter 23.

〔Effect of the invention〕

As explained above, according to this invention, the input
Since the DC test and the functional test are performed in parallel, it is possible to provide a semiconductor integrated circuit in which the time required for these tests is shorter than in the past.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an input circuit section of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a timing chart showing the operation of the above embodiment circuit. 21, 22...Signal input terminal, 23, 24...
Inverter (signal input means), 25... selection circuit (selection means), 26... inverter.

Claims (1)

[Scope of Claims] n first signal input means each supplied with a functional test signal of 1 bit out of 1 n bits or an input DC test signal;
a second signal input means to which a functional test signal of the bit to be supplied is supplied to the first signal input means to which a DC test signal is supplied; and an output of each of the n first signal input means. 1. A semiconductor integrated circuit comprising n selection means for guiding either the signal or the output signal of the second signal input means into the integrated circuit based on each n-bit control signal. 2. The semiconductor integrated circuit according to claim 1, wherein each of the n first signal input means and the second signal input means is constituted by an input buffer having a signal inversion function. 3. A first AND circuit in which the n selection means each control the output signal of the corresponding bit from the first signal input means according to the logic level of the control signal of the corresponding bit. , comprising a second AND circuit that controls the output of the output signal from the second signal input means, and an OR circuit to which the output signals of the first and second AND circuits are supplied in parallel. A semiconductor integrated circuit according to claim 1.