JPH046025B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] When a failure that is thought to be related to the TLB occurs, a TLB invalid mode operation is executed in which address translation is performed using a table without using the TLB. In this case, TLB is used as a means to temporarily hold the real address converted in the table until it is used. For this reason, a TLB valid bit is provided to perform control to temporarily validate the TLB.

[Industrial application field]

The present invention relates to an information processing device having a TLB as means for rapidly converting a logical address into a real address, and particularly relates to a control mechanism in TLB invalid mode.

[Conventional technology]

FIG. 3 shows the basic configuration of an address translation mechanism of an information processing device to which the present invention is applied.

In the figure, 31 is a logical address register, 32
is TLB, 321 is logical address LA, 322 is key, 323 is real address RA, 324 is entry, 33 is comparison section, 34 is dynamic address translation section, 35 is key check section, BS is buffer storage device, MSU is The main memory, STO, represents the segment table start address.

The address translation operation performed using this mechanism is as follows.

The logical address LA set in the logical address register 31 is first sent to the TLB 32 for reference. If a corresponding entry (address translation pair) is registered in the TLB, it is used to perform address translation at high speed.

The comparison unit 33 detects whether there is an entry with the same logical address in the TLB, and if there is a match, it outputs a hit, and if there is no match, it outputs a miss.

If a human is obtained in TLB32,
Key 322 in read entry 324
The key check unit 35 checks whether there is access protection, and if access is possible, the same entry 324
The real address RA323 inside is the buffer storage device.
It is sent to the BS or main storage MSU and access is executed.

Also, if there is a mistake in TLB32,
The logical address LA is sent to the dynamic address translation unit 34, and address translation processing using the segment table and page table is executed.

At this time, the physical address RA resulting from address translation by the dynamic address translation unit 34 and the original logical address LA are registered in the TLB 32, and at the same time, the key is fetched from the main storage device MSU using the real address RA. It is registered along with TLB32.

Next, use the original logical address LA to
See. This time it will be a TLB hit, so
The key of the corresponding entry 324 from TLB32
Read out the key 322 and check it with the key check unit 35. If it is accessible, its real address
Sends RA323 to BS or MSU to execute main memory access.

In this way, in the case of a TLB error, the result of address translation by the dynamic address translation unit 34 is
Main memory access is executed using the real address obtained by registering it in the TLB and re-referencing it.

By the way, the contents of the TLB 32 may be replaced when the purge TLB is executed due to paging, etc., but if for some reason the entry is incompletely cleared, the subsequent
TLB references may result in erroneous conversion output.

In such cases, information processing equipment uses TLB to stop using the TLB as a means of determining whether the cause of the error is caused by software or hardware.
A disabled mode is available.

There are two methods of operation in conventional TLB invalid mode:

The address translation section dynamically performs address translation every time the main memory is accessed, and the main memory is accessed using the translated real address. At this time, the converted real address is not registered in the TLB.

The dynamic address translation unit always performs address translation every time the main memory is accessed, and the translated real address is temporarily stored in a register. Next, the real address is used to fetch the key from main memory and perform a key check. If the result is that access is possible, main memory access is executed using the real address of the register.

[Problem that the invention seeks to solve]

In the conventional operation method in the TLB invalid mode described above, in the case of the method, the address after translation from the dynamic address translation unit is converted as shown in Figure 3.
Path for registering in TLB and main storage MSU
There is also the problem that a path is required for data transfer, the control is different from that in normal mode, and key check is not possible.

In the case of the second method, there is a special register that temporarily holds the address after conversion, and a comparison circuit such as logical address and segment table start address STO to determine whether the address is the target address. There was a problem that .

[Means for solving problems]

In the present invention, the operation in the TLB invalid mode is based on the operation in the case of a TLB miss in the normal mode, and one entry in the TLB is temporarily used as a register to hold the address after conversion. It is what you use. However, control is required to temporarily enable the TLB, which is originally disabled.

For this reason, 1 bit of TLB valid bit is provided,
Normally leave it off.

When a TLB miss occurs when accessing main memory,
Address conversion is performed using a table, and the resulting data is registered in the TLB via a normal path,
Set the TLB valid flag on. and
After using the data registered in the TLB, reset the TLB valid bit to OFF.

FIG. 1 is a conceptual diagram showing the basic configuration of the present invention.

In the figure, 11 is a logical address register, 1
2 is TLB, 121 is logical address LA, 122 is key, 123 is real address RA, 124 is
125 is an entry, 14 is a dynamic address translation unit, and 16 is a TLB valid flag.

A logical address LA is set in the logical address register 11 when a main memory access request occurs.

One entry 125 of the TLB 12 includes an address translation pair consisting of a logical address LA 121 and a real address RA 123, a key 122, and an intra-TLB valid flag 124 indicating validity/invalidity of the entry itself.

The dynamic address translation unit 14 detects a TLB reference failure,
That is, when a TLB miss occurs, address translation is performed using the segment table and page table. In main memory access during TLB invalid mode operation, address translation is always performed by the dynamic address translation unit 14.

The TLB valid flag 16 is a flag unique to the present invention, and when operating in TLB invalid mode, the TLB12
Used for control to temporarily enable use. The TLB valid flag 16 is reset to off when TLB invalid mode is specified.

The TLB valid flag 16 is set on when an address translation request is made to the dynamic address translation unit 14 due to a TLB miss. Then, the dynamic address translation unit 14 performs address translation and converts the result into
It is temporarily held in TLB12, the next TLB reference becomes a hit, and main memory access is executed, but
When the use of the TLB entry is completed, the TLB valid flag 16 is reset to OFF.

An address translation request due to a TLB miss occurs when the TLB valid flag is off, or when the TLB valid flag is on but the in-TLB valid flag of the entry is off.

When the TLB valid flag is on and the TLB internal valid flag of the entry is also on, it is determined that the TLB reference is successful, that is, a TLB hit.

[Effect]

The operating procedure of the configuration of the present invention shown in FIG. 1 in the TLB invalid mode is performed as follows.

First, when a main memory access request occurs, the logical address LA of the logical address register 11 is
It is transferred to TLB12 and referenced, but at that time,
or is executed depending on whether the TLB valid flag 16 is off or on.

In the initial state, since the TLB valid flag 16 is off, a TLB miss occurs, and the address translation by the dynamic address translation unit 14 is always performed.

' At this time, the TLB valid flag 16 is set on.

The dynamic address translation unit 14 executes address translation. The address translation result is registered in entry 125 of TLB12. At the same time, the key corresponding to the real address RA is retrieved from the main memory.
Fetch the key and register it.

' At this time, registered entry 125
The intra-TLB valid flag 124 is set on.

Execute the TLB reference operation again and check the TLB valid flag 16. Since this flag has already been turned on in ', entry 125 is read from TLB12.

Since the valid flag 124 in the TLB of the read entry 125 is turned on at ',
The key 122 is checked, and if the main memory can be accessed, the real address RA is transferred to the buffer storage or main storage.

' At this time, the TLB valid flag 16 is reset to OFF.

An access operation is performed using the buffer storage device or the main storage device.

As described above, each time the main memory is accessed,
TLB 12 is validly used only once.

〔Example〕

FIG. 2A is a configuration diagram of one embodiment of the present invention,
FIG. 2B is a timing diagram showing the operation.

In FIG. 2A, elements 11, 12, 121 to 125, 14, and 16 are the same elements as in FIG. 1, and 13 represents a comparison section, 15 represents a key check section, and 17 represents an AND circuit. There is.

Note that the explanation of the operational functions of each of the above elements explained in FIG. 1 will be omitted here to avoid duplication.

Further, the operating functions of the comparison section 13 and the key check section 15 are different from those of the comparison section 3 of the conventional example explained in FIG.
3 and the key check section 35.

In operation in the normal mode, the comparator 13
It is transferred from the logical address register 11 and read from the logical addresses LA and TLB12. Compare the logical address LA of each entry 125, and if a match is found, the TLB hit is set, and if there is a mismatch, the TLB hit is
Outputs TLB miss.

In addition, in the operation in the TLB invalid mode, when the output of the AND circuit 17 is "1", the comparator 13
Outputs a TLB hit, and outputs a TLB miss when it is “0”.

One of the two inputs of the AND circuit 17 is the content A of the TLB valid flag 16, and the other is the content B of the intra-TLB valid flag 124 of the TLB entry.
Therefore, TLB hits in TLB invalid mode are represented by A and B, and TLB misses are represented by +.

With this, when either the TLB valid flag 16 or the TLB internal valid flag 124 is off,
When a TLB miss occurs and both the TLB valid flag 16 and the TLB internal valid flag 124 are on, the TLB
Humans arise.

When a TLB miss occurs, the logical address is sent to the dynamic address translation unit 14 and address translation is executed. Also, when a TLB hit occurs, the real address RA read from the TLB is transferred to the buffer storage device BS.
TAG or main storage MSU.

Next, the operation will be explained according to the timing chart shown in FIG. 2B.

First, at _t1 , the logical address LA is set in the logical address register 11, and a main memory access request is made. However, in the TLB reference, since the TLB valid flag 16 is off, a TLB miss occurs. t ₂
The dynamic address translation unit 14 sequentially fetches the segment table and the page table until t ₆ to obtain the page frame real address PFRA.

PFRA and byte index BX at t ₆
Write to TLB12. At this time, the TLB internal valid flag 124 is set on.

Perform TLB reference again at t ₇ . This time there is a TLB hit, so at _t8 the buffer storage device BS is read, main memory access is executed, and the TLB valid flag 16 is reset to OFF.

The above operations are repeated.

〔Effect of the invention〕

According to the present invention, a 1-bit
With a slight increase in hardware by simply providing a TLB valid flag, the basic control of normal mode and TLB invalid mode can be shared and executed, simplifying the configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 A is a configuration diagram of one embodiment of the present invention, FIG. 2 B is an operation timing diagram of the embodiment shown in FIG. 2 A, and FIG. 3 is a conventional diagram. It is a block diagram of an example. In Figure 1, 11: Logical address register, 1
2: TLB, 14: Dynamic address translation unit, 16:
TLB valid flag, 121: Logical address LA, 1
22: Key, 123: Real address RA, 12
4: Valid flag in TLB, 125: Entry.

Claims (1)

[Claims] 1. TLB 12 for performing address translation at high speed
In an information processing device having
TLB valid flag 1 indicating overall validity or invalidity
6 is provided, and the early TLB valid flag 16 is set on when main memory access fails to refer to the TLB and address translation is requested, and when main memory access fails to refer to the TLB, address translation is requested.
It is reset to OFF when the TLB reference is successful and the main memory access is completed. Also, when accessing the main memory, if the TLB valid flag 16 is OFF, or if the TLB valid flag 16 is ON and the TLB internal valid flag 124 is If it is off, address translation is requested as a TLB reference failure, and if the TLB valid flag 16 is on and the TLB internal valid flag 124 is on, the address in TLB 12 is used as a TLB reference success, and each main memory access is performed. Perform address translation to
A TLB control method characterized by performing TLB disabled mode operation.