JPH0460348B2 - - Google Patents
Info
- Publication number
- JPH0460348B2 JPH0460348B2 JP59247944A JP24794484A JPH0460348B2 JP H0460348 B2 JPH0460348 B2 JP H0460348B2 JP 59247944 A JP59247944 A JP 59247944A JP 24794484 A JP24794484 A JP 24794484A JP H0460348 B2 JPH0460348 B2 JP H0460348B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- connection layer
- cap
- sealing
- inward
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/60—Seals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は内部に搭載した半導体素子をはんだ材
を使用して気密封止する半導体パツケージの封止
構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a sealing structure for a semiconductor package in which a semiconductor element mounted therein is hermetically sealed using a solder material.
従来、半田あるいは金スズ共晶半田を使用して
気密封止するものとしては、たとえば第５図に示
す如くパツケージ基板２の中央凹部２ａに半導体
素子３を取付けたのち、上記パツケージ基板２の
両側突起部２ｂの上面に接続層４′を形成し、こ
の接続層４′上にはんだ５を載置し、さらに上面
に上記接続層４′と同一大きさの接続層４を形成
したキヤツプ１を載置し、ついで加熱により上記
はんだ５を溶融して上記パツケージ基板２と、キ
ヤツプ１とを封止するものが実施されている。然
るに上記の構成においては、上記はんだ５の溶融
時に上記キヤツプ１がソリを発生し、これにより
上記突起部２ｂの上面と、キヤツプ１とのギヤツ
プが不均一になつて封止に必要なはんだ５の量が
変化して余剰となるはんだが表面張力と、半導体
素子３を取付け凹部２ａに落下する力との釣り合
いを保持できなくなると、封止時にはんだ５から
発生するはんだくずが上記凹部２ａに落下して半
導体素子３を短絡することになる。また、従来実
公昭58−24446号公報に記載されているように、
パツケージ基体と、キヤツプとの間に介挿された
接続層が上記パツケージ基体と、キヤツプとによ
つて形成される気密空間部に露出しないように上
記接続層と、上記気密空間部との間に接続層とは
異なる金属を設け、これによつて封止体の冷却時
の減圧によつてはんだくずが凹部内に飛び込むの
を防止するようにしたものが考案されている。然
るに上記の考案においては、上記キヤツプのソリ
によりキヤツプと、パツケージ基体とのギヤツプ
の変化による接続層の飛散防止については、何等
配慮されていない。すなわち、キヤツプにソリが
発生した場合、キヤツプと、パツケージ基体の上
面との間に隙間が発生するので、この隙間をはん
だくずが通つて凹部内に落下して半導体素子を短
絡する恐れがあるからである。さらに従来特開昭
58−155743公報に記載されているように、キヤツ
プの中央部を凸状に形成し、その周囲に鍔を設
け、これによつて接続層加熱時にはんだくずが表
面張力によつてキヤツプの中央部に行くのを防止
し、鍔部分に集められるようにしたものが発明さ
れている。然るに上記発明のようにセラミツクに
て形成されたキヤツプを上記の如く加工すること
は実際問題として容易に行なうことができない問
題がある。
Conventionally, when using solder or gold-tin eutectic solder to achieve hermetic sealing, for example, as shown in FIG. A cap 1 is formed in which a connection layer 4' is formed on the upper surface of the projection 2b, a solder 5 is placed on this connection layer 4', and a connection layer 4 having the same size as the connection layer 4' is formed on the upper surface. The package substrate 2 and the cap 1 are sealed by placing the package substrate 2 on the package substrate 2 and then melting the solder 5 by heating. However, in the above structure, the cap 1 warps when the solder 5 melts, and as a result, the gap between the top surface of the projection 2b and the cap 1 becomes uneven, and the solder 5 necessary for sealing becomes uneven. If the amount of solder 5 changes and the surface tension of the surplus solder cannot maintain a balance with the force of dropping the semiconductor element 3 into the mounting recess 2a, the solder waste generated from the solder 5 during sealing will fall into the recess 2a. It will fall and short-circuit the semiconductor element 3. In addition, as previously stated in Publication of Utility Model Publication No. 58-24446,
The connection layer inserted between the package base and the cap is placed between the connection layer and the airtight space so that it is not exposed to the airtight space formed by the package base and the cap. A device has been devised in which a metal different from that of the connection layer is provided to prevent solder waste from jumping into the recessed portion due to the reduced pressure when the sealing body is cooled. However, in the above-described invention, no consideration is given to preventing the connection layer from scattering due to a change in the gap between the cap and the package base due to warping of the cap. In other words, if warpage occurs in the cap, a gap will be created between the cap and the top surface of the package base, and there is a risk that solder waste may pass through this gap and fall into the recess, causing a short circuit in the semiconductor element. It is. In addition, the conventional Tokkai Sho
As described in Publication No. 58-155743, the center part of the cap is formed into a convex shape and a flange is provided around it, so that when the connection layer is heated, solder waste is drawn to the center part of the cap by surface tension. A device has been invented that prevents it from going to the tsuba and collects it in the tsuba area. However, as in the above-mentioned invention, there is a problem in that it is not easy to process a cap made of ceramic as described above.
本発明は上記に述べた従来の問題点を解決し、
簡単な構成にて、はんだのくずがパツケージ基板
に取付けられた半導体素子に付着して短絡するの
を防止し、かつ気密封止作業の歩留りの向上を可
能とする半導体パツケージの封止構造を提供する
ことにある。
The present invention solves the above-mentioned conventional problems,
Provides a semiconductor package sealing structure that has a simple configuration and prevents solder debris from adhering to semiconductor elements attached to the package board and causing short circuits, and also improves the yield of hermetic sealing work. It's about doing.
本発明は上記の目的を達成するため、基板上の
接続層を、キヤツプ側の接続層の位置より内方、
好ましくはキヤツプの内側面よりも内方に位置す
る如く配置し、キヤツプのソリによりキヤツプ
と、基板とのギヤツプが変化したため、はんだく
ずが内方に飛散するのを基板上の接続層に吸着さ
せてはんだくずの飛散を防止するようにしたこと
を特徴とするものである。
In order to achieve the above object, the present invention extends the connection layer on the board from the position of the connection layer on the cap side.
Preferably, the cap is placed inward from the inner surface of the cap so that solder chips scattered inward due to warping of the cap change the gap between the cap and the board are adsorbed to the connection layer on the board. This is characterized by preventing scattering of solder waste.
以下本発明の実施例を示す図面について説明す
る。第１図は本発明の一実施例を示す半導体パツ
ケージの封止構造を示す断面図、第２図はその封
止部を示す拡大断面図である。同図において６は
キヤツプにして、アルミナ等のセラミツクにて断
面が冂形状に形成され、その先端面に接続層７ａ
を固定している。８は基板にして、上記キヤツプ
６と同一材にて形成され、中央部には図示してい
ないが半導体素子を搭載し、その周囲には上記接
続層７ａに対して内方に位置し、かつ上記キヤツ
プ６の内周面６ａよりも内方に位置する如く対向
する接続層７ｂを固定している。９は錫鉛合金か
らなるはんだである。なお、上記両接続層７ａ，
７ｂのはんだ９の対向面には、タングステン等の
メタライズ処理を行なつたのち、ニツケル、金メ
ツキ等を施して、はんだ９がぬれ易いように形成
されている。上記の構成であるから、はんだ９が
溶融してそのはんだくずが内方に飛散しようとし
たとき、そのはんだくずを基板８側の接続層７ｂ
が吸着してこれ以上はんだくずが内方に飛散する
のを防止することができ、かつはんだ９が溶融時
の加熱から冷却するさいの温度変化によつて発生
する細かい小球状の固形物が表面張力によりキヤ
ツプ６の内側面６ａにそうて中央部に飛散するの
を防止することができる。またはんだ９を溶融す
るさいの加熱によりキヤツプ６にソリが発生して
キヤツプ６と、基板８とのギヤツプが変化したた
め、キヤツプ６と、基板８との間のはんだ９のく
ずが内方に飛散しようとしても上記に述べたと同
一作動により、はんだくずが基板８側の接続層７
ｂより内方に飛散するのを防止することができ
る。さらに基板８側の接続層７ｂの内端部上の、
キヤツプ６より内方に張り出したはんだ９の高さ
がキヤツプ６側の接続層７ａの下面よりも高い位
置にあるので、はんだ９の重力により該はんだ９
に穴あけ等の現象が発生するのを防止することが
できる。
The drawings showing embodiments of the present invention will be described below. FIG. 1 is a sectional view showing a sealing structure of a semiconductor package according to an embodiment of the present invention, and FIG. 2 is an enlarged sectional view showing the sealing portion thereof. In the figure, reference numeral 6 denotes a cap, which is made of ceramic such as alumina and has a cross-sectional shape, and has a connecting layer 7a on its tip surface.
is fixed. Reference numeral 8 denotes a substrate, which is made of the same material as the cap 6, has a semiconductor element (not shown) mounted in the center, and has a semiconductor element located inwardly with respect to the connection layer 7a around it, and The opposing connection layer 7b is fixed so as to be located inward from the inner circumferential surface 6a of the cap 6. 9 is a solder made of a tin-lead alloy. Note that both the connection layers 7a,
The surface of 7b facing the solder 9 is metallized with tungsten or the like and then plated with nickel or gold so that the solder 9 can easily wet the surface. With the above configuration, when the solder 9 melts and the solder waste is about to scatter inward, the solder waste is removed from the connection layer 7b on the board 8 side.
can be adsorbed and prevent further scattering of solder waste inward, and small spherical solids generated due to temperature changes when the solder 9 is heated to melted and cooled are removed from the surface. Due to the tension, it is possible to prevent the cap from falling against the inner surface 6a of the cap 6 and scattering to the center. Warpage occurred in the cap 6 due to heating during melting of the solder 9 and the gap between the cap 6 and the board 8 changed, so the scraps of the solder 9 between the cap 6 and the board 8 were scattered inward. Even if an attempt is made to do so, the same operation as described above causes solder waste to fall onto the connection layer 7 on the board 8 side.
It is possible to prevent the particles from scattering inward from b. Furthermore, on the inner end of the connection layer 7b on the substrate 8 side,
Since the height of the solder 9 protruding inward from the cap 6 is higher than the lower surface of the connection layer 7a on the side of the cap 6, the gravity of the solder 9 causes the solder 9 to
It is possible to prevent phenomena such as punctures from occurring.
つぎに第３図は本発明の他の一実施例を示す半
導体パツケージの封止構造を示す断面図である。
同図においては、キヤツプ６側の接続層７ａに固
定され、下端部がはんだ９内を上下方向に貫通し
て基板８側の接続層７ｂの上面に接触するスペー
サ１０を設けたもので、上記以外は第１図と同一
である。上記の構成であるから、キヤツプ６がス
ペーサ１０を介して基板８上に接続層７ｂ上に支
持され、キヤツプ６上に重り（図示せず）を搭載
しているので、上記スペーサ１０の外方位置のは
んだ９が溶融してもそのはんだくずがスペーサ１
０を通過して内方に飛散するのを防止することが
できる。またキヤツプ６のソリによつてキヤツプ
６と、基板８とのギヤツプが変化したため、スペ
ーサ１０の外方位置のはんだ９のくずがスペーサ
１０の下端部を通つて内方に飛散したとしても、
基板８上のスペーサ１０の内方位置の接続層７ｂ
上に吸着してそれ以上内方に飛散するのを防止す
ることができる。 Next, FIG. 3 is a sectional view showing a sealing structure of a semiconductor package showing another embodiment of the present invention.
In the figure, a spacer 10 is provided which is fixed to the connection layer 7a on the side of the cap 6, and whose lower end penetrates through the solder 9 in the vertical direction and comes into contact with the upper surface of the connection layer 7b on the side of the board 8. The rest is the same as FIG. 1. With the above configuration, the cap 6 is supported on the connection layer 7b on the substrate 8 via the spacer 10, and a weight (not shown) is mounted on the cap 6, so that the spacer 10 is Even if the solder 9 at the position melts, the solder waste will become the spacer 1.
0 and can be prevented from scattering inward. Furthermore, since the gap between the cap 6 and the board 8 changes due to the warping of the cap 6, even if the solder chips 9 located outside the spacer 10 scatter inward through the lower end of the spacer 10,
Connection layer 7b located inside spacer 10 on substrate 8
It can be adsorbed to the top and prevented from scattering further inward.
つぎに第４図は本発明のさらに他の一実施例を
示す半導体パツケージの封止構造を示す断面図で
ある。同図においては、基板８側の接続層１２ｂ
をその外側がキヤツプ１１側の接続層１２ａの外
側と一致し、その内側が上記接続層１２ａの内側
よりも内方になる如く形成し、かつ上記基板８上
に固定され、接続層１２ｂを上下方向に貫通して
はんだ１３の内側端部に接触するダム１３を設け
たものである。上記の構成であるから、はんだ１
３が溶融して内方に流れようとすると、先ずダム
１３により堰止められる。また一部上記ダム１３
より溢出したはんだくずは基板上８上のダム１３
の内方に取付けられた接続層１２ｂ（捨て接続層
または捨てパターンという）に吸着され、これ以
上内方に飛散するのを防止することができる。ま
たはんだ１３が２個の接続層１２ａ，１２ｂ間を
内方に円滑に流れるのを助長することができる。
従つて、たとえはんだ１３の加熱によつてキヤツ
プ１１にソリが発生し、これによりキヤツプ１１
と、基板８とのギヤツプからはんだくずが内方に
飛散しようとしても、上記ダム１３および内方の
接続層１２ｂによつてこれを防止することができ
る。 Next, FIG. 4 is a sectional view showing a sealing structure of a semiconductor package showing still another embodiment of the present invention. In the figure, the connection layer 12b on the substrate 8 side
is formed so that its outer side coincides with the outer side of the connecting layer 12a on the side of the cap 11, and its inner side is inward than the inside of the connecting layer 12a, and is fixed on the substrate 8, and connects the connecting layer 12b above and below. A dam 13 is provided that penetrates in the direction and contacts the inner end of the solder 13. Because of the above configuration, solder 1
3 melts and attempts to flow inward, it is first blocked by the dam 13. In addition, some of the above dams 13
The solder waste spilled out from the dam 13 on the board 8.
The particles are attracted to the connection layer 12b (referred to as a sacrificial connection layer or a sacrificial pattern) attached to the inner side, and can be prevented from scattering further inward. It is also possible to help the solder 13 smoothly flow inward between the two connection layers 12a, 12b.
Therefore, even if the solder 13 is heated, warping occurs on the cap 11, which causes the cap 11 to warp.
Even if solder chips try to scatter inward from the gap between the board 8 and the board 8, this can be prevented by the dam 13 and the inner connection layer 12b.
本発明は以上述べたる如くであるから、簡単な
構成にてはんだが接続金属より内方に飛散して半
導体素子に付着し、これによつて半導体素子が短
絡するのを防止することができ、かつ封止作業の
歩留りを向上することができる。
As described above, the present invention can prevent the solder from scattering inward from the connecting metal and attaching to the semiconductor element, thereby causing a short circuit in the semiconductor element, with a simple configuration. Moreover, the yield of sealing work can be improved.
第１図は本発明の一実施例を示す半導体パツケ
ージの封止構造を示す断面図、第２図はその封止
部を示す拡大断面図、第３図は本発明の他の一実
施例を示す半導体パツケージの封止構造を示す断
面図、第４図は本発明のさらに他の一実施例を示
す半導体パツケージの封止構造を示す断面図、第
５図は従来の半導体パツケージの封止構造を示す
断面図である。
１，１１……キヤツプ、２，８……基板、３…
…半導体素子、４，７ａ，１２ａ，４′，７ｂ，
１２ｂ……接続金属、５，９，１３……はんだ、
１０……スペーサ、１４……ダム。
FIG. 1 is a cross-sectional view showing a sealing structure of a semiconductor package according to an embodiment of the present invention, FIG. 2 is an enlarged cross-sectional view showing the sealing part, and FIG. 4 is a sectional view showing a sealing structure of a semiconductor package according to still another embodiment of the present invention, and FIG. 5 is a sectional view showing a sealing structure of a conventional semiconductor package. FIG. 1, 11... Cap, 2, 8... Board, 3...
...Semiconductor element, 4, 7a, 12a, 4', 7b,
12b... Connection metal, 5, 9, 13... Solder,
10...Spacer, 14...Dam.
Claims (1)
のパツケージ基板上の上記半導体素子の周囲に接
続層およびはんだを介して実装された気密封止用
キヤツプとよりなる半導体パツケージの封止構造
において、上記パツケージ基板上の接続層を、上
記気密封止用キヤツプ側の接続層に対して内方に
位置する如く設け、封止体冷却時の減圧により発
生するはんだの飛散を防止するように構成したこ
とを特徴とする半導体パツケージの封止構造。 ２ 前記パツケージ基板上に前記気密封止用キヤ
ツプ側の接続層に対向する如く配置された接続層
と、この接続層の内側に該接続層より上方に突出
するダムと、このダムの内側に配置された接続層
とを設けたことを特徴とする前記特許請求の範囲
第１項記載の半導体パツケージの封止構造。[Claims] 1. Sealing of a semiconductor package comprising a package substrate on which a semiconductor element is mounted, and an airtight sealing cap mounted around the semiconductor element on the package substrate via a connection layer and solder. In the structure, the connection layer on the package substrate is located inwardly with respect to the connection layer on the hermetically sealed cap side, so as to prevent solder from scattering due to the reduced pressure when cooling the sealing body. A sealing structure for a semiconductor package characterized by comprising: 2. A connection layer disposed on the package substrate so as to face the connection layer on the side of the airtight sealing cap, a dam protruding upward from the connection layer inside the connection layer, and a dam disposed inside the dam. 2. A sealing structure for a semiconductor package according to claim 1, further comprising a connecting layer having a cylindrical shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59247944A JPS61127150A (en) | 1984-11-26 | 1984-11-26 | Sealing structure of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59247944A JPS61127150A (en) | 1984-11-26 | 1984-11-26 | Sealing structure of semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61127150A JPS61127150A (en) | 1986-06-14 |
| JPH0460348B2 true JPH0460348B2 (en) | 1992-09-25 |
Family
ID=17170868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59247944A Granted JPS61127150A (en) | 1984-11-26 | 1984-11-26 | Sealing structure of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61127150A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101602278B1 (en) * | 2015-09-11 | 2016-03-10 | 주식회사 피플앤코 | Magnetic puff and compact with magnetic puff handle projecting out over case |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0649700A (en) * | 1992-07-31 | 1994-02-22 | Sumitomo Metal Ind Ltd | Continuous pickling device for band steel |
| JP4513513B2 (en) * | 2004-11-09 | 2010-07-28 | 株式会社村田製作所 | Manufacturing method of electronic parts |
| FR2949172B1 (en) * | 2009-08-13 | 2011-08-26 | Commissariat Energie Atomique | HERMETIC ASSEMBLY OF TWO COMPONENTS AND METHOD OF MAKING SUCH ASSEMBLY |
-
1984
- 1984-11-26 JP JP59247944A patent/JPS61127150A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101602278B1 (en) * | 2015-09-11 | 2016-03-10 | 주식회사 피플앤코 | Magnetic puff and compact with magnetic puff handle projecting out over case |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61127150A (en) | 1986-06-14 |
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