JPH046110B2 - - Google Patents

Description

Detailed Description of the Invention [Summary] The present invention provides an emitter side potential barrier layer consisting of a superlattice layer formed between an emitter layer and a base layer, and a base layer and a collector layer in a semiconductor logic circuit device. A storage active element having a collector-side potential barrier layer formed between the storage active element and the current source inserted between the base and emitter of the storage active element, and a current source inserted between the base and emitter of the storage active element; It has a configuration comprising means for selectively applying a signal to the base of the active element, the base side being controlled so that one of the two stable states of the storage active element can be selected at an intended time, and the collector From the side or emitsuta side,
By extracting a signal corresponding to either of the two stable states, the structure is simple and high-speed multistable logic operation is possible.

[Industrial application field]

The present invention relates to a semiconductor logic circuit device using a resonant-tunneling transistor (hereinafter abbreviated as RHET) as a storage active element.

[Conventional technology]

To date, many types of bistable semiconductor logic circuit devices (flip-flops with clock pulse terminals) that can transition between two stable states only when intended have been put into practical use, but their speed has increased. There is no end to the demand for higher integration. However, due to technological limitations in microfabrication, increased delay time due to increased wiring capacity, etc., the ability to meet the above requirements is gradually reaching a plateau. In order to overcome this,
It is necessary to increase the speed of the active elements themselves, provide new functions, reduce the number of elements, and increase the speed without impairing the function of the semiconductor logic circuit device. Incidentally, at least three transistors are required to construct a D flip-flop, which is one of the simplest semiconductor logic circuit devices as described above.

[Problem that the invention seeks to solve]

As mentioned above, in the future, one ideal form of bistable or even multistable semiconductor logic circuit devices is not only high speed but also one with a reduced number of constituent elements. However, the reason why such a bistable or even multistable semiconductor logic circuit device has not been realized is thought to be due to the lack of a storage active element suitable for constructing it. Therefore, the present invention provides a transistor that utilizes the resonant tunneling effect, for example.
By using RHET, we aim to obtain a multistable semiconductor logic circuit device that is simple in configuration and operates at high speed.

[Means for solving problems]

The present invention has an emitter-side potential barrier layer formed of a superlattice layer formed between an emitter layer and a base layer, and a collector-side potential barrier layer formed between the base layer and the collector layer. and a storage active element having a differential negative resistance region in the voltage-current characteristic between its base and emitter, and a storage active element connected between the base and emitter of the storage active element to cause the storage active element to take a plurality of stable states. a current source, a terminal that applies a signal to its base when specifying rewriting of the active storage element, and a signal that corresponds to one of the two stable states from the collector side or emitter side of the active storage element. The present invention provides a semiconductor logic circuit device characterized by comprising a terminal.

[Effect]

Transistors that utilize the resonant tunneling effect, such as RHET, have extremely high operating speeds, and can have differential negative characteristics in their base-emitter voltage-current characteristics as described above. Therefore, by controlling the base side, one of the two stable states of the storage active element can be selected when desired, and a signal corresponding to one of the two stable states is generated from the collector side or the emitter side. By taking out the circuit, a simple configuration and high-speed multistable logic operation are possible.

[Example] First, Fig. 2 shows a diagram used in an example of the present invention.
FIG. 2 is a diagram for explaining RHET, in which A is a cutaway side view of a main part, and B is an energy band diagram corresponding to diagram A.

In Fig. 2A, 1 is the n ⁺ type GaAs collector layer, 2 is the AlyGa _1-y As collector side potential layer.
3 is an n ⁺ type GaAs base layer, 4 is a superlattice layer, 5 is an n ⁺ type GaAs emitter layer, 6 is an emitter electrode, 7 is a base electrode, and 8 is a collector electrode. Moreover, in FIG. 2B, Ec indicates the bottom of the conduction band, EF indicates the Fermi level, and Ex indicates the energy level of the sub-band. The superlattice layer 4 is composed of an AlxGa _1-x As barrier layer 4A and a GaAs well layer 4B, and in the example shown, it is composed of two barrier layers and one well layer, but if necessary, Multiple well layers and barrier layers to form them may be used.

Figures 3A to 3D represent energy band diagrams to explain the operating principle of RHET,
The same symbols as those used in FIG. 2 are used to indicate the same parts or have the same meaning. In FIG. 3, Ex is the energy level of the sub-band generated in the well layer 4B, q is the amount of carrier (electron) charge, and φc is the amount of charge between the collector side potential barrier layer 2 and the base layer 3. conduction band bottom discontinuity value
discontinuity) and VBE indicate the base-energy voltage, respectively.

In Figure 3 A, the base-energy voltage VBE is 0.
This is an energy band diagram in the case of 0 or close to 0. In the illustrated state, the voltage VCE is applied between the collector and the emitter, but since the voltage VBE between the base and the emitter is almost 0, the energy level in the emitter layer 5 is lower than the sub-level in the well layer 4B. Since the energy level of the band is different from Ex, it is impossible for the electrons in the emitter layer 5 to tunnel through the superlattice layer 4 and escape to the base layer 3, and therefore there is no current in the RHET. It's not flowing.

Figure 3B shows that the base-emitter voltage VBE is
This is an energy band diagram in the case of almost equal to 2Ex/q. In the illustrated state, the energy band in the emitter layer 5 is equal to the energy level of the sub-band in the well layer 4B.
In order to match Ex, the electrons in the emitter layer 5 are injected into the base layer 3 through the superlattice layer 4 due to the resonance tunneling effect, where the potential energy (≒2Ex) is converted into kinetic energy, so that the electrons is in a so-called hot state, and the base layer 3
It passes through the varistake and reaches the collector layer 1.

However, if the collector barrier height is 2Ex
If it is made larger, most of the electrons will be blocked by the collector barrier, and will not become a collector current but a base current.

Figure 3C shows that the base-emitter voltage VBE is
This is an energy band diagram in the case of larger than 2Ex/q. In the illustrated state, the energy level in the emitter layer 5 is equal to that in the well layer 4.
Sub-band energy level Ex in B
Since the current becomes higher, the resonant tunneling effect does not occur, and no electrons escape from the emitter layer 5 to the base layer 3 again, and the current is reduced.

Figure 3D shows that the base-emitter voltage VBE is
This is an energy band diagram in the case of considerably larger than 2Ex/q. In the illustrated state, of the two barrier layers 4A, the energy level of the barrier layer 4A closer to the base layer 3 is lower than that of the emitter layer, so electrons are transferred to the barrier layer 4A closer to the emitter layer 5. Tunnel 4A directly. Furthermore, since the electrons at this time have sufficient energy to cross the collector barrier, they cross the collector barrier and reach the collector layer 1.

FIG. 4 is a diagram illustrating the relationship between base-emitter voltage VBE tunneling base current IB and collector current Ic in RHET as described above. In the figure, the horizontal axis represents the base-emitter voltage, and the vertical axis represents the base current IB and collector current Ic. As is clear from the figure, in the relationship between VBE and IB in RHET, there exists a differential negative resistance region due to the so-called resonance tunneling effect. Therefore, by utilizing this characteristic, it is possible to operate the RHET as an active storage element.

FIG. 1A is a circuit diagram of a main part for explaining the principle of a semiconductor logic circuit device according to the present invention, and FIG. 1B shows logic symbols representing the semiconductor logic circuit device of FIG. 1A. In the figure, QR is a storage active element which is RHET, QS is a switching element, RL is a negative resistance, RB is a current source resistance, D is an input terminal, Q is an output terminal, T is a clock terminal, Vcc1 and Vcc2.
indicate the positive current source level, respectively.

As shown in the figure, the positive current source level VCC1 is connected to the base of the storage active element QR through the current source resistor RB.
When connected to a power source that supplies As you can see. In the figure, the horizontal axis shows the base-emitter voltage.
VBE is taken, and the vertical axis is the base current IB.
CL is the characteristic line, load line when LL switching element QS is OFF, LLH is switching element QS
is the load line when QS is ON and the input is at a high level, LLL is the load line when the switching element QS is ON and the input is at a low level, and A, B, C, and D indicate the stable points, respectively. .

As is clear from the figure, when the switching element QS is in the OFF state (LL), the storage active element QR can maintain two stable states as seen at stable points A and B.

Switching element QS from OFF state (LL)
When transitioning from ON state to OFF state again, when the input is at a high level (LLH), the stable point is A.
Or transition from B to B via C. When the input is at a low level (LLL), the stable point transitions from A or B to A via D.

As described above, the switching element QS can cause the storage active element QR to transition from one of the two stable states to the other as seen at the two stable points A and B.

FIG. 5B shows the relationship between base-emitter voltage VBE and collector current Ic. In the figure, the horizontal axis represents the base-emitter voltage VBE.
On the same scale as Figure A, the vertical axis shows the collector current
IC is taken. Points E and F correspond to stable points A and B in FIG. 5A, respectively. At stable point B, a large amount of collector current (corresponding to F in Figure B) is flowing, so the collector level of storage active element QR becomes low due to load resistance RL, and at stable point A, Since only a small amount of collector current (corresponding to E in Figure B) is flowing, the collector level will be high.

As described above, it is possible to realize a bistable logic circuit that can make a transition from one of the two stable states to the other only when the switching element QS is turned on.

FIG. 6A shows a dynamic frequency divider circuit constructed using the bistable semiconductor logic circuit device according to the present invention, and FIG. 6B shows a static frequency divider circuit constructed using the bistable semiconductor logic circuit device according to the present invention. FIG. 2 is a main circuit diagram for explaining the principle of a frequency dividing circuit.
DF is the semiconductor logic circuit device, I is an inverter circuit, IN is an input, and OUT is an output.

Figure 7 shows the input IN, output OUT, connection point N ₁ or
A timing chart of the potential at N ₃ is shown.

As is clear from the figure, for the input signal IN,
It can be seen that the frequency of the output signal OUT is halved. According to the configuration of the above embodiment, the resonant tunneling effect generated in the RHET, which is an active storage element, can cause two stable states of the base to appear, and these two stable states can be expressed by a signal from the base side. A signal corresponding to the stable state can be taken out from the collector side or emitter side. Utilizing this, a bistable semiconductor logic circuit device is constructed that can transition states only when intended (only when a timing signal is applied to CP or T). Furthermore, the semiconductor logic circuit device according to the present invention, which conventionally required at least three transistors, can be realized by using only two transistors. Moreover, its operation is stable. Furthermore, by using one semiconductor logic circuit device as a dynamic frequency divider, or using two semiconductor logic circuit devices and two inverters, it is possible to easily configure a static frequency divider that operates from low frequencies to ultra-high frequencies. can do.

In the following, the embodiments of the present invention will be explained more specifically by giving the following constants to various elements constituting a semiconductor logic circuit device to cause them to perform logical operations, and by taking the output from the connection point N with a probe and observing it. The results are shown below.

RB: 1.5 [KΩ] RL: 10 [KΩ] Vcc1:1 [V] Vcc2:1 [V] The operation of this semiconductor logic circuit device, that is, the potentials at input terminal D, output terminal Q, and clock terminal CP. The timing chart is shown in FIG. 8, where the same symbols as those used in FIG. 1 indicate the same parts or have the same meanings.

From the illustrated potential waveform, it can be seen that the storage active element QR performs a bistable logic operation that can definitely change the state at the intended time.

In addition, in the above embodiment, the case where the quantum well has one level is shown, but it is possible to use a memory active element in which the quantum well has two or more levels and two or more differential negative resistance regions appear. In this case, there are three or more stable points, and accordingly, three or more collector current values can be detected.

In the above embodiment, as shown in FIG. 1A, a transfer gate transistor QS is inserted on the base side of the storage active element, and when a timing signal is applied to the gate, a D Although we have explained the example in which the input signal D is applied and the contents of the storage active element are rewritten, by directly connecting the input signal D to the base of the storage active element without providing the transistor QS, the input signal D itself can be rewritten at the intended rewriting timing. Alternatively, the voltage may be applied as follows. Furthermore, the storage active element applied to the present invention is
A structure including a plurality of quantum wells may be used, and although an example has been shown in which the collector barrier is configured with a heterojunction, it may also be configured with a PN junction barrier. Furthermore, although an element in which electrons undergo resonance tunneling is shown as a storage active element applied to the present invention, an element in which holes undergo resonance tunneling may also be used.

〔Effect of the invention〕

As described above, the semiconductor logic circuit device according to the present invention has an emitter-side potential barrier layer formed of a superlattice formed between an emitter layer and a base layer, and a memory active layer having a base layer and a collector layer. a current source connected between the base and emitter for causing the base of the active storage element to assume two stable states; The structure includes means for transitioning from one to the other at an intended time.

According to this structure, in the RHET storage active element, due to the resonance tunneling effect,
Since the base can realize two stable states, and these two stable states can be arbitrarily changed by a signal from the base side, by using only two active elements. ,
This enables bistable logic operation that allows state transitions at intended times, which is advantageous for higher integration and higher speed of semiconductor logic circuit devices.

[Brief explanation of drawings]

1A and 1B are a circuit diagram and a logic circuit diagram, respectively, for explaining the principle of a bistable semiconductor logic circuit device according to the present invention, and FIGS. 2A and 2B are respectively
A cross-sectional view of the main parts and an energy band diagram to explain the RHET, Figures 3A to 3D are energy band diagrams to explain the operating principle of the RHET, and Figure 4 is the base diagram.
A diagram showing the relationship between emitter voltage VBE, base current IB, and collector current Ic, Figures 5A and B
6A is a diagram showing the relationship between base-emitter voltage VBE and base current IB and a diagram showing the relationship between collector current Ic and FIG. and B are main part circuit diagrams for explaining a frequency divider using a semiconductor logic circuit device according to the present invention, and No. 7
This figure is a timing chart for explaining the operation of the static frequency divider of FIG. 6B, and FIG. 8 is a timing chart for explaining the operation of the semiconductor logic circuit device according to the present invention. 1...n ⁺ type GaAs collector layer, 2...Al _y Ga _1-y
As collector side potential barrier layer, 3...
n ⁺ type GaAs base layer, 4... superlattice layer, 5... n ⁺
type GaAs emitter layer, 6...emitter electrode, 7...
...Base electrode, 8...Collector electrode, QR...
Storage active element which is RHET, QS... switching element, RL... negative resistance, RB... current source resistance,
D...Input terminal, Q...Output terminal, T...Clock terminal, Vcc1 and Vcc2...Positive current source level.

Claims (1)

[Claims] 1. An emitter-side potential barrier layer consisting of a superlattice layer formed between an emitter layer and a base layer, and a collector-side potential barrier layer formed between a base layer and a collector layer. a storage active element having a differential negative resistance region in the voltage-current characteristic between its base and emitter; a current source for causing the active storage element to take a rewrite, a terminal for applying a signal to its base when specifying rewriting of the active storage element, and a terminal that corresponds to one of the two stable states from the collector side or the emitter side of the active storage element. 1. A semiconductor logic circuit device comprising a terminal for taking out a signal.