JPH0462472B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method suitable for manufacturing a heterojunction bipolar semiconductor device having a stacked structure of layers made of compound semiconductors.

Prior Art and Problems FIG. 1 is a cross-sectional side view of essential parts of a conventional heterojunction bipolar semiconductor device.

In the figure, 11 is _a semi-insulating _GaAs substrate, 12
is n ⁺ type G _a A _s collector contact layer, 13 is n
_{14 is a p-type Ga As base layer ;}
15 is an n-type AlG _a A _s with a large band gap.
16 is _an n-type _GaAs emitter layer, 17 is an emitter electrode, 18 is a base electrode, and 19 is a collector electrode.

When manufacturing this conventional example, _{the n-type GaAs emitter} layer 16 and _the n-type _AlGaAs layer 15 are selectively etched to expose the surface of _the p-type _GaAs base layer 14. The exposed p- _{type GaAs} base layer 14 and the n-type _{GaAs collector} layer 13 below it are selectively etched to form an n ⁺ type _{GaAs .} Collector contact layer 1
The surface of 2 is exposed, and the collector electrode 1 is placed on that surface.
It is necessary to form 9.

Therefore, in such a heterojunction bipolar semiconductor device, a considerable step is formed on the surface, which is the main cause of wiring disconnection.

OBJECTS OF THE INVENTION The present invention provides a method for manufacturing a heterojunction bipolar semiconductor device that can reduce the occurrence of the above-mentioned step difference and, as a result, prevent wiring from being cut. .

Structure of the Invention In the method for manufacturing a heterojunction bipolar semiconductor device of the present invention, 1. a semiconductor substrate (for example _, a semi-insulating _GaInAs substrate 1);
upper collector contact layer (e.g. n ⁺ type _Ga
A step of selectively forming a _collector electrode (for example, collector electrode 3) on the surface of collector contact layer 2), and then a step of forming an insulating film (for example, silicon dioxide film 4) covering the side periphery of the collector electrode. Then, using the collector electrode covered with the insulating film as a mask, a collector layer (for example, n-type _{GaAs )} is formed on the collector contact layer.
collector layer 5) and base layer (e.g. p-type _Ga
A _s base layer 6) and emitter layer (e.g. n-type
A step of sequentially stacking an AlGaAs layer 7 + _an n-type _GaAs emitter layer 8) and then selectively removing the emitter layer located in a portion where _a base electrode _is to be formed; An electrode (e.g. emitter electrode 9) and a base electrode (e.g. base electrode 10) on the base layer.
2. A step of selectively forming an emitter electrode on the surface of the emitter contact layer on the semiconductor substrate, and then an insulator covering the side circumference of the emitter electrode. A step of forming a film, and then, using the collector electrode covered with the insulating film as a mask, an emitter layer, a base layer, and a collector layer are sequentially laminated on the emitter/contact layer, and then the emitter layer is placed in the area where the base electrode is to be formed. and then forming a collector electrode on the collector layer and a base electrode on the base layer.

Therefore, even if the stacked semiconductor layer is etched to selectively expose a part of the base layer to form a base electrode, the resulting step difference will be slight, and Since the emitter (or collector) electrode is formed on the surface of the top layer of the stacked semiconductor layers, the overall level difference is reduced.
No wiring breaks occur.

Embodiment of the Invention FIGS. 2 to 6 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining an embodiment of the present invention, and the following description will be made with reference to these figures. do.

See Figure 2 (a) For _example , by applying the molecular beam epitaxy (MBE) method, _an ⁿ
For example, the thickness of the G _a A _s collector contact layer 2 is
Grow to about 4000 [Å].

(b) For example, by applying a sputtering method, a layer of electrode material with excellent heat resistance is formed to a thickness of, for example, 8,000 mm.
The collector electrode 3 is formed by forming a film with a thickness of approximately [Å] and applying a normal photolithography technique. As an electrode material having excellent heat resistance, for example, high melting point metal silicide such as molybdenum silicide and tungsten silicide can be used.

See Figure 3 (c) Chemical vapor deposition
A silicon dioxide (SiO ₂ ) film 4 is grown to a thickness of, for example, about 2000 Å by applying a deposition (CVD) method.

See Figure 4 (d) Using a parallel plate type dry etching device,
The silicon dioxide film 4 is etched using CF ₄ gas as an etchant.

As a result, the silicon dioxide film 4 is removed except for the part that covers the side periphery of the collector electrode 3.

See Figure 5 (e) MBE method or MOCVD (metal organic
n _- type _GaAs collector layer 5, p-type _GaAs base layer 6 _, n-type _AlGaAs layer 7 _, and n- _{type GaAs} emitter layer 8 by applying the chemical vapor deposition method.
grow in order. The thickness of each of these semiconductor layers is, for example, 2000 [Å], 1000 [Å], 2000 [Å],
2000〔Å〕.

See Figure 6 (f) Applying normal lithography technology, n-type _Ga
The As emitter layer 8 and _the n-type _AlGaAs layer 7 are selectively etched to expose a part of the surface of _the p-type _GaAs base layer 6.

(g) After this, the emitter electrode 9 and the base electrode 10 are formed by applying a normal technique.

In the embodiment described above, the semi-insulating _Ga
Although the n ⁺ type _{Ga As} collector contact _{layer 2 and the n type Ga As collector layer 5 are formed on the A s substrate 1 side, these may be converted to the n type Ga As emitter layer 8 .} ,
In that case, it goes without saying that the collector electrode 3 becomes an emitter electrode.

Effects of the Invention In the method for manufacturing a heterojunction bipolar semiconductor device of the present invention, a collector (or emitter) electrode is selectively formed on the surface of a collector (or emitter) contact layer on a semiconductor substrate, and then the collector An insulating film is formed to cover the side circumference of the (or emitter) electrode, and then, using the collector (or emitter) electrode covered with the insulating film as a mask, a required semiconductor layer is formed on the collector (or emitter)/collector layer. The structure includes a step of layered growth.

Therefore, the electrode leading out from the collector (or emitter) layer, which is the lowest layer, is formed from the beginning, and in order to lead out the electrode, it is necessary to etch the stacked semiconductor layers, etc. in order to lead out the electrode, as in the conventional technology. It is no longer necessary, and even if a base electrode is formed by selectively exposing a part of the base layer, the difference in level caused by this is slight, and furthermore, the emitter (or collector) electrode is formed by stacking layers. Since it only needs to be formed on the surface of the top layer of the semiconductor layer, the overall level difference is reduced and there is almost no risk of wiring disconnection.Furthermore, since the collector (or emitter) electrode is formed in a self-aligned manner, it is easy to manufacture. Yield improves.

[Brief explanation of the drawing]

FIG. 1 is a cutaway side view of the main part of a conventional heterojunction bipolar semiconductor device, and FIGS. 2 to 6 are cutaway side views of the main part of the semiconductor device at important process points for explaining one embodiment of the present invention. each represents. In the figure, 1 is a semi-insulating Ga _{A s} substrate, 2 is an n ⁺
Type _{Ga As} collector/contact layer, 3 is collector electrode, 4 is silicon dioxide film, 5 is n-type _{Ga As} collector layer, 6 is p-type _{Ga As} base layer, 7 is n-type Ga _As
an n-type _AlGaAs layer having a larger band gap than _{the As} collector layer 5 or the p-type _{GaAs base} layer 6;
8 is an n-type _{Ga As emitter} layer, 9 is an emitter electrode,
Reference numeral 10 indicates a base electrode.

Claims (1)

[Claims] 1. A step of selectively forming a collector electrode on the surface of a collector contact layer on a semiconductor substrate; Next, a step of forming an insulating film covering a side circumference of the collector electrode; A step of sequentially stacking a collector layer, a base layer, and an emitter layer on the collector contact layer using the collector electrode covered with a film as a mask, and then selectively removing the emitter layer located in a portion where the base electrode is to be formed. and then forming an emitter electrode on the emitter layer and a base electrode on the base layer. A method for manufacturing a heterojunction bipolar semiconductor device. 2. A step of selectively forming an emitter electrode on the surface of the emitter contact layer on the semiconductor substrate. Next, a step of forming an insulating film covering the side periphery of the emitter electrode. Next, a collector covered with the insulating film. using an electrode as a mask to sequentially stack an emitter layer, a base layer, and a collector layer on the emitter/contact layer, and then selectively removing the collector layer located in a portion where the base electrode is to be formed; A method for manufacturing a heterojunction bipolar semiconductor device, comprising the step of forming a collector electrode on the layer and a base electrode on the base layer.