JPH0464034B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a test method for a host unit equipped with a large number of semiconductor integrated circuits.

(b) Technology background In recent years, with the development of semiconductor technology, especially integration technology, 1
Highly integrated circuit devices (LSI), which have many circuit elements mounted on a package, are now available at low cost. Conventionally, logic circuits for data processing have been constructed by interconnecting combinational circuits such as NAND and OR/NOR circuits, and sequential circuits such as latches, registers, and flip-flop circuits (FF) obtained by multiple combinational circuits. configured. Logic circuits in data processing devices, such as central processing units (CPUs), are also composed of combinational circuits and sequential circuits, but in the past, when the degree of integration was not initially large to construct this CPU, the combinational circuits and/or sequential circuits were of the same type. A large number of small-scale integrated circuit devices (SSI) or medium-scale integrated circuit devices (MSI) that realize basic functions obtained by combining a small number or a small number of devices are assembled by mounting them on a higher-level intermediate mounting unit, such as a printed wiring board. Higher-level functions were realized by the logic circuits that were used, and higher-level logic circuit functions were realized by connecting a large number of intermediate real number units to form, for example, a stack unit. As the degree of integration improves, the scale of logic circuit configurations at the printed wiring board or stack unit level in conventional packaging units, such as large-scale and complex logic circuits such as microprocessors (MPUs), can be reduced to a small, lightweight, high-performance one package. Integrated circuit devices (LSI) are now available at low cost, and even master slice
Desired LSIs, such as LSIs, can now be provided in a short time based on the specifications ordered by customers. Of course, a large number of these LSIs can now be mounted and connected to an upper-level real number unit to realize upper-level functions, such as the conventional device level.

(c) Conventional technology and problems The improvement in the degree of integration as described above supports the development of data processing technology by providing small size, light weight, and high reliability at low cost through circuits with advanced logic functions. At the same time, it has brought about more complex and difficult conditions for various tests on LSI or intermediate mounting units, and the number of man-hours has increased to an enormous extent, leading to increased costs. In order to improve the reliability and maintainability of logic circuits with complex configurations, we incorporate error detection, automatic correction, and retry functions, while at the LSI level, we make it easier to diagnose logic circuits and pinpoint fault locations. Registers inside LSI, external lead terminals (pins) of package such as FF
Means has been introduced to read the status of a portion that is not connected to (scan out) or to write an arbitrary test pattern (scan in) in order to set expected data in the portion. Multiple LSIs
When testing a mounted unit that is connected to a mounted unit, for example, the data obtained from the pins can be obtained by connecting a mounted unit tester as a test target, but multiple
The above-mentioned scan-out output terminals and normal data input/output terminals for logic operations in the LSI are connected internally to the mounted unit, but they are not connected to the pins of the mounted unit. Even if some kind of failure occurs, in order to find the faulty LSI, it is necessary to directly probe the pins of the LSI, which has the drawback of making testing cumbersome and increasing the number of man-hours.
Furthermore, depending on the structure of the mounted unit, probing of LSI pins may be extremely difficult due to heat dissipation fins or the like.

(d) Purpose of the Invention The purpose of the present invention is to apply the scan-in/scan-out method to the real number unit level in order to eliminate the above-mentioned drawbacks and problems, and to apply the scan-in/scan-out method to the real number unit level to obtain output terminals in logic operations connected to LSI pins. Data is sent out using the scan-out terminal of each LSI, and the mounted unit is also provided with a collection function and scan-out terminal of the mounted unit, and the scan address of the mounted unit is applied to the LSI without probing. The present invention attempts to provide an efficient testing method for integrated circuit element mounting units that outputs expected data from the terminals.

(e) Structure of the Invention The object of the present invention is to reduce the maximum number p≦2 in a mounting unit in which a plurality of integrated circuit elements constituting a logic circuit using a plurality of semiconductor elements are mounted and connected to each other to form a higher-level logic circuit block. k logic data output means for outputting logic operation data to ^h integrated circuit elements; means for scanning data into/out of o flip-flop circuits forming an internal logic circuit; The mounting unit includes means for outputting q+k pieces of data by collecting data at a scan-out terminal of the scan-in/out means in accordance with the selection of a decoder that receives a scan address of m bits in the scan-in/out means; It is equipped with a mounting unit scan-out means that collects the outputs of the scan-out terminals of integrated circuit elements and outputs up to 2 ^h (q+k) pieces of data, and sends data to the mounted unit according to the h+m bit scan address applied to the mounted unit. By providing a test method for an integrated circuit element mounting unit, which is characterized in that scan-in/out data and output data of flip-flop circuits of all integrated circuit elements mounted and connected are outputted through a common mounting unit scan-out means. It can be achieved.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. The figure shows a block diagram of a testing method for an integrated circuit element mounting unit in one embodiment of the present invention. In the figure, 1 is an integrated circuit element mounting unit, for example, a printed wiring board mounting unit, 2a...
2p- ₂ , 2p- ₁ , 2p are highly integrated circuit elements (LSI), OR ₀ is an OR circuit, 21a is a decoder, FF _{aa to aq} are flip-flop circuits, AND _aa,ab
... _ar-1,ar is an AND circuit and OR _a is an OR circuit. Data input to the mounting unit 1 is input via its data input terminals PI _{pa to ps} , and each LSI 2 _a
~p is distributed and connected. LSI2 _a~p data input terminals
PI _aa~at ,...PI _pa~pt includes PI _pa~ps and other LSI2 _a
Data is input according to the connections from the data output terminals PO _{aa to ak} of _~p , . . . PO _{pi to pk} . The results of data processing in the LSIs 2 _{a to p} are outputted from the data output terminals PO aa to PO _ak in the LSIs 2 a to p via the data output terminals PO _{aa to p1} of the mounting unit 1. On the other hand, the scan data is applied from the scan-in data input terminal PSI ₀ of the mounted unit 1 to the scan-in data input terminals PSI _{a to p} of each LSI 2 _a to p connected in parallel, and also to the scan address input terminal of the mounted unit 1.
Applied to scan address input terminals of LSI 2 _{a to p} via PSI aa to ao PSI _{aa to} an ... _{pa to pn} . p decoders 21 _{a to p} are provided for each LSI that receives n bits of scan address, respectively decode m bits out of n bits, and decode 2 ⁿ for all LSIs 2 _{a to p} , 2 ^m for each LSI.
Select one of the addresses, for example FF _aa of _LSI2a , and input and set the scan-in data. Right here
If 2 ⁿ ≧p×2 ^m and p≦2 ^h , then 2 ⁿ ≧2 ^h+m . Also scan out data is via PSI _aa~ao PSI _aa~pn
The decoder 21 _a~p selects according to the scan address n bits applied to AND _aa~ar ... FF _aa~pq by _pa~pr and PO _aa~ak ... OR the data obtained from _pa~pk in each LSI. Output from _{a to p} via scan-out data output terminals PSO _{a to p} of LSI _{a to p} ,
This output data is sent to the outside from the scan-out data output terminal PSO ₀ of the mounting unit 1 from the OR ₀ that collects it. Since this embodiment is configured in this way, the data cannot be processed during normal data processing operation.
It is input to PI _pa~ps and output to PO _pa~p1 , but
According to the scan-in address of n=h+m bits applied to PSI _{aa to ao} , in addition to FF _{aa to pr} , data output terminals of LSI _{a to p} are output to PO _{aa to pk} ... _{pa to pk} during data processing operation. Scan-out output of mounted unit 1 allows any data to be sent and received between LSIs _a to p, including data not connected to mounted units PO _{pa to pl} , by simply manipulating signals without manual operations such as probing. It can be output from terminal PSO ₀ . In the above, the integrated circuit elements were explained using LSI _{a to p} , but of course they may be replaced with MSI and SSI, and the number of input terminals is uniformly set to an undefined maximum number t, k, etc., but any number of input/output terminals may be used. But it can be achieved as well. Also, in the scan address, n≧h+m, h is assigned to the selection of LIS2 _{a to p} , and m is assigned to the selection within each LSI, but all n bits are assigned to the selection of LSI2 _{a to p} decoder 21 _a to p decoder 21 _{a to} There is no problem even if applied to _p .

(g) Effects of the Invention As explained above, according to the present invention, data output in a mounting unit such as a conventional printed wiring board and data output of an LSI that is not output to the outside of the unit can be mounted by applying a scan-out address without probing. It is possible to provide an efficient testing method for integrated circuit element mounted units that can be obtained from the scan-out data output terminal of the unit.

[Brief explanation of the drawing]

The figure is a block diagram of a testing method for an integrated circuit element mounting unit in one embodiment of the present invention. In the figure, 1 is a mounting unit, 2 _{a to p} are highly integrated circuit elements (LSI), 21a is a decoder, FF _{aa to aq} are flip-flop circuits, AND _{aa to ab are AND circuits, and FF aa to aq} are flip-flop circuits.
OR _a is an OR circuit.

Claims (1)

[Claims] 1. In a mounting unit that is equipped with a plurality of integrated circuit elements that constitute a logic circuit using a plurality of semiconductor elements and are connected to each other to form a higher-level logic circuit block, the maximum number p≦2 ^h of integrated circuit elements is used to store logic operation data. k logical data output means for outputting the data; means for scanning data in/out to the q flip-flop circuits forming the internal logic circuit;
means for collecting the data obtained by the logical data output means at the scan-out terminal of the scan-in/out means and outputting q+k pieces of data according to the selection of the decoder that receives the m-bit scan address in the scan-in/out means. At the same time, the mounting unit collects the outputs of the scan-out terminals of each integrated circuit element for up to 2 ^hours.
It is equipped with a mounted unit scan-out means for outputting (q+k) pieces of data, and scans in/out of flip-flop circuits in all integrated circuit elements mounted and connected to the mounted unit according to the h+m bit scan address applied to the mounted unit.
A testing method for integrated circuit element mounting units characterized by outputting out data and output data through a common mounting unit scan-out means.