JPH0464713B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a disaster prevention system in which fire alarm equipment, gas leak alarm equipment, smoke prevention equipment, etc. are installed singly or in combination.

The applicant previously filed Japanese Patent Application No. 57-9535
127292) for an invention called ``Fire Detection System''. That is, the present invention relates to improvements in disaster prevention systems, including the fire detection system of the earlier application.

The invention in the earlier application connects multiple types of analog sensors to an alarm line, quantum encodes the output value of each analog sensor and sends it to the alarm line, and receives and decodes the signals to provide information for monitoring the fire state. In the fire detection system equipped with a processing device, a type code is determined for each type of the analog sensor, and each analog sensor transmits the type code before transmitting the quantized code. Ta. In other words, by having the analog sensor itself hold its own type information, the processing procedure of the information processing device on the receiving side becomes simpler, there is no need to prepare a table of addresses versus sensor types in advance, and it is also easier to replace the sensor. As a result, the degree of freedom in designing the sensor arrangement was increased. In order to avoid reducing the transmission speed when adopting this system, when initializing the program on the information processing device side, we instruct all sensors to provide type information and import all sensor types at the beginning. In the previous invention, it was also proposed to transmit only the quantized information after that.

However, if we use the method described above, which imports the sensor type at the initialization stage and then sends only the quantized information, it will be difficult to resolve the issue if the type of sensor placement is changed during system operation due to repair work, etc. If the system continues to operate as it is, there will be an inconvenience that the information sent from the changed sensor of a different type will be processed using the same processing standards as the sensor before the change. It was necessary to stop the system, restart it after making changes, and re-initialize the system. However, stopping the operation of the entire system even for a short period of time is not desirable, especially in fire detection systems.

The disaster prevention system according to the present invention can avoid the above-mentioned undesirable situations, and will be described in detail below with reference to the drawings.

In addition, in the previous application, the name was the fire detection system, but this system is not limited to fire alarm equipment, but can be used for multiple connected systems such as gas leak alarm equipment or smoke prevention equipment. It is clear that this invention can be applied to a disaster prevention system in which signals are sent and received individually between a terminal device and a central device, so in this invention, we purposely call it the disaster prevention system. did.

FIG. 1 is a schematic configuration diagram of the main parts of an embodiment of the disaster prevention system according to the present invention, in which a plurality of types of terminal devices 1 providing various information including their own type information are connected to a central device 2. Extended address signal line AD, clock signal line CL, data signal line
It is connected in parallel to the four signal lines SD and command signal line CM. Taking an analog sensor for fire detection as an example of a terminal device, inside the sensor is a detection section D that detects phenomena peculiar to fire such as heat and smoke and outputs an analog signal, and a detection section D that outputs analog signals from the detection section D. The A/D converter ADC quantum encodes the incoming analog signal and converts it into a digital signal and outputs it, and the detection part D is an ionization smoke densitometer, an optical smoke densitometer, or a thermometer. A type information sending section SH that sends out type information such as whether there is a type, an information selection circuit JS that selects and drives the type information sending section SH or the A/D converter ADC, and the four signal lines AD and CL. , SD, and CM, detects the self address sent via the address signal line AD, and sends the digital signal from the A/D converter ADC or the type information from the type information sending unit SH to the data signal line SD. as well as the command signal line.
A modem interface MOD is provided that selectively drives the information selection circuit JS based on command signals sent via the CM.

Inside the central unit 2, there is an oscillator G that sends a clock signal to the clock signal line CL and each circuit described below, and an oscillator G that sends the clock signal to the clock signal line CL and each circuit described below, and a value that is greater than the sum of the number of address bits, the number of start/stop bits, and the number of returned data bits. A frequency divider that divides the frequency by
FD, a counter C and a shift register that receive the above clock signal and frequency-divided signal as inputs and send an address signal to the address signal line AD.
Address signal generator 3 consisting of a combination of SR ₁
, a return data detection circuit 4 consisting of a combination of a shift register SR ₂ and an OR gate OR, and detecting the absence or abnormality of information from each terminal device 1 sent via the data signal line SD; A command circuit 5 which receives the detection output signal of the data detection circuit 4 as an input and sends a command signal to a command signal line CM consisting of a shift register SR ₃ having the number of steps corresponding to the number of terminal devices 1 connected to the signal line. is provided. In addition, the central device 2 side processes and displays information sent from each terminal device 1 via the data signal line SD, or processes and displays information sent from each terminal device 1 via the data signal line SD.
Various functions are provided for sending control information to, but these are not shown because they are normally provided and are not directly relevant to the description of this invention.

In one embodiment of the disaster prevention system according to the present invention configured as described above, when the power of the central device 2 is turned on, the shift register SR ₃ of the command circuit 5
is reset and set to zero. The clock signal output from the oscillator G is frequency-divided via a frequency divider FD by a value greater than or equal to the sum of the number of address bits, the number of start/stop bits, and the number of return data bits, thereby creating timing for calling each terminal. The output of this frequency divider FD is supplied to the counter C and shift register SR ₁ of the address setting circuit 3 and to the shift register SR ₃ of the command circuit 5.

The following explanation will be made with reference to the time chart of FIG. 2 showing the waveforms of each part in this embodiment.

In the address setting circuit 3, the counter C counts at the positive edge of the output pulse of the frequency divider FD, and the shift register _SR1 presets the contents of the counter C at the negative edge. in this case,
At the same time, the start bit and stop bit are also set. The contents of this shift register _SR1 are serially sent to the address signal line AD according to the timing of the clock signal.

On each terminal 1 side, when the command signal line CM is at low level, the information selection circuit JS
is driven to send the type information to the data signal line SD, and when the level is high, the information selection circuit JS drives the A/D converter ADC and sends the type information to the data signal line SD.
Since the SD is set to convert and send out the signal from the detection section D, in the initial state where the shift register SR ₃ of the command circuit 5 is reset and set to zero, each terminal 1 sends out the type information. Department SH
is being driven.

Therefore, on each terminal device 1 side, the address signal line AD
The address information sent via the modem interface and its own unique address information are
Compare on MOD, and if they match, the command signal line CM is low level, so the data signal line
Sends own type information to SD. The type information thus serially sent to the data signal line SD is applied to the shift register _SR2 of the return data detection circuit 4, and is taken in and stored in accordance with the timing of the clock signal.

On the central device 2 side, the parallel output of the shift register SR ₂ is taken in together with the address information, and the type of the terminal device is set and registered, and such processing is normally performed.

Now, the shift register of the return data detection circuit 4
The parallel output of SR ₂ is applied to the OR gate OR. Since the OR gate OR outputs a high level value as long as the type information is received, the shift register SR ₃ of the command circuit 5 takes in this output value in accordance with the output timing of the frequency divider FD. That is,
The shift register SR ₃ of the command circuit 5 is used for all terminals 1
After taking in the type information, its output is inverted and becomes high level, and the command signal line CM is set to high level. After that, the information selection circuit JS in each terminal 1 selectively drives the A/D converter ADC, so each terminal 1 receives the information obtained from the detection unit D at the time when it receives the call. the data signal line
Send to SD.

The information obtained from the detection section D is taken in and stored in the shift register _SR2 of the return data detection circuit 4 in accordance with the timing of the clock signal. The central device 2 receives the parallel output of the shift register SR ₂ together with address information, registers the detection status of the terminal, and displays it as necessary.

Shift register of this return data detection circuit 4
Since the parallel output of SR ₂ is also input to the shift register SR ₃ of the command circuit 5 via the OR gate in accordance with the output timing of the frequency divider FD, the information of each terminal 1 is sequentially transmitted without missing any information. As long as the data is being taken in, the output of the shift register _SR3 continues to be at a high level, and the command signal line CM continues to be at a high level.

However, if the type of terminal device arrangement is changed due to repair work or the like and the terminal device is removed, no information will be retrieved from the shift register SR ₂ of the return data detection circuit 4 when the terminal device 1 is called. Since the parallel output is not input, the OR output of the parallel output becomes zero. Then, the shift register SR ₃ of the command circuit 5 becomes
This zero output is taken in at the output timing of the frequency divider FD, and the output of the shift register SR ₃ is set to zero the next time this terminal device 1 is called, and the command signal line CM is set to a low level. Therefore, at this time, each terminal device 1 is
Since the information selection circuit JS drives the type information sending unit SH, the terminal 1 that received the call and which lacked information last time also sends out the type information to its own type information data signal line SD.
As a result, the central device 2 side redoes the setting registration of the type of the terminal device. Then, the return data detection circuit 4 also generates a detection signal, and in order to cause the shift register SR ₃ of the command circuit 5 to take in the output value, the information obtained from the detection unit D is sent to the terminal 1 from the next call as a data signal. Send it to line SD.

In the above explanation, the processing when information is missing has been explained, but it goes without saying that the same effect can be achieved in the case of information abnormality due to a timing shift when the return data detection circuit 4 takes in the data. do not have.

Additionally, since the status of each terminal 1 is registered at any time, it would be very convenient to display any missing or abnormal information when outputting a list of terminals, such as during maintenance and inspection. .

Furthermore, in the above embodiment, the processing within the central unit is performed by a combination of shift registers, OR gates, etc., but the same effects and effects can be obtained by using means such as a microcomputer programmed with the above processing procedure. It is obvious that it will play.

In this embodiment, address signal lines AD,
Although we used four transmission lines: a clock signal line CL, a data signal line SD, and a command signal line CM, it is of course possible to use a method of time-divisionally transmitting these four pieces of information using a pair of signal lines. be.

As described above, according to the disaster prevention system according to the present invention, there is no need to stop the operation of the entire system when changing the terminal device, and the system can continue to operate continuously, and the setting registration of the type after the change is automatically performed. This function can greatly improve the reliability of the entire system, and this function can be used in systems that import type information only at the initial stage and then import other information to shorten transmission time. , which further improves reliability and provides operational convenience.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an embodiment of the present invention, and FIG. 2 is a time chart of each part used to explain the operation of the embodiment shown in FIG. 2...Central device, AD, CL, SD, CM...Signal line, 1...Terminal device, SH...Type information sending section, 4
...Return data detection circuit, 5...Command circuit, JS
...Information selection circuit.

Claims (1)

[Scope of Claims] 1. Connecting a plurality of terminal devices of a plurality of types to a line extending from a central device, each of which is given a unique address and which provides at least its own type information and information obtained from a detection unit, In a disaster prevention system in which the central device sequentially calls each terminal device using the above address and monitors and controls them individually, the central device may have a problem with the lack of information sent from each terminal device or the timing at which information is taken in. Detection means for detecting abnormalities caused by misalignment etc. for each terminal device, and detecting abnormalities by instructing terminal devices for which the detection means does not detect an abnormality to provide information obtained from the detection section. A command means for instructing the terminal device to provide the type information is provided, and each of the terminal devices is provided with a selection means for selecting which of the above information to be provided by a command from the command means. A disaster prevention system characterized by: