JPH0465403B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor having a cryptographic function.

[Conventional technology]

Conventionally, in applications using microprocessors, there are cases in which the right to use the microprocessor is granted only to a specific person, in which a code is input at the initial stage of operation, or the method of use is extreme. Some are more complex than others, some respond only to the voice of a specific predetermined speaker, and some respond only to specific magnetic cards.

[Problem that the invention seeks to solve]

The method of entering the code is, for example, by entering 4 digits using the keys 0 to 9. In this case, there are 10 ⁴ combinations, or 10,000 combinations. To increase the number of combinations, input more digits. However, the number of comparison circuits with preset cipher numbers increases, and the number of programs for comparison increases, making it difficult for a single-chip microprocessor with built-in program memory to process the program area. It has the disadvantage of being pressurized. Another disadvantage of this method is that it is always possible to decipher the information if you patiently enter the information in order.

Making the method of use complicated is not a good method because even certain users find it inconvenient to use. Currently, methods for recognizing specific speakers are still expensive and require very complex peripheral circuitry. The method using a magnetic card requires a card reader and cannot be applied to inexpensive devices.

As described above, the cryptographic functions in devices using conventional microprocessors are difficult to decipher and cannot be implemented at low cost.

[Means for solving the problem] In a microprocessor that has a circuit that generates a certain period of time after power is turned on and a key input terminal,
means for comparing key-input data with preset data; a shift register into which a signal generated by the key-in operation itself is input as a clock; By having a latch that sequentially latches the comparison results within a period and a means for prohibiting the supply of the operating clock if all the latched comparison results do not match, it is possible to perform encryption even with a cryptographic code input method using a small number of keys. By increasing the complexity, it becomes possible to easily realize a cryptographic code system that is quite difficult to decipher.

〔Example〕

Next, the present invention will be explained with reference to the drawings.
FIG. 1 shows an embodiment of the present invention, in which a crystal resonator 39 is connected to the frequency input terminal 1.
AC amplifier 27 built into the microprocessor
The reference frequency is obtained by oscillating at . When power is applied to the power supply terminal 5, the reset signal 7 generated by the reset circuit 6 resets the counters 2, 28 to 3.
0, latches 21-24, shift registers 31-3
At the same time, the crystal resonator 39 starts oscillating. Momentary keys 40 are connected to key input terminals 8 to 11, and when those keys 40 are pressed, a high level is applied to key input terminals 8 to 11. Key input terminals 8 to 11 are connected to internal pull-down resistors. Since the key input terminals 8 to 11 are pulled down by 26, they become low level when the key 40 is not pressed.The states of the key input terminals 8 to 11 are converted by the programmable logic array 13 and become input data to the latches 21 to 24. Also,
After passing through the chattering/causing circuit 15,
It is input to OR gate 16. Therefore, when any key 40 is pressed, the output of the OR gate 16 becomes high level, and the output of the NAND gate 35 and NOR gate 16 becomes high level.
The input of gate 37 also becomes high level. The outputs of the shift registers 31 to 34 are initially at low level due to the reset signal 7, so the NOR
Output of gate 38 is high level, inverter 36
The output also becomes high level. This inverter 36
The output remains high until four clocks are input to the shift registers 31 to 34, and when the fourth clock is input, it becomes low level and the NAND gate 3
5 input to low level, shift register 3
Prohibit clock input from 1 to 34.
That is, if any key is pressed four times after the reset signal 7 is output, the shift operations of the shift registers 31 to 34 are automatically stopped.

On the other hand, the output of the OR gate 16 is inverted and passed through the NOR gate 37 only while the gate signal 12, which is the other input of the NOR gate 37, is at a low level.
It is input to NAND gates 17-20. NAND
The outputs of gates 17-20 provide the clocks for latches 21-24. Therefore, when there are four key inputs to the key input terminals 8-11 while the gate signal 12 is at a low level, the data of the key inputs are sequentially latched into the latches 21-24 via the PLA 13.

The data on the PLA output signal 14 is latched first. In order for this signal to become high level, the data at the key input terminals 8 to 11 must be 1000.

The next data will be 0010, 0001, 0100. In other words, it is necessary to set the key input terminal 8, key input terminal 10, key input terminal 11, and key input terminal 9 to a high level in this order. In this way, by pressing the key 40 (inputting the encryption code) as specified in the above-mentioned PLA 13 during the period when the gate signal 12 is low level, the outputs of the latches 21 to 24 all become high level, and the output of the AND gate 25 becomes high level. The frequency obtained by dividing the frequency input from the frequency input terminal 1 into 1/2 by the counter 2 appears as the CPU clock at the output. Conversely, unless the specified key input is made,
No clock is supplied to the CPU.

The low level period of the gate signal 12 is determined by the frequency of the frequency input terminal 1 and the number of stages of the counters 2, 28 to 30, but the operation of the above embodiment is shown in _FIG . Divide counters 2 and 30 by 1/2, counters 28-29 by 1/5
Total 1/2 x 2 x 5 ¹⁰ = 1/39062579 with 10 stages of frequency division
The frequency is divided, and the low level falls (a in Figure 2).
Point) is 39.06 seconds after the power is applied to the power supply terminal 5, and the low level period (points a to 6 in FIG. 2) is also 39.06 seconds.

〔Effect of the invention〕

As described above, the present invention has the effect of making it possible to realize a cryptographic code system that is quite difficult to decipher at a relatively low cost by setting a limit on the input time even in a cryptographic code input method using a small number of keys.

The setting data (encryption code) can be easily changed by changing the contents of the PLA, and in the embodiment, 4 ⁴ = 256 settings are possible. Also, to make it more complicated, it is possible to press multiple keys at the same time for one key input, in which case 15 ⁴ =
There are 50625 ways. In addition, the key input validity period can be changed relatively easily by manipulating the number of stages of the counter, so it is possible to increase the complexity of the cipher indefinitely.

Furthermore, it goes without saying that these functions can be configured by the microprocessor program itself.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a microprocessor having an encryption function according to the present invention, and FIG. 2 is a timing chart illustrating its operation. 1... Frequency input terminal, 2... Flip-flop, 3... Clock signal, 4... CPU clock signal, 5... Power supply terminal, 6... Reset signal generation circuit, 7... Reset signal, 8-11... Key input terminal, 12... Gate signal, 13... Programmable logic array (PLA), 14...
PLA output signal, 15...Chattering cancel circuit, 16...OR gate, 17-20...
NAND gate, 21-24...Latch, 25...
...AND gate, 26...Pull-down resistor, 27
...AC amplifier, 28-30...Counter, 31
~34...Shift register, 35...NAND gate, 36...Inverter, 37-38...
NOR gate, 39...crystal oscillator, 40...momentary key.

Claims (1)

[Claims] 1. A circuit that generates a certain period of time after power is turned on, a means for comparing key input data with preset data in a microprocessor having a key input terminal, and a signal generated by the key input operation itself. a shift register that inputs the clock as a clock, a latch that sequentially latches the comparison results within the certain period in the input order determined by the output of the shift register, and operates if all the latched comparison results do not match. A microprocessor characterized in that it has means for inhibiting clock supply.