JPH0465571B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention aims to provide a simplified multi-input CMOS gate circuit.

Conventional configuration and its problems In general, a multi-input CMOS gate circuit has n inputs.
requires a minimum number of 2n elements for For this reason, it cannot be denied that the chip area increases when integrated circuit IC is used, and it is extremely unsuitable for use as a decoder that simply detects the count value of a binary counter. In order to eliminate such drawbacks, the present inventor filed a patent application in 1983.
No. 79537 provided a multi-input CMOS gate circuit that can have (n+2) constituent elements.

FIG. 1 illustrates one circuit configuration thereof.

In Figure 1, A is a NAND gate circuit, B
is a NOR gate circuit.

NAND gate circuit A consists of n enhancement type N-channel MOS transistors (N-type transistors) QN ₁ , QN ₂ , QN ₃ . . . QN _o and one enhancement type transistor connected in series corresponding to the number of inputs n. It is composed of a total of (n+2) elements including a P-channel MOS transistor OP ₁ and a load element QL ₁ , and one end of a group of N-type transistors connected in series is connected to an output terminal b and the other end is connected to a first power supply V _SS , The respective gates are connected to input terminals a ₁ , a ₂ , a ₃ ...
It's a _o . The P-type transistor _QP1 has one end connected to the second power supply _VDD, the other end to the output terminal b, and its gate connected to the gate of the N-type transistor _QN1 . The load element QL ₁ is connected between the second power supply V _DD and the output terminal b.

On the other hand, NOR gate circuit B includes n P-type transistors QP ₁ , QP ₂ , QP ₃ . . . connected in series.
QP _o and one N-type transistor QN ₁ and load element
QL ₁ , one end of a group of P-type transistors connected in series is connected to the output terminal b, and the other end is connected to the first power supply V _DD
connected to the respective gates input terminals a ₁ , a ₂ , a ₃
...it's a _o . The N-type transistor _QN1 has one end connected to the second power supply _VSS , the other end to the output terminal b, and its gate connected to the gate of the P-type transistor _QP1 . The load element QL ₁ is connected between the second power supply V _SS and the output terminal b.

That is, circuit A and circuit B are exactly symmetrical circuits, and at least one of the inputs has a complementary configuration. In A, QN ₁ and QP ₁ are
In B, QP ₁ and QN ₁ each have a complementary configuration.

Here, the load element QL ₁ may be composed of an active element, such as a P-type transistor or an N-type transistor.

When the multi-input CMOS gate circuit explained above is integrated into an IC, as shown in Fig. 2, stray capacitance C ₁ ,
C ₂ , C _{3 .} . . C _o is attached, and this causes a decoding malfunction. FIG. 3 is a waveform diagram showing this situation.

The circuit operation of the conventional example will be explained below with reference to FIGS. 2 and 3. To simplify the explanation, an example will be shown in which the Q output of a free counting up counter or the output of a down counter is decoded for a NAND gate circuit having four inputs (n=4). In addition, stray capacitance C ₁ , C ₂ , C ₃ , C ₄
are all equal, N-type transistors connected in series
The on-resistance of QN ₁ , QN ₂ , QN ₃ , and QN ₄ is sufficiently low.
The explanation will be given while ignoring back gate bias effects and the like.

LSB (a ₁ ) to MSB (a ₄ ) of the counter shown in Figure 3
are the inputs a ₁ to a ₄ in Fig. 2. First, the count value is
In the case of 15, that is, in the period from 15 to 0, a ₁ to a ₄ are all H and all N-type transistors QN ₁ to QN ₄ are “ON”.
However, the potential of output terminal b becomes _VL . The magnitude of V _L is determined by the voltage division ratio of the combined ON resistance of QN ₁ to _{QN 4} and the resistance of the load element QL ₁ , so it may be set to a level that does not cause the next stage circuit to malfunction. i.e. period 15
~0, the charges in the capacitors _C1 ~ _C4 for all _QN1 ~ _QN4 to turn on are discharged, and the potential at each connection point is 0 (actually in the range of VL _~ O). be). Next, in period 0 to 1, a ₁ to a ₄ are all L, and P
Only type transistor QP ₁ is ON, QN ₁ ~ QN ₄
are all turned off. Therefore, _C1 is charged with charge by _QP1 and _QL1 , and the output terminal b becomes _VDD . Here, the resistance of QL ₁ with respect to the ON resistance of QP ₁ is sufficiently large, so it will be ignored in the following explanation. However, C ₂
The charge on ~ _C4 is 0. Next, in period 1 to 2, since a ₁ is H and a ₂ to a ₄ are L, only QN ₁ is turned on and C ₁
A phenomenon occurs in which the charge of is distributed to C ₂ , and the potential of output terminal b becomes V _DD /2. Next, in period 2-3
Since a ₂ is H and a ₁ , a ₃ , and a ₄ are L, QP ₁ and QN ₂ are turned ON, and QP ₁ charges C ₁ to V _DD again. On the other hand, since QN ₂ is also ON, charge distribution from C ₂ to C ₃ occurs, resulting in V _DD /4. Next period 3~
In 4, a ₁ and a ₂ are H and a ₃ and a ₄ are L, so QN ₁ and
QN ₂ is turned on, and charge distribution from C ₁ to C ₂ and C ₃ occurs, resulting in V _DD /2. Thereafter, similar charge distribution is repeated between each capacitor, and eventually the potential at the output terminal b changes as shown in FIG. By the way, during the period when a ₁ is L, OP ₁ is always turned on, so it becomes V _DD , and the period 5 to 6,
3V _DD /4 for 7-8, 9-10, 11-12, 13-14,
27V _DD /48, 75V _DD /96, 450V _DD /576,
The potential becomes 1026V _DD /1152. That is, due to the charge distribution phenomenon in the stray capacitances C ₁ and C _{4 ,} the H level of the output terminal b does not become constant at V _DD , causing a problem that malfunction of the next stage circuit occurs.

Note that in reality, the counter output has a propagation delay τP・
Due to various factors such as the presence of back gate bias in _the N- _type transistors QN ₁ to QN ₂ with
When ~ _C4 becomes large, the potential of the output terminal b approaches the L level, and the output terminal b becomes unusable.

OBJECTS OF THE INVENTION The present invention provides a multi-input gate circuit that eliminates the problems caused by charge distribution in the conventional example.

Configuration of the Invention The present invention can solve the problems with an extremely simple configuration that only requires adding one new load element to the conventional circuit configuration.

That is, one end of a plurality of serially connected MOS transistors of the same polarity is connected to an output terminal, the other end is connected to a first power supply, and each gate is used as an input terminal.
of opposite polarity to the transistors in the MOS transistor group.
One end of the MOS transistor is connected to a second power supply, the other end is connected to the output terminal, and a gate is connected so as to have a complementary configuration with at least one of the MOS transistors, and between the output terminal and the second power supply. A first load element is connected to the connection point on the first power supply side of the transistors of the MOS transistor group configured in a complementary manner, and the second
The configuration is such that a second load element is connected between the power source and the power source. In such a configuration, the first and second load elements may be constituted by active elements (N-type or P-type transistors, etc.), and the second load element is constituted by a transistor synchronous with the reverse polarity MOS transistor, Its gate may be connected to the gate of the reverse polarity MOS transistor.

DESCRIPTION OF EMBODIMENTS FIGS. 4A and 4B show the basic configuration of the present invention. A is
The NAND gate circuit, B is a NOR gate circuit, and what is different from the conventional example in Figure 1 is the second load element.
This is the addition of QL ₂ .

That is, in circuit A, QN ₁ to QN _o have the same polarity.
It is a MOS transistor, QP ₁ is a reverse polarity transistor, QL ₁ and QL ₂ are the first and second load elements, and V _SS
is the first power supply, and V _DD is the second power supply. In addition, in circuit B, QP ₁ to QP _o are the same polarity MOS transistors, QN ₁ is the opposite polarity transistor, QL ₁ ,
QL ₂ is the first and second load elements, V _DD is the first power supply, V _SS
is the second power supply.

Next, we will explain the operation when there are stray capacitances C ₁ to _{C o} at each connection point using the 4-input (n = 4) shown in Figure 5.
This will be explained using a NAND gate circuit as an example with reference to the waveform diagram in FIG.

LSB (a ₁ ) to MSB of the counter output shown in Figure 6
(a _o ) is input into a ₁ to a ₄ in FIG. First, when the count value is 15, that is, in the period from 15 to 0, a ₁ to a ₄ are all H, all N-type transistors QN ₁ to QN ₄ are "ON", and the potential of the output terminal b is equal to V _L. Become. The magnitude of V _L is determined by the voltage division ratio of the combined ON resistance of QN ₁ to QN ₄ and the resistance of the first load element QL ₁ , and the combination of QN ₂ to _{QN 4} .
It is determined by the voltage division ratio between the ON resistance and the resistance of the second load element QL ₂ , and the resistance value of the second load element QL ₂ is set smaller than the resistance value of the first load element QL ₁ .
In reality, the magnitude of V _L is determined by the latter partial pressure ratio.
In this case as well, there is a constraint that the level must be set to prevent the next stage circuit from malfunctioning.

Next, in periods 0 to 1, a ₁ to a ₄ are all L, only the P-type transistor QP ₁ is turned on, and all of QN ₁ to QN ₄ are turned off. Therefore, _C1 is charged with charge by _QP1 , and the output terminal b becomes _VDD . On the other hand, C ₂ is charged with electric charge by the second load element QL ₂ having a relatively low resistance. At this time, at least 0~
If charging can be completed within a period of 1, C ₂ will be charged to V _DD . Therefore, when a ₁ becomes H and QN ₁ is turned "ON" in the next period 1 to 2, charge distribution from C ₁ to C ₂ does not occur. Period 2-3, 4-5, 6-7,
At 8 to 9, 10 to 11, 12 to 13, and 14 to 15, _a1 is L, _QP1 is “ON”, and the potential of output terminal b is V _DD
Therefore, there is no problem as in the conventional example. Next, period 3
~4, QN ₂ is “ON” in periods 2 and 3, and C ₃
Since charging is done by the second load element QL ₂ and C ₂ has already been charged, no charge distribution occurs either. Below, periods 5-6, 7-8, 9-10, 11-
12, 13 to 14 can prevent charge distribution,
The problems of the conventional example can be solved. In addition,
It goes without saying that the first and second load elements QL ₁ and QL ₂ can be constructed from active elements (N-type or P-type transistors, etc.).

Here, when the second load element QL ₂ is configured with a resistor or an active element that is always “ON”,
It is necessary to keep the magnitude of V _L below a value that does not cause the next stage circuit to malfunction, which has the disadvantage of being subject to restrictions.

FIG. 7 shows an embodiment of the present invention that eliminates such restrictive conditions.

7A and 7B are the basic configuration of the present invention.
This is an embodiment shown corresponding to B, and the difference from FIG. 4 is that the second load element NL ₂ has a reverse polarity transistor.
QP ₂ and QN ₂ having the same polarity as QP ₁ and QN ₁ are used, and their gates are connected to the gates of opposite polarity transistors QP ₁ and QN ₂ .

With such a configuration, QN ₁ is “ON” in circuit A.
Since _{QP 2} can be OFF _{like QP 1} when Capacity C ₁ can be charged using only QP ₁ , and C ₂ to _{C o} can be charged using only QP _2. The ON resistance is not restricted by V _L , and reliable operation is possible. It is something.

Effects of the Invention As explained above, according to the present invention, by simply adding one second load element to a (n+2) multi-input CMOS gate circuit with a small number of constituent elements, floating can be achieved without changing the input configuration at all. It can eliminate the charge distribution phenomenon caused by capacitance and realize reliable operation, and when integrated, the chip size can be smaller than a complete CMOS multi-input gate circuit with 2n components, and its operating characteristics are the same. This also has the advantage of relatively low current consumption.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional multi-input CMOS gate circuit, Fig. 2 is a block diagram of a 4-input NAND gate circuit to explain the operation of a conventional multi-input CMOS gate circuit, and Fig. 3 is the operating waveform of Fig. 2. 4 is a basic configuration diagram of a multi-input CMOS gate circuit of the present invention,
Fig. 5 is a configuration diagram of a 4-input NAND gate circuit to explain the operation of the multi-input CMOS gate circuit of the present invention, Fig. 6 is an operation waveform diagram of Fig. 5, and Fig. 7 is an embodiment of the present invention. FIG. 2 is a configuration diagram of a multi-input CMOS gate circuit. V _DD , V _SS ... power supply, QN ₁ - QN _o ... N channel MOS transistor, QP ₁ - _{QP o} ... P channel MOS transistor, QL ₁ ... first load element,
QL ₂ ... second load element, a ₁ to a _o ... gate input or gate input terminal, b ... output terminal.

Claims (1)

[Scope of Claims] 1. A gate circuit for decoding the output of a counter, comprising a plurality of series-connected same-polarity MOS transistors connected between an output terminal and a first power supply, and comprising a plurality of series-connected same-polarity MOS transistors. The output of the counter is connected to the gate of the transistor, and the output of the counter on the lower bit side is input to the transistor connected to the output terminal side, and the output on the higher bit side is input to the transistor connected to the first power supply side. A group of MOS transistors input to the transistor connected to the transistor connected to the transistor connected between the second power source and the output terminal and a transistor connected to the output terminal of the group of MOS transistors have a complementary configuration. The MOS with the gate connected to
a reverse polarity MOS transistor having a polarity opposite to that of the transistor group; a first load element connected between the output terminal and the second power source; and a first load element connected to the output terminal of the MOS transistor group. A multi-input CMOS gate circuit comprising: a second load element connected between a connection point on the first power supply side and the second power supply. 2. The multi-input CMOS gate circuit according to claim 1, wherein the first load element is an active element. 3. Multiple inputs according to claim 1 or 2, in which the second load element is composed of an active element.
CMOS gate circuit. 4. The multi-input CMOS according to claim 1 or 2, wherein the second load element is composed of a transistor of the same polarity as the reverse polarity MOS transistor, and its gate is connected to the gate of the reverse polarity MOS transistor. gate circuit.