JPH0465616B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention provides a method for protecting the output circuit section of an electronic device or its external device against overcurrent that may occur in the output circuit section, particularly at the interface section with an external device. This invention relates to an overcurrent protection circuit for protection.

[Prior art and its problems]

As is well known, an interface is placed at the interconnection point between the aforementioned electronic devices and an external device, and this interface often includes an output circuit that can handle enough power to directly operate the external device. is provided. For example, a program controller or a sequencer as an electronic device must have its own or an attached output circuit section to operate a relay or a solenoid valve in an external device. Alternatively, electronic circuits built into sensors often require an output circuit section that can directly drive external solenoid valves, alarms, etc. In such an output circuit section, an output transistor is provided for each operation or control channel so that the above-mentioned operation or control in an external device can be performed based on a weak signal in the electronic circuit.

However, troubles may occur in the objects operated or controlled by such output circuit units for various reasons, and failures such as short circuits often occur in the wiring leading to the objects. In such a short circuit accident, an excessive load is placed on the output transistor in the output circuit, which may cause it to burn out.Also, even if it does not result in a short circuit, if an overcurrent flows for a long time due to a problem, However, the output transistor may be damaged, and at the same time, damage may also occur within the object to be operated or controlled.

For this reason, the output circuit section serving as an interface has traditionally often incorporated a function to protect the output transistor in the output circuit from overcurrent generated in the output circuit. Give an example of a circuit. In the figure, the internal circuit of the electronic device is simply indicated by the reference numeral 1, and an output circuit 2 for one channel is shown on the right side of the dashed line on the right side. The main body of this output circuit 2 is an output transistor 3, which receives on/off or analog control commands S from a drive transistor for driving the output circuit in the internal circuit 1, and transmits them via a power source B (not shown). Generates a load current IL as an output signal to an object to be operated or controlled within an external device. When an accident occurs within the object, this load current IL becomes excessive, and since this load current is naturally the collector current of the output transistor 3, the output transistor 3 may be damaged due to the excessive collector current. For this protection, a current detection resistor 4 is connected to the emitter side of the output transistor 3, and the voltage drop flowing through the resistor 4 is applied between the base and emitter of the protection transistor 5 shown to the left. Given. Therefore, when an overcurrent due to a fault flows through the current resistor 4, the base potential of the transistor 5 increases and the transistor 5 turns on, lowering the base potential of the output transistor 3 by bringing it closer to the ground potential, and lowering the load. Limits the current IL to below the allowable current value.

Even with such conventional technology, overcurrent protection can be achieved with a relatively simple circuit configuration, but as can be seen from the above explanation, a sustained current continues to flow through the output transistor 3 until the failure is recovered. become. That is, if the base-emitter voltage that turns on the transistor 5 is Vbe, the resistance value of the current detection resistor 4 is Rs, and the limit current of the load current IL when overcurrent protection is performed is ILm, then ILm= A limited current of the value Vbe/Rs will flow continuously. The value of this limited current is determined by the output transistor 3 or its load, and in particular, for the transistor 3, it must be selected to be relatively low in the case of a sustained current. On the other hand, the value of Vbe in the above equation is determined by transistor 5 and cannot be lowered below a certain limit, so in order to lower the value of limiting current ILm, it is necessary to increase the value of the current detection resistor Rs. . However, since this resistance value is always inserted into the load current IL not only during failure but also during normal operation, it is necessary to keep it as low as possible from this point of view. As described above, in conventional technology, there is a dilemma between the requirement to avoid unnecessary power consumption in the output circuit and the requirement to provide sufficient overcurrent protection, and for this reason, it is difficult to ignore some power consumption. The current situation was such that we had no choice but to choose complete protection. Further, in such a conventional technique, apart from the power consumption under normal conditions, it is undesirable from the point of view of the original purpose of protection to flow a completely useless current to the output transistor or load in the event of a failure.

[Purpose of the invention]

It is an object of the present invention to solve the above-mentioned problems of the prior art and to obtain an overcurrent protection circuit for the above-mentioned application, which has minimal power consumption and a more complete protection function.

[Key points of the invention]

According to the present invention, a current suppressing transistor whose collector is connected to the base of an output transistor of an output circuit that generates a predetermined load current based on a command and controls and suppresses the current of the output transistor, and a current suppressing transistor that controls and suppresses the current of the output transistor, and an emitter of the output transistor and grounding. a current detection resistor connected between them, an overcurrent detection transistor whose base is connected to the connection between the emitter and the current detection resistor, and which responds when the voltage at the end of the current detection resistor exceeds the voltage between the base and emitter; A constant current source is connected to the connection between the capacitor and the collector of the overcurrent detection transistor to charge the capacitor, and a reference voltage is connected to the non-inverting input of the inverting transistor. This is achieved by an overcurrent protection circuit configured with a voltage comparator whose input is connected to the collector of an overcurrent detection transistor, and an output of the voltage comparator is connected to the base of a current suppression transistor. In the circuit of the present invention, with the above configuration, when an overcurrent occurs in the output circuit, the load current is immediately cut off or suppressed to an extremely small suppressed current value compared to the conventional limited current. This suppressed or cut-off state continues until a time limit end signal is issued from the time limit circuit, and at the time the time limit end signal is generated, the suppress state is canceled and the output circuit is returned to the state before the suppress operation. At this time, if the output circuit has still recovered from the overcurrent state, the output circuit enters the normal state, but if the overcurrent state still continues, the current suppression operation described above and its release are performed. The operation is repeated until the output circuit condition is restored to normal or the cause of the failure is artificially removed.
At this time, an overcurrent flows into the output circuit when the current suppression operation is canceled, but the time until the current suppression operation resumes after cancellation can be made extremely short.
The influence of such a short-time overcurrent on the output transistor and load and the power loss in the output circuit can be made much smaller than in conventional protection circuits. In the case of the circuit of the present invention, even if the fault in the output circuit happens to be recovered during the current suppression operation, the current suppression operation will continue until the time limit end signal is issued from the time limit circuit. If selected appropriately, there is no problem for large-scale applications.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a circuit diagram of an embodiment of the present invention, in which parts common to those in FIG. 1 are given the same reference numerals. Further, FIG. 3 is a waveform diagram of main signals in the circuit of this embodiment.

In FIG. 2, a transistor 11 is an overcurrent detection transistor that inputs a current value signal Vs generated by a current detection resistor 4 as a base, and when the load current IL in the current detection resistor 4 becomes an overcurrent, a current value signal is generated. The value of Vs is the base-emitter voltage Vbe
When the voltage is exceeded, the capacitor 12 and the constant current source 13 are connected immediately by short-circuiting the capacitor 12.
Starts a timed circuit consisting of. On the other hand, the comparator 14 shown on the right receives the capacitor voltage of this capacitor 12 at its inverting input.
On the other hand, a reference voltage Vr is applied to its non-inverting input. Since the reference voltage Vr is selected to be smaller than the capacitor voltage Vc before the transistor 11 conducts, the output of the comparator 14 is "0" before the conduction. The current suppressing transistor 15 shown in the figure is in an off state, but as mentioned above, the transistor 1
1 becomes conductive due to the overcurrent value signal, the capacitor voltage to the inverting input becomes zero, so the output of the comparator 14 is inverted and becomes "1", turning on the current suppressing transistor 15, and until then the output from the internal circuit 1 is Since the command S given to the transistor 3 is led to the ground, the output transistor 3 is turned off and the load current IL is cut off. The pattern of this circuit operation is shown in FIG.

During the normal period Tn shown on the left side of FIG. 3, the value of the current value signal Vs is the voltage between the base and emitter of the overcurrent detection transistor 11 shown by the dashed line, as shown in FIG. Although it is lower than Vbe, when a failure occurs in the output circuit and enters the failure period Ta, the transistor 11 immediately conducts and shorts the capacitor 12, so the capacitor voltage Vc becomes zero as shown in Figure b. , the current suppression signal Sl as the output signal of the comparator 14 shown in FIG. The output transistor 3 receives this current suppression signal Sl and cuts off the load current IL after a short delay time ΔToff.
At the time of this interruption, the current value signal Vs becomes zero, and at the same time, the transistor 11 is turned off and charging of the capacitor 11 of the time limit circuit is started. After that, the capacitor voltage Vc is determined by the capacitance of the capacitor 12 and the constant current source 13.
Figure 2b shows the slope determined by the charging current value from
As shown in , it rises linearly and the reference voltage Vr
The output of the comparator 14 is inverted to "0" at the point where it intersects with "0". The current suppression transistor turns off due to the disappearance of the current suppression signal Sl, and after a short delay time △Ton, the output transistor 3 turns on and the current IL flows through the output circuit again. If not, the overcurrent will flow to the output circuit again, so the circuit can repeat the above-described current suppression operation and its release until the fault is recovered or until the fault is noticed and the output recovery is artificially turned off.

In this way, the embodiment circuit shown in FIG. 2 repeats current suppression and its release operation during the failure period Ta at the period T shown in FIG. 3c, but at the time tr shown in FIG. If the fault is not recovered or the output circuit is artificially turned off, then even if the current suppression operation is canceled and the output circuit is turned on, no overcurrent will flow, so the current value of the current detection resistor 4 will change. The detection signal Vs does not reach the base-emitter voltage Vbe of the overcurrent detection transistor 11, and therefore the current suppression operation does not occur and the circuit remains in the initial normal period.
Return to the operating state at Tn. Now, as can be seen from the above explanation, the time during which the load current IL flows during the operation cycle T of the circuit within the failure period Ta is only the aforementioned cutoff delay time △Toff, and the cutoff operation of the output transistor is usually long. Since the duration does not exceed several milliseconds, the average value or effective current of the load current IL flowing through the output circuit throughout the failure period Ta is extremely small. On the other hand, in the case of the conventional technology shown in FIG. 1, the load current IL continues to flow without being cut off from the time of failure initiation to the time of failure recovery tr.
During this period, the value of the current value signal Vs generated across the current detection resistor 4 changes to the base-emitter voltage of the overcurrent detection transistor 11, as shown by the chain line in FIG. 3a.
Since a load current balanced by Vbe will flow, the load current that continues to flow throughout the failure period Ta is:
Equal to the aforementioned limit current ILm (=Vbe/Rs). From this, it can be seen that in the case of the circuit of the present invention, the effective value of the load current flowing during the failure period is much smaller than that in the prior art.

A more quantitative explanation of the above matters is as follows. Now, the capacitance of the capacitor 12 in the time limit circuit is c, and the value of the charging current from the constant current source 13 is Ic.
If the charging period from the start of timed operation until the capacitor voltage Vc reaches the reference voltage Vr and the current suppression command Sl from the comparator 11 is erased, that is, the time limit of the timed circuit, is Tc as shown in FIG. 3b, then Tc =C·Vr/Ic, and this time limit Tc can be freely determined by selecting the charging current Ic, capacitor capacity C, and reference voltage Vr. On the other hand, the period T of the current suppression operation of the circuit can be expressed as T = Tc + △Toff + △Ton, so if the average value of the load current IL during the failure period is TLa, the current rate k for the limit ILm according to the conventional technology is k = ILa/ILm=ΔToff/T=ΔToff/Tcb+ΔToff+ΔTon. Since ΔToff in the above equation is naturally much smaller than Tc, the current rate k is a very small value.

Furthermore, as can be seen from the above description, in this embodiment circuit, unlike the conventional technology, the overcurrent detection transistor 11 is functionally separated from the current suppression transistor 15, and the above-mentioned time limit T can be freely selected in terms of design. In addition to the overcurrent detection transistor 11
This has the advantage of being able to use an element with a low base-emitter voltage Vbe so that it operates sensitively against overcurrent. In addition, since the transistor 11 is only turned on during the cut-off delay time ΔToff as described above, it can be used as a short-time rated element and there is little deterioration in detection characteristics. Note that in the above explanation, the current suppression operation of the output transistor 3 was simply cut off, but this is not limited to this; substantially the same effect as described above can be obtained even in the case of current limitation, if the limiting current value is made small. Of course. For example, if the load of the output circuit is inductive and it is difficult to shut off quickly and there is a risk of overvoltage, by connecting a high resistance in parallel between the collector and emitter of the output transistor 3, this difficulty can be avoided and at the same time Shutoff delay time can be shortened.

FIG. 4 shows an embodiment in which the timer circuit is constructed from a separate circuit. This embodiment differs from the previous embodiment in that a digital circuit is used for the timer circuit, and the same reference numerals as in FIG. 2 are used. It is attached. In this embodiment as well, the overcurrent detection transistor 11 becomes conductive when the current value signal Vs from the current detection resistor 4 exceeds a predetermined value due to an overcurrent, so that its collector output becomes "0" and the inverter 16 The flip-flop 17, which had been in the reset state, is set via the . The Q output of the flip-flop 17 becomes ``1'' due to this setting, enabling the AND circuit 18 shown above it to clear the clock pulse CP from the clock generator 19 from the counter 20.
and initiates its timed operation by initiating a count. Furthermore, since the output of the flip-flop 17 at the same time as it is set is also inverted and becomes "0", the NOR condition is satisfied in the NOR gate 21 to which this is input, and the output becomes "1", and the current is set as the current suppression command Sl. is applied to the suppression transistor 15. As in the previous embodiment, the current suppression transistor 15 is thereby turned on, and the output transistor 3 changes the load current IL to a short delay time ΔToff.
Shut off after. This pattern is shown in FIG. 5a for the current value signal Vs, and FIG. 5c shows the waveform of the current limit command Sl. In the NOR gate 21 described above, the input state before the NOR condition is met is "1" as the output of the flip-flop 17, while the count output COP from the counter 20 is of course still in the clear state, so the input state is "1". As shown in Figure b, it is "0",
Therefore, the NOR condition is satisfied only after the output of flip-flop 17 is inverted.

Now, due to the cutoff operation of the output transistor 3, the load current IL becomes zero, and therefore the current value signal Vs received by the overcurrent detection transistor 11 also becomes "0" as shown in the figure, so the transistor is turned off and the flip-flop 17 is set. The input returns to "0", but since the flip-flop 17 is in the set state, its output state remains unchanged, and the NOR gate 21
maintains the current state and continues issuing the current suppression command Sl until the counter 20 issues the count-up output COP. When the counter 20 as a time limit circuit counts up, that is, when a predetermined time limit comes, the counter 20 issues a count-up output COP as shown in FIG. 5b, so the NOR condition of the NOR gate 21 that receives this is It no longer holds true, and the current suppression command as its output is canceled.
The output transistor 3 closes the output circuit again after a short delay time ΔTon. Note that the count-up output from the counter 20 is output from the flip-flop 17.
This resets the flip-flop 17 and its Q
When the output becomes "0" and the AND gate 18 is closed, the counter 20 is cleared in response to the output, and the flip-flop 17 and the counter 20 return to a state in which they can receive the next overcurrent detection signal. Therefore, the count up output of counter 20
The waveform of COP becomes a pulse as shown in FIG.
The state in which the NOR condition of the gate is not satisfied does not change.
Thereafter, as in the previous embodiment, this embodiment circuit repeats the current suppression and its release operation at a cycle T until the output circuit recovers from the failure at time tr.
The rate at which the average value of the load current IL is reduced compared to the prior art is also the same as in the previous embodiment.

In the above descriptions of both embodiments, an example was introduced in which the current suppression transistor is used as the base circuit of the output transistor, but the current suppression circuit is not limited to this embodiment, and various known circuits may be adopted. be able to. For example, it is possible to insert the current suppression circuit directly into the output circuit, or the output transistor itself can act as a current suppression transistor. Further, as the time limit circuit, an analog circuit using a known CR circuit or a special circuit such as a timer may be freely used within the scope of the present invention.

〔Effect of the invention〕

As explained above, the overcurrent protection circuit according to the present invention can extremely shorten the time from detecting an overcurrent to releasing the time limit signal from the time limit circuit and entering the current suppression operation again. Since the effect of short-term overcurrents on the output transistor and load and the power loss in the output circuit can be minimized, the value of the average load current during the failure period in the output circuit can be significantly reduced compared to the conventional technology. can be reduced. This reduces wasted power consumption in the output circuit in the event of a failure, and significantly reduces power consumption for devices such as sensors that are used continuously over long periods of time and sequence controllers with multiple output circuits. effective. Further, the possibility that such power consumption causes heat generation in output circuit elements such as output transistors, load-side operation, or circuits to be controlled, thereby damaging the circuit elements, is prevented. As described above, the present invention has the effect of making the overcurrent protection function for the output circuit more complete than the conventional one, and also has the function of preventing the protection circuit device itself from being damaged by overcurrent.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an example of a conventional overcurrent protection circuit, Fig. 2 is a circuit diagram showing an embodiment of the overcurrent protection circuit of the present invention, and Fig. 3 is an embodiment circuit shown in Fig. 2. Figure 4 is a circuit diagram of an embodiment using a digital circuit for the timer circuit, Figure 5 is a waveform diagram of major signals in the embodiment shown in Figure 4. It is a diagram. In the figure, 1: internal circuit that issues a command to the output circuit, 2: output circuit, 3: output transistor as output circuit means, 4: current detection resistor as current detection means,
5, 15: Current suppression transistor constituting a current suppression circuit, 11: Overcurrent detection transistor as an overcurrent detection circuit, 12: Capacitor as a timed circuit element, 13: Constant current source as a timed circuit element, 14: Current Comparator constituting the suppression circuit, 20: Counter as a time circuit element, S:
command, Sl: current suppression command, Vs: current value signal.

Claims (1)

[Claims] 1. A current suppressing transistor whose collector is connected to the base of an output transistor of an output circuit that generates a predetermined load current based on a command to control and suppress the output current of the output transistor, and a current suppressing transistor between the emitter of the output transistor and ground. a current detection resistor connected thereto, an overcurrent detection transistor whose base is connected to a connection between the emitter and the current detection resistor, and which responds when a voltage at the end of the current detection resistor exceeds a voltage between the base and emitter; a capacitor connected in parallel between the collector and emitter of the detection transistor; a constant current source connected to the connection between the capacitor and the collector of the overcurrent detection transistor to charge the capacitor; An overcurrent protection circuit comprising: a voltage comparator to which a voltage is connected and whose inverting input is connected to the collector of the overcurrent detection transistor; and an output of the voltage comparator is connected to the base of the current suppression transistor.