JPH0466406B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and more particularly to a circuit for preventing malfunction of an input circuit or the like due to fluctuations in chip ground potential.

(Prior Art) For example, in a memory integrated circuit, a peak current is generated when an output buffer or other peripheral circuit operates, and this peak current flows into a ground terminal. At this time, the ground potential of the chip fluctuates due to the inductance of the grounding wiring (inside the chip and outside the chip), mainly the wiring outside the chip, which may cause the input circuits inside the chip to malfunction. It was hot.

In order to prevent circuit malfunctions caused by noise caused by fluctuations in the ground potential within the chip as described above,
Conventionally, an input circuit section in an integrated circuit has been configured as shown in FIG. 3, and the response of the input circuit has been slowed down to make it difficult to respond to the noise.
That is, in FIG. 3, the input signal of the input pad 31 passes through two-stage inverters 32 and 33 for waveform shaping, and becomes one input of a two-input NAND gate 34, and the output signal of the inverter 33 is input to a four-stage inverter 35. 38 and capacitors 39 and 40 to the other input of the NAND gate 34, and the output signal of this NAND gate 34 is inverted by an inverter 41.

In the input circuit shown in Fig. 3 above, even if a noise pulse is equivalently generated due to fluctuations in the ground potential during the low level period of the input signal as shown in Fig. 4, the normally expected time width of the noise pulse is If the delay time _t1 of the delay circuit is set longer than , the timings of the noise pulse appearing in the output signal of the inverter 33 and the noise pulse appearing in the output signal of the inverter 38 of the delay circuit will not match.
Output signal of NAND gate 34 and inverter 4
The output signal of 1 no longer contains noise pulses,
Malfunctions will no longer occur. In this case, the rise of the output signal of the inverter 41 is delayed by at least a time τ _A that is larger than the delay time t ₁ compared to the rise of the input signal.

As described above, the conventional input circuit section sacrifices the response speed to the rising edge of the input signal to prevent malfunctions due to noise. For this reason, especially in semiconductor integrated circuits that require high speed, delays in the input circuit section become a serious problem, making it impossible to employ the above-mentioned input circuit section.

(Problems to be Solved by the Invention) The present invention prevents malfunction of the input circuit when a noise pulse is generated at the ground potential of the chip due to the peak current when the output buffer or peripheral circuit operates as described above. This was developed to solve the problem that the response speed to the rising edge of the input signal is sacrificed due to the input signal when a noise pulse is generated at the chip ground potential. An object of the present invention is to provide a semiconductor integrated circuit that can prevent malfunction of the circuit.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor integrated circuit of the present invention includes a waveform shaping circuit that shapes an input signal, and a waveform shaping circuit that shapes the waveform of an input signal, and a waveform shaping circuit that shapes the waveform of the input signal from the first change to the next change. A delay circuit that delays the input signal by a certain period of time longer than the time width of the noise pulse generated during the time, and a delay circuit that delays the input signal by a fixed time longer than the time width of the noise pulse generated during the time, and a pulse generation circuit that generates a pulse signal for a certain period of time shorter than the time width of
a first logic circuit into which the output signal from the delay circuit and the pulse signal are input and which can operate for the time width of the pulse signal; and the output signal from the waveform shaping circuit and the output from the first logic circuit. and a second logic circuit to which the signal is input and removes the noise pulse without causing a response delay when the input signal changes next.

(Function) According to the above configuration, when a noise pulse occurs between the first change of the input signal (e.g. falling edge) and the next change (e.g. rising edge), the input signal is delayed by a certain period of time. A signal and a pulse signal that occurs for a certain period of time from the first change of the input signal are input to a first logic circuit, and the output signal from the waveform shaping circuit and the first
The output signal from the second logic circuit is input to the second logic circuit. Thereby, the noise pulse can be removed without causing a response delay when the input signal changes next time, and malfunction of the input circuit due to the noise pulse can be prevented.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the input circuit section of a semiconductor integrated circuit, where 1 is an input pad to which an input signal is applied, and 2 is an input pad to which an input signal is applied.
and 3 is a two-stage inverter (waveform shaping circuit) for shaping the input signal from the input pad 1; 4 is a delay circuit to which the output signal of the inverter 3 is input (for example, inverters 5 connected in three stages; 6 and 7 and capacitors 8 and 9 connected between the stages), 10 is a pulse generation circuit into which the output signal of the inverter 3 is input, and outputs a pulse signal over a certain period of time from a change in the input signal; 11 12 is a two-input NAND gate into which the output signal of the pulse generating circuit 10 and the output signal of the delay circuit 4 are input; 12 is a two-input NAND gate into which the output signal of the NAND gate 11 and the output signal of the inverter 3 are input; and 13 is a two-input NAND gate. This is an inverter that inverts the output signal of the NAND gate 12.

The operation of the input circuit will be explained with reference to FIG. During the low-level period from when the input signal falls until it rises, the peak current generated when the output buffer (not shown) or peripheral circuits in the semiconductor integrated circuit operates causes the ground potential within the integrated circuit chip to fluctuate, equivalently producing a noise pulse. Consider the case where this occurs. The input signal is waveform-shaped by two stages of inverters 2 and 3, and the output signal of this inverter 3 is input to a delay circuit 4 and a pulse generation circuit 10. The delay circuit 4 delays the input signal by a fixed delay time longer than the time width of the noise pulse, and also inverts the phase. Pulse generation circuit 10
detects changes in the falling edge of its input signal and generates a high-level pulse output over a certain period of time.
Note that the time width τ _B of the pulse output is shorter than the time width from the falling edge to the rising edge of the input signal. When this pulse output and the delayed output of the delay circuit 4 are subjected to NAND processing by the NAND gate 11, the NAND output is in phase with the output signal of the inverter 3, but its leading and trailing edges are the leading edges of the delayed output. and the trailing edge of said pulse output. This is because the output of the NAND gate 11 becomes "0" at least when the pulse output is "1", so while the pulse output is not generated, the NAND output is always "1".
This is because it can be said that the NAND gate 11 cannot operate. This NAND output and the output signal of the inverter 3 have different timings of noise pulses contained in each, so the NAND output of the NAND gate 12 and the output of the inverter 13 to which both of the above signals are input do not contain noise pulses. It disappears. Moreover, the leading and trailing edges of the output of the inverter 13 are defined by the output signal of the inverter 3.

Therefore, in the input circuit section, noise caused by fluctuations in the chip ground potential is generally caused by the peak current of the chip itself, so the pulse generation circuit is designed so that the time width of the output pulse is equal to the output operation time of the chip. 10, it is possible to prevent malfunctions due to the above-mentioned noise, and also eliminate delay in response to the rise of the input signal.

It should be noted that the present invention is not limited to the above-mentioned embodiment, and the combination of the delay circuit 4, pulse generation circuit 10, and NAND gate 11 performs a delay operation only for a certain period of time from the falling edge of the input signal. , thereafter, any circuit that outputs a constant level may be used.

[Effects of the Invention] As described above, according to the semiconductor integrated circuit of the present invention, it is possible to prevent malfunction of the input circuit when a noise pulse occurs at the chip ground potential without sacrificing the response speed to the rising edge of the input signal. Therefore, it is particularly effective in realizing semiconductor integrated circuits that require high speed performance.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing an input circuit section in an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a timing waveform diagram showing the circuit operation of FIG. 1, and FIG. 3 is a diagram of a conventional semiconductor integrated circuit. FIG. 4 is a logic circuit diagram showing the input circuit section, and a timing waveform diagram showing the circuit operation of FIG. 3. 1...Input pad, 2, 3, 5, 6, 7, 13
...Inverter, 4...Delay circuit, 10...Pulse generation circuit, 11, 12...NAND gate.

Claims (1)

[Claims] 1. A waveform shaping circuit that shapes an input signal; A delay circuit that delays the input signal by an amount of time, and a pulse that generates a pulse signal for a fixed period of time shorter than the time width from the first change to the next change in response to the first change in the input signal. a generation circuit; a first logic circuit into which the output signal from the delay circuit and the pulse signal are input and which can operate for the time width of the pulse signal; and the output signal from the waveform shaping circuit and the first logic circuit; 1. A semiconductor integrated circuit comprising: a second logic circuit into which an output signal from the circuit is input, and which removes the noise pulse without causing a delay in response when the input signal changes next time.