JPH0467120B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Related Technical Field of the Invention The present invention provides a plurality of electronic stage blasting caps having individual delay times for one command signal from an ignition device, and the ignition device connected in series or in parallel with the blasting caps to form at least one ignition circuit in which the individual In order to adjust the setting of the delay time (△T), the first signal stream F△ _T is supplied from the signal source to the integrator,
In a subsequent delay period starting simultaneously with said command signal in all detonators, the first signal stream
A second signal stream F _T that has a predetermined relationship with F△ _T
is applied to the integrator until reaching the integral value of the first signal stream already loaded into the integrator or until this integral value is reduced to zero, at which point the ignition is triggered. This invention relates to a method for staggered triggering of stage blasting detonators. Furthermore, the invention provides that an electronic stage blasting cap connected to an ignition device providing at least one time signal provides a first signal stream for loading the integrator during a loading period defined by the time signal. a signal source, and a controller for initiating a delay period during which, after the loading period has elapsed, a second signal stream is provided from the signal source for unloading or reloading the integrator; an ignition signal is generated when the value of the integrator is reduced to a predetermined value by unloading or when the integral value of the new loading of the integrator reaches the integral value already loaded during the loading period; The present invention relates to a device for triggering an electronic stage blasting cap configured as described above with a time difference.

PRIOR ART In a known method of the type mentioned above (German Patent Application No. 2945122), the ignition device
One pulse train is supplied to a number of connected stage blasting detonators, and the pulses of this pulse train are counted by a counter provided in each detonator. At the first count value of the counter, which is unique for each detonator, a pulse from a pulse generator provided in the detonator is applied to an integrator configured as an up/down counter, which is thereby loaded. or set (accumulated). This loading or setting ends for each detonator when its first counter reaches the second count value. The first counter then continues to count, and when it reaches the third count value, which is the same for all detonators, the integrator is switched inverted, so that the subsequent pulses of the pulse generator are counted down and the integrator is value is reduced. When the value of the integrator is reduced to a predetermined value, for example zero, ignition is triggered. The specific delay times of the individual igniters are formed in a known manner by starting the integration process at different points in time. That is, the first count values of the first counters of the individual integrators are set to different values. Therefore, the integrator loading periods of all detonators differ from each other in their starting times. The same delay that occurs with respect to the beginning of the load period also occurs at the end of the unload period. In this case, the detonator whose integrator loading (or accumulation into the integrator) started the last time could be the first to fire (because the integrator that started last would have a small (as all integrators are loaded to the same value), or when all integrators are loaded to the same value.
It is also possible to make sure that the detonator whose load begins last is the last to ignite.

Problems to be Solved by the Invention This known ignition method is expensive in terms of circuit technology.
This is because in each detonator, in addition to the counter, at least two comparators are required to detect the first and second count values of this counter.

It is therefore an object of the invention to provide a method of the type mentioned at the outset, which makes it possible to reduce the circuit engineering costs of the detonator.

Structure of the invention This problem is solved in the method of the type mentioned at the beginning.
Start feeding the first signal stream to the integrators of all detonators simultaneously, and set a separate delay time (△T) for each detonator.
is determined solely by the end state of the supply of the first signal stream, which depends on the time signal, and the ratio between the characteristic values of the first and second signal streams. After the electronic stage blasting caps have been installed in the blast hole and connected to each other, a voltage is generated in the blasting caps, in particular by the electromagnetic field, on the input side of at least some of the blasting caps, which voltage has already caused the respective electronic elements to The operating state may be set to an indeterminate state, with the result that subsequent adjustment of the individual delay time settings may not be carried out correctly. Furthermore, erroneous conditions may occur due to superimposed noise signals when adjusting the settings of the individual delay times.

Therefore, in order to increase the reliability when setting the individual delay times by means of the ignition device signal, according to an embodiment of the method of the invention, a first predetermined number of delay times can be set before the time signal from the ignition device. transmitting an enable pulse during a first time sequence and integrating one of the signal streams during the first time sequence;
Subsequently, a second predetermined number of start pulses different from the first predetermined number are transmitted during a second time sequence different from the first time sequence but having the same length, also during this period. One signal stream is integrated such that the deviation of the integral value formed during the first time sequence from the integral value formed during the second time sequence reaches a predetermined limit value after receiving a predetermined total number of pulses. Trigger the ignition only when the temperature is below.

This ensures that both the setting of the individual delay times and the triggering of the stage blasting caps only take place when the signal generated by the ignition device is processed in the desired manner by the staged blasting caps. Although this increases the cost of the individual electronic stage blasting caps somewhat, this is more than compensated for by the additional reliability of operation.

Advantageously, the first time sequence is a first predetermined constant frequency and the second time sequence is a second predetermined constant frequency. This allows easy control of the pulses during both time sequences.

If the enable pulse and the following start pulse are not processed correctly, the first and second
one or more times in succession, such that an output pulse can be delivered only if, at the end of at least one second time sequence, the deviation between the two integral values is below a predetermined limit value. , it is advantageous to reset the integral value to its initial value if the deviation between the two integral values is greater than a limit value. In this way, after at least the first second time sequence of the successive first and second time sequences, a predetermined condition occurs in the stage blasting primer, and the next pulse train is processed as desired. It becomes like this.

When using the embodiments of the invention described above, in order to increase reliability, the enable pulse and the start pulse as well as the subsequent signals for adjusting the individual delay time settings must be distinguished from each other in the stage blasting detonator. . To facilitate this, according to another embodiment of the invention: That is, at least the first
the shortest duration of the time signal is greater than the longest duration of the enable pulse by a predetermined factor, and at the end of the first pulse, when the integral of the signal stream exceeds a second predetermined limit value, one or more The first pulse received after the end of a predetermined number of second time sequences evaluates the received signal from the ignition device as a time signal.

In the known method of the type mentioned at the outset, the staged blasting cap is provided with an energy storage device which is supplied with energy from the outside and which supplies the elements of the electronic staged blasting cap and the ignition element. supplies energy for ignition. To prevent the stage blasting cap from being accidentally triggered in the presence of strong noise signals, the integral value reached at the end of the loading period or at the end of each first period is given a value of opposite sign or polarity. It is advantageous to replace and then integrate in the same direction as before. This allows sufficient energy to be supplied to the ignition element only when the stage blasting cap correctly processes the enable pulse and the start pulse.

Further, an apparatus of the type described above for carrying out the method of the present invention described above can be obtained with the following configuration. That is, the signal source can be switched and controlled to generate two signal streams having different values according to a predetermined ratio to each other.

The signal source has a pulse generator, a frequency divider is downstream connected to the pulse generator, and a first
The signal stream is from the pulse generator through the frequency divider,
Advantageously, an integrator configured as a counter is fed, and the second signal stream is fed directly from the pulse generator to the integrator configured as a counter.

In this case, the signal source only needs to have one pulse generator, thus ensuring that the pulses in the load period have the same frequency as the pulses in the delay period. During the load period, frequency division is performed by a frequency divider. The ratio of the pulse repetition frequencies of both periods need not be an integer ratio. Rather, the divider uses a non-integer division ratio (e.g. 3:8)
It can be configured so that it is possible. This is possible by using a known PLL circuit.

A further embodiment of the device according to the invention provides for the signal source to include two constant current sources with mutually different current values, and for the integrator to include a charging capacitor. In this case, loading and unloading of the integrator is advantageously carried out using analog circuit technology, with one constant current source forming the current source for the integrator current and the other constant current source forming the current sink.

Another device according to the invention for carrying out the method of the invention is a device for staggered triggering of electronic stage blasting primers of the type described above, in which the control device for each primer is configured to provide a time pulse train which is supplied as a train of pulses. A first signal stream is started at the time of the first pulse of the signal and maintained until the time of the mth pulse unique for each detonator, and a second signal stream is started at the time of the nth pulse of the time signal. In this case, m≦n is satisfied.

In order to increase the reliability when loading and possibly unloading the integrator and when generating the ignition signal, the device according to the invention, in which the control device includes a counter, provides a first memory element. established,
the sum of the number of pulses transmitted from the ignition device during the first time sequence and the subsequent second time sequence corresponds to a predetermined count value of the counter and formed in the integrator during the first time sequence; The first memory element is caused to be switched if the difference between the integral value and the integral value formed during the second time sequence is less than a predetermined value, and the memory element triggers the ignition only in the switched state. Configure it so that

In this way, the ability of the staged blasting cap to correctly receive and process the signal provided by the ignition device is first checked before it is put into a state in which it can generate an ignition signal. It is advantageous if the loading and possibly unloading of the integrator for generating the ignition signal is interrupted before the memory element is switched on. In order to further increase the certainty, it is advantageous to compare the value of the integrator with a predetermined limit value as claimed in claims 21 and 22.

To further increase reliability in electronic stage blasting caps, where an externally supplied energy storage is provided for the activation of each electronic element and for the activation of the ignition element, the energy storage is not activated until the memory element is switched. Advantageously, the charge is made such that the ignition element is charged to a value sufficient to ignite the ignition element.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an ignition circuit showing the configuration of one detonator Z _i in relatively detail, serving to illustrate the method and apparatus for staggered triggering of an electronic stage blasting detonator according to the invention.

As is clear from Fig. 1, k
Detonators Z ₁ to Z _k and associated igniters ZM are provided. The role of the ignition device ZM is to supply energy to each detonator and to supply a signal to each detonator, which signal determines the time T and starts ignition at a precise point in time.

Possible internal configurations of the electronic circuit of the detonator Z _i are shown by the dashed line in the block diagram. For the supply of energy or for the supply of the length of the delay period Δt and for the initiation of the triggering of all detonators Z ₁ to Z _k , the igniter ZM sends various coded signal streams to each detonator Z ₁ to _Zk , and this signal stream is decoded by a decoder D. Coding can be performed by frequency modulation, amplitude modulation or pulse code modulation.

In case of accurate detection of the code, the following sequence occurs. Energy storage configured as a capacitor
ES is charged via a rectifier G and supplies the operating voltage for the entire electronic circuitry and the energy for ignition of the electric ignition element ZE. To simplify the diagram, the electrical connections from the energy storage device ES to the entire electronic circuit are not shown. delay time module
The input 1 of the VZM is connected to a decoder D, the output 2 of which is connected to an electronic ignition switch SZ, for example a thyristor. In this delay time module VZM, the individual igniters Z ₁ to _{Z k}
A delay time ΔT is formed. This delay time △T
It is advantageous to carry out the formation digitally by comparing the states of internal counters, but if necessary it can also be carried out analogously, for example by comparing the charging voltages of several capacitors. After the delay time ΔT has elapsed, the electronic ignition switch SZ is closed, and the energy storage ES is then discharged via the ignition element ZE, which is ignited.

In FIG. 2, only the digital-based delay time module VZM is shown. In the programming phase, a signal is supplied via input 1 for a time T. At the start of the signal supply, switch S ₁ is closed, then the pulse generator
Pulses are supplied from IG to counter Z via frequency divider FT and switch _S1 to count up. The frequency divider FT operates in such a way that for an input of n pulses only m pulses are output from this frequency divider FT. At this time, the ratio of m and n is fixedly input to the frequency divider of each detonator. In this case, m/n·f _i ·T pulses are supplied to the counter Z during the closing time T of the switch S ₁ . that time,
f _i is the frequency of the pulse generator IG of the i-th detonator Z _i .

After the expiration of the time T, the switch S ₁ is opened and in the trigger phase the switch S ₂ is closed simultaneously with the opening of the switch S ₁ or with a corresponding signal, for example with a separate pulse IP indicating the ignition signal. , is closed after a delay from the opening of switch _S1 .
Then, pulses are supplied from the pulse generator IG to the counter Z, and the count value of this counter Z is counted down. If counter Z reaches its initial state again, a corresponding signal is then supplied via output 2 to ignition switch SZ, as shown in FIG. Counter Z with the above configuration
Alternatively, a second counter having the same initial state may be configured to count up the pulses. If this second counter reaches the same end state as the first counter, a corresponding signal is likewise sent via output 2 to the ignition switch.
Supplied to SZ.

As a simple example of this configuration, assume that switch _S1 is closed for a time T=3s. Pulse generator IG
If the frequency f _i of is 5000Hz, during this period 3s,
15000 pulses are supplied to the divided period FT. For example, in the case of a division of n=64 and m=24, 5625 pulses are supplied to counter Z. Then, after closing switch S ₂ , corresponding to the ratio of 5625 and 5000
After 1.125s, ignition element ZE is triggered. This is because after 1.125 s after the closing of switch S ₂ , counter Z returns to the counting state of the previous step, i.e. 5625
This is because the same count state as input pulses is reached.

If the pulse generator IG has a frequency _fi = 6000 Hz, then if the frequency divider FT has the same division ratio of 24:64, then during T = 3s 6750 pulses are supplied to the counter Z, and then , for the closure of switch S ₂ , f _i
= 5000 Hz, and corresponding to the ratio of 6750 to 6000, the ignition element ZE is ignited after 1.125 s.

According to this method, it is advantageous that the length of the delay period Δt no longer needs to be input fixedly into the detonators Z ₁ to Z _k , i.e. the length of the delay time Δt is determined by the detonator Z ₁
It is not specific to ~ _Zk , but the ignition device ZM allows the length of the delay time Δt to be varied by the time T. Furthermore, digital circuit technology makes it possible to make the delay time ΔT independent of the frequency f _i of the pulse generator IG and thus independent of the tolerances of the electronic components and ambient influences. . Therefore, the delay time △T
The accuracy of is determined only by the short-term stability of the pulse generator IG, which remains responsive to the requirements that arise in practice. With digital technology, the frequency divider FT also
It becomes independent of the tolerances of its components.

In all detonators Z ₁ to _{Z k} of the ignition circuit, each switch S ₁ is closed for the same length of time T, so that all detonators in the same time phase m have the same delay time ΔT. The time step m is divided by a fixedly programmed division ratio m/n.
It is provided in FT. The delay time interval Δt, which can be programmed arbitrarily by means of the ignition device ZM, is:
For all detonators Z ₁ to Z _k they have the same length, independent of their time phase.

In the case of the delay time module according to FIG. 3, which is constructed in digital circuit technology as in _FIG . be done. The first pulse is switch S ₁
is closed and the mth pulse reopens switch _S1 . In this case, the number m of m pulses is a number specific to the igniter. or, as the case may be, one pulse corresponding to a length that is an integer multiple of m is activated by the switch S ₁
You may also try opening it again. Therefore, if the closing time ΔT is the same as the delay time ΔT of the detonator in time stage m, ΔT=1/f _ZM ·m holds true. The closing time, ie the delay time, can therefore also be adjusted by means of the selectable frequency by the ignition device ZM.

During the closing time of switch S ₁ , the internal pulse generator
A counter Z counts up ΔT·f _i =N _i pulses according to the frequency f _i of IG.

Another pulse of the ignition device ZM, which is the actual ignition pulse, lasts for a predetermined time t in the trigger phase.
After T=1/f _ZM ·n, simultaneously close the switches S ₂ of all detonators Z ₁ to Z _k of the ignition circuit. As a result, the count value N _i is either counted down towards zero at the clock pulse frequency f _i or counted up to N _i by the second counter, similar to the counter Z described above. The count value is zero or N _i
Once reached, ignition is initiated via output 2.

Instead of a shift register, a counter equipped with a decoder, frequency divider, etc. can also be used.

FIG. 4 shows a delay time module constructed using analog circuit technology. For example, the second
By means of suitable signals, such as those described in connection with the figures, switch S ₁ is closed for a time T in the programming phase. During this time, the time capacitor CT receives the charging current I ₁ from the constant current source KSQ1
It is charged from the initial voltage U ₁ to the final voltage U ₂ by .
The ratio between the charging current I ₁ and the discharging current I _e that flows later is:
Same as ΔT vs. T. After the time tT, due to the triggering by the same ignition signal of the igniter ZM for all detonators Z ₁ to _{Z k} , the switch S ₂ is closed and the time capacitor CT is connected to the constant current source KSQ2 acting as a current sink. is discharged with a discharge current _Ie . If the time capacitor CT reaches the initial voltage U ₁ again, a signal is sent from the downstream comparator K via output 2 to the ignition switch SZ.
Ignition is started.

The adjustment of the time step m/n=I ₁ /I _e is determined by the ratio of the currents.

FIG. 5 shows another embodiment of a delay time module constructed using analog circuit technology.
In this embodiment, the adjustment of the time stage m of the detonator is carried out by the third
This takes place via a shift register SR corresponding to the diagram. For example, as explained in connection with Figure 3,
By means of a suitable signal, the switch _S1 is closed for a time ΔT via the shift register SR. During this time, the constant current I ₁ of the constant current source KSQ charges the time capacitor CT from the initial voltage U ₁ to the final voltage U ₂ . After the delay time ΔT has elapsed, switch S ₁ is opened. Then, by another ignition signal of the same igniter ZM for all detonators Z ₁ to Z _k , the switch S ₂ is closed, and the time capacitor CT is connected to the constant current source KSQ, which at this point operates as a current sink. Via
It is charged with a discharging current _Ie of the same magnitude as the charging current _I1 . If the time capacitor CT reaches the initial voltage _U1 , a signal is sent from the comparator K via the output 2 to the ignition switch SZ and the ignition is started. At that time, the variation in delay time △T is determined by the time capacitor
It depends only on the short-term tolerances of CT, constant current source KSQ and comparator K.

FIG. 6 shows another embodiment of the time input method shown in FIGS. 3-5. In the embodiment of FIG. 6, the frequency of the pulses emitted by the ignition device ZM during the time T in the programming phase is not constant but variable. That is, the time interval between the start pulse 0 and the pulse 1 that determines the first time stage 1 is different from the time interval between the pulse 1 and another pulse 2, and so on.

In this case, for the delay time ΔT _n of the m-th time step, ΔT _n = _n 〓 ¹ Δt _i generally holds.

For example, in practice it can be arranged such that the pulse 1 defining the first time step appears 10 ms after the start pulse 0, ie Δt ₁ =10 ms. The second pulse 2 appears after 30ms, i.e. after the start pulse 0
The third pulse 3 appears after 40ms, e.g. after 20ms, i.e. after start pulse 0.
It appears after 60ms, and the fourth pulse is e.g. after 500ms, i.e. after the start pulse 0.
Appears after 560ms, etc. A unique delay time ΔT _n is therefore defined for each time phase m by the ignition device ZM. In that case, always △T _n
>△T _n-1 . According to this method, for each time step m, an arbitrary delay time △T is set for the ignition device ZM
The advantage is that the settings can be adjusted according to the requirements and the blasting technology requirements can therefore be met even better, possibly with a smaller number of time steps. The trigger phase is initiated by a ignition signal from the igniter ZM, which is a continuous signal of the same type for all detonators Z ₁ to Z _k , and which triggers the closing and closing of the switch S _{2 .} , further steps as described in FIGS. 3 to 5 take place. When to open the switch _S1 can be determined in various ways.

Figure 7 shows the delay time △T at the ignition switch SZ.
Settings can be adjusted for the trigger as well as the delay time △T after the safety device release phase.
A circuit arrangement is shown which makes it possible to adjust the settings of and trigger the ignition switch _S2 . This circuit device connects to the ignition device via terminals 101 and 103.
It is connected to ZM, and this terminal 101, 103
First, a safety device release signal is received from , and then a signal for adjusting the setting of the delay time ΔT and a signal for ignition trigger are received. Furthermore, these signals
The illustrated circuit arrangement is supplied with current.

The foregoing takes place in unit 102.
Both terminals 101 and 103 are connected to the unit 102, and in order to avoid any problem even if there is a misconnection in terms of the polarity of the input line, the unit 102 also processes signals that are input as bipolar alternating current pulses. In order to make this possible, the signals input from terminals 101 and 103 are rectified in unit 102. The voltage available from the unit 102 is fed via the output 105 to a regulating circuit 168, which then charges a capacitor 172 and derives a regulated operating voltage UB from this charging voltage. This operating voltage UB is used as the operating voltage for the electronic components of the device. At this time, the charging voltage of the capacitor 172 is controlled in a predetermined manner, as will be explained later. Furthermore, at the beginning of the first supply signal, a pulse is taken from the output P of the regulating circuit 168, by means of which the various elements of the illustrated device are brought into an initial state, as will be explained later. The state will be reset.

Furthermore, the unit 102 has terminals 101 and 103.
each side edge or each leading edge of the alternating current pulse applied via the circuit transmits a short-duration signal on line 109 and a clock pulse signal following this short-duration signal on line 107; This clock pulse signal is applied via switch 104 to the count clock pulse input of counter 106. The operational functions triggered by this will be explained using the time diagram of FIG.

FIG. 8a shows alternating current signals input via terminals 101 and 103. First, a slightly longer signal is transmitted via terminals 101 and 103. The duration of this signal does not have to be precise; it simply needs to be large enough to charge capacitor 172 to a predetermined minimum voltage. The charging voltage of capacitor 172 is shown in FIG. 8d. The charging voltage of the capacitor 172 is large enough to supply the necessary operating voltage to the electronic elements, but not yet large enough to ignite the ignition element ZE when the ignition switch SZ is closed. do not have.

As the next signal, several symmetrical pulses each of pulse duration ta appear. This pulse is first supplied to the count clock pulse input side of the counter 106 via the closed switch 104, and counting is started from the zero position.
The counter 106 is then set to the zero position by the already mentioned starting pulse P via the OR element 148, the line 149 and the input MR of the counter 106. As long as the counter 106 is in the zero position, this counter 130 is also held in the zero position via the input MR of a further counter 130.

As soon as counter 106 is no longer in the zero position, counter 130 can count the clock pulses supplied via AND element 118 from pulse generator IG. The period of this clock pulse is then significantly smaller than the pulse duration ta of the alternating current pulses supplied via terminals 101, 103. AND element 118 is enabled by the corresponding output signal of flip-flop 116. Flip-flop 116 is set to this position by start pulse P via OR element 114. The counter 106 further counts the input alternating current pulses, and the counter 130 correspondingly counts the input alternating current pulses.
Count the clock pulses of the pulse generator IG. As a result, the count positions of both counters increase at different rates. Regarding the situation, the case of the counter 106 is shown in FIG. 8b.
The case of counter 130 is shown in FIG. 8c. At this time, the count position of the counter is shown to rise continuously for the sake of simplicity, but in reality, the count position of the counter rises in stages.

As soon as counter 106 reaches position NR,
A signal is sent out via line 117, which signal is fed to AND elements 122,142. AND element 122 connects line 1 from flip-flop 164 to
It is enabled by a signal sent via 65. Flip-flop 164 is set to the appropriate position by starting pulse P. The aforementioned signal is therefore provided from line 117 via OR element 124 to pulse shaper 126 . Pulse shaper 126 generates short pulses that are applied to the input side of counter 130.
The counter 130 is supplied to the CMP, which inverts the sign of the value of the counter 130, that is, converts it into a negative count value of the same magnitude. This can be seen from Figure 8c.

The other input side of the AND element 142 is supplied with a signal from the output side of the decoder 132. A decoder 132 is connected to the output 131 of the counter 130 and sends out a signal as long as the count position is at a predetermined value, here indicated by ZEU.
Therefore, this configuration makes it possible to deal with the following situations in particular. That is, noise pulses may be superimposed on the pulses generated by the ignition device ZM, which cause the counter 106 to count more rapidly than in the normal case, or thereby cause the counter to count faster than in the normal case. Or, the igniter ZM becomes a more uncertain count than
When loading the igniter with a blasting charge before connecting the detonator to the igniter, noise signals may be received and the device may be put into an undesired state. .

Therefore, when the counter 106 reaches the counter position NR but the counter 130 has not yet reached the count position ZEU below the counter position NR, a signal is sent to the output side of the AND element 142. This signal is supplied to one input side of an AND element 146 via an OR element 144. The other input side of AND element 146 is connected to line 165, and a signal from line 165 enables AND element 146. Therefore,
A corresponding input of the OR element 148 is supplied with a signal which, via the line 149 and the input MR of the counter 106, resets this counter 106 to the zero position and resets it to the next safe, which is repeated at least once. Prepares counter 106 for the device release process. Thereby, counter 130 is also set to zero.

When the counter 106 reaches the position NR, the counter 130 exceeds the count position ZEU,
If the position ZEO is also exceeded, this means that
It is detected by a decoder 134, which is connected to the output side 131 of the counter 130 in the same way as the decoder 132, and then an output signal is sent out from the decoder 134, which output signal is sent to the counter via an OR element 144, an AND element 146, etc. 106 to its starting position. This reset occurs as soon as counter 130 reaches count position ZEO, even before counter 106 reaches count position NR. Therefore, several alternating current pulses obtained from the ignition device ZM, for example due to a bad contact or a short circuit, are connected to the lines 101,1.
It is possible to deal with the situation where the information is not entered correctly via 03.

When determining both counting positions ZEU and ZEO, it is assumed that the clock pulse frequency of the pulse generator IG is within specified limits, which has been measured during the manufacture of the device and before assembly of the detonator. Ru.

If the pulses from the ignition device ZM are input accurately until they reach the count position NR of the counter 106, and this value is also established in the ignition device ZM, the next pulse will be sent to this ignition device ZM.
It is transmitted with twice the pulse period. During this transmission time, counter 130 counts forward from a negative count position. This negative count position is achieved by sign reversal, as described above. For technical reasons, the sign reversal means can also be implemented here, instead of as described above, in such a way that the counting direction of the counter 130 can be reversed.

As soon as the counter 106 reaches the count position NE which is equal to 1.5 times the count position NR because the pulse period has doubled, the counter 130
should reach the zero position again in the ideal case. However, since the count clocks of both counters 106 and 130 are asynchronous with each other and a small frequency fluctuation occurs, when counter 106 reaches count position NE, counter 130 differs from zero position by K position. If a deviation occurs, ie at least a count position -K or a position not higher than count position K is reached, the device shall process the pulses obtained from the ignition device ZM normally. This is detected at decoder 140. This decoder 140, like the other decoders, is connected to the output 131 of the counter 130. Therefore, if the deviation of the counter position of the counter 130 from the zero position is less than the K position, a signal is sent to the output 141 of the decoder 140. This signal, in conjunction with the signal sent on line 121 from count position NE of counter 106, causes a signal to be placed on the output of AND element 162, so that flip-flop 164 is switched and now on line 165. A signal is sent on line 167 instead. Additionally, the output signal of AND gate 162 switches flip-flop 154 via OR element 152, sets counter 106 to the zero position via OR element 148, etc. By doing so, counter 130 is also set to the zero position, as seen in FIG. Switching of flip-flop 164 completes the safety release phase. This is because flip-flop 164 is no longer reset and the programming phase can begin.

However, if the count position NE of the counter 106 deviates from the zero position by more than the K position, a signal is emitted from the output 143 of the decoder 140. This signal cooperates with the signal sent over line 121 and the signal sent over line 165 of the now dormant flip-flop 164 to provide a signal at the output of AND element 166. send it out. This signal again sets counter 106 via OR element 148 and line 149, so that counter 130 is also set to the zero position. As a result, the device is ready for operation to receive a new series of safety release pulses;
This safety release pulse is basically repeated at least once by the ignition device ZM.

After switching flip-flop 164, line 167
A signal sent to regulator circuit 168 via capacitor 172 charges to a maximum voltage.
This maximum voltage is made possible by the signal just then being supplied by the ignition device ZM, as can be seen in FIG. 8a. To that end, the pause time tp
is provided. After this pause time tp, the period te
A new safety disengagement phase begins, which requires . In the case of flip-flop 164 switching,
The signals obtained in this case and sent via line 109 in the manner described above in turn cause counter 106 and counter 130 to be activated on each side of the alternating current pulse.
is also set to a new zero position, and a pulse sent via line 107 immediately after this alternating current pulse switches counter 106 to position 1. As a result, counter 130 is a pulse generator.
IG clock pulse signals can be counted. This is because flip-flop 116 is still in position to enable AND element 118. Such a periodic reset to the zero position is illustrated in FIGS. 8b and 8c.

At the end of the second safety release phase te, a relatively long pause period occurs after the last edge of the alternating current pulse. During that pause period, counter 130 exceeds position ZPU. Counter 130 cannot exceed this position ZPU before this.
This is because the duration of each pulse during the safety release phase is very short compared to this phase and both counters 106, 130 are repeatedly reset to the zero position before reaching position ZPU. During the pause period, as soon as the counter 130 reaches the position ZPU, the decoder 138, which is connected like the other decoders to the output 131 of the counter 130, sends out an output signal. Counter 106 is still at position 1
Therefore, a signal is sent to line 115, and a signal is also sent to line 167 of flip-flop 164. As a result, AND element 156 provides an output signal to reset flip-flop 154 via OR element 158.
Therefore, a reset pulse to counter 106 cannot be sent via AND element 160 thereafter. In this way, the safety release pulses being processed are distinguished from the programming pulses for longer duration delay time adjustments. This will be explained later.

However, since the pause period after each safety release phase is longer than the longest programming pulse, counter 130 will eventually reach position ZPO.
When this position ZPO is reached, the decoder 136, which is connected like the other decoders to the output 131 of the counter 130, sends out an output signal. Counter 106 is still at position 1 and line 11
Since the signal is sent to 5, AND element 15
0, therefore OR element 152 sends out an output signal. This output signal resets counters 106, 130 via OR element 148 and line 149 on the one hand, and resets flip-flop 154 again on the other hand. As a result, another reset pulse is subsequently sent out again via the AND element 160 for zeroing the counter 106. By doing so, the counter 13
0 is also set to zero. In this way, rest periods in the input alternating current pulses, or more precisely, relatively long-lasting sustained periods of approximately constant pulse voltage, are distinguished from subsequent programming pulses. At this point, it should be pointed out that Figure 8 is not to scale.

On the first programming pulse of period Δt, counter 106 is switched to position 1 and counter 1
Start counting from the zero position of 30. Since the minimum value of the pulse period Δt of the programming pulse is such that the counter 130 exceeds the position ZPU,
As long as counter 106 is still in position 1, flip-flop 154 is switched. As a result, AND element 160 is cut off again, following which:
Subsequent edges of the input alternating current pulse can no longer generate a reset pulse for the counter 106. On the other hand, the counter 130 is
After counter 106 is no longer at position 1, position ZPO is reached on subsequent programming pulses. As a result, at this time no signal is sent over line 115, so AND element 150 is cut off and flip-flop 154 is not reset again.

In this way, counter 130 counts the pulses of pulse generator IG until counter 106 reaches position NK. This position NK is previously given and fed to the decoder 108 via a multiplex input 110 . Furthermore, this decoder 108
is connected to the output 111 of the counter 106. In case of a match between the respective signal combinations input from both multiple input sides, an output signal is sent out from the decoder 108 and supplied to the AND element 112. At this time, AND element 112 is enabled via line 167. Therefore, flip-flop 116 is switched and AND element 11
8 is blocked. As a result, the clock pulses from the clock pulse generator IG no longer reach counter 1.
30 is not entered. Therefore, at this instant, the reached position of the counter 130 continues to be maintained, so that this position, as already explained, provides a measure for the programmed delay time.

However, regardless of this, further programming pulses are input to the counter 106 until the counter 106 has finally counted completely and an overflow signal is emitted from the output 123. This overflow signal opens switch 104 so that counter 106 continues to be maintained in this final position and cannot return to the zero position. Otherwise, the counter 130 would also be set to zero, thereby eliminating the adjusted delay time.

Additionally, the overflow signal sent via line 123 is provided to a pulse shaper 126 via an OR element 124. The pulse shaper 126 again passes short pulses to the input side of the counter 130.
The signal is sent to CMP, and therefore the count position of counter 130 is sign-inverted. This has already been explained in the case of the safety release phase. Additionally, flip-flop 116 is switched again via OR element 114. As a result, the AND element 118 is enabled, and the counter 130 receives the pulse from the clock pulse generator IG again and counts toward zero from the negative position obtained by the sign inversion.

As soon as the counter 130 reaches the zero position,
The preprogrammed delay time tv must be extinguished after the last programming pulse counted by the counter 106 so that ignition can be triggered. This is done as follows. That is, when counter 130 reaches the zero position from a negative value, it sends a signal to AND gate 170, which is enabled by the overflow signal sent via line 123. As a result, the output signal of the AND element 170 can close the ignition switch SZ. Thereby, the electric charge stored in the capacitor 172 is discharged through the ignition element ZE, and the electric charge stored in the capacitor 172 is discharged through the ignition element ZE.
Ignite ZE.

By the last programming pulse when counter 106 reaches its final position, lines 101, 103
The signal supply via is cut off. At this time, the ignition device ZM may cut off the supply of electric energy, or the detonator with the shortest delay time may cut off the connection with the ignition device ZM by a trigger. Therefore, capacitor 172 is no longer supplied with energy during the delay time and the voltage applied to capacitor 172 gradually drops due to energy consumption by the illustrated device. In order to ignite the ignition element ZE, a predetermined minimum voltage is required across the capacitor 172, so the unit 16
8 monitors this voltage, and this voltage
If ZE falls below a predetermined limit value where it is not possible to trigger it reliably, the ignition switch SZ is activated as in the normal case and the ignition is activated, even if the predetermined delay time has not yet elapsed. is triggered. If this is not done, the following situation will occur: That is, the operating voltage UB is large enough to operate the electronic device, and the AND element 170 eventually closes the ignition switch SZ via its output signal, but at this point the voltage stored in the capacitor 172 is The energy being released is no longer high enough to trigger the igniter, so after blasting, an unignited charge is left in the mine, and this can occur. Must be avoided at all costs. However, such a situation can only occur in the event of a fault, in particular if the capacitance of capacitor 172 is too small due to an unacceptably large deviation.

By means of the above-mentioned device with a safety release phase that preprograms the delay time, the adjustment of the delay time setting and the triggering of the ignition is possible.
Since this can only be done by pulses from the ignition device ZM provided for this purpose, safety can be extremely increased.

The circuit arrangement according to FIG. 7 requires, for example, that a device in the receiver be triggered by a signal transmitted from the transmitter to the receiver via a possibly disturbed or noisy path. , which can also generally be used advantageously if it is necessary to ensure that noisy signals are ever triggered. The trigger signal is then transmitted immediately after the last safety release phase and is evaluated only when flip-flop 164 switches.

Effects of the invention In the method of the invention, the integrators of all detonators connected to the ignition device are started together (simultaneously) at the occurrence of the time signal, so that the starting point of the loading period can be set individually for each detonator. There's no need. The end of the loading period can be defined individually for each detonator, but the length of the loading period can also be the same for all detonators. In either case, the cost of the comparator required for the detonator circuit can be reduced. Reducing the circuit cost of detonators is important. This is because the detonator circuit is only used once,
This is because it is destroyed when the loaded gunpowder explodes. Therefore, the ignition circuit should be constructed as simply and inexpensively as possible.

In the case of the device of the present invention, the values of both signal streams are in a relationship with each other having a fixed division ratio, and this division ratio is specified for each detonator. This allows the ratio of the length of the loading period to the delay period to be different for each detonator, with the loading period having the same length for all detonators. Furthermore, the delay period can be selectively made longer or shorter than the load period.

In a further device according to the invention, for example, the control device is provided with a counter that counts up to the value n (modulo n counter). A comparator makes it possible to detect when the count value m is reached. In this case only one comparator is required in addition to one counter. Instead of a counter,
A shift register activated by the first pulse of the time signal and clocked by the pulse of the time signal may be used. Such a shift register has n shift stages and has an output at the nth and mth shift stage.

[Brief explanation of the drawing]

FIG. 1 serves to illustrate the method and apparatus for staggered triggering of an electronic stage blasting detonator of the present invention. FIGS. 2 to 5 are diagrams showing various embodiments of the delay time module VZM of the detonator Zi;
FIG. 6 is a diagram showing a modified embodiment of FIGS. 3 to 5, FIG. 7 is a diagram showing a circuit device for adjusting the delay time setting and triggering after the safety device release phase, and FIG. FIG. 8 is a diagram showing a time diagram for explaining the functional operation of the circuit device shown in FIG. 7; ZM...Ignition device, _Z1 ~ _Zk ...Detonator, G...Rectifier,
D...Decoder, ES...Energy accumulator, VZM...Delay time module, ZE...Ignition element, SZ...Ignition switch, IG...Pulse generator, FT...Frequency divider, 2,
106, 130... Counter, SR... Shift register, KSQ... Constant current source, K... Comparator, CT... Time capacitor, 168... Adjustment circuit, IG... Clock pulse generator, 126... Pulse shaper, 108, 1
32, 134, 136, 138, 140...decoder.

Claims (1)

[Claims] 1. A plurality of electronic stage blasting caps have individual delay times (ΔT) with respect to a command signal from an ignition device, and the ignition device is connected in series or with the electronic stage blasting caps. are connected in parallel to form at least one ignition circuit in which the individual delay times (ΔT) of each of these detonators are determined during the charge or load period determined by the time signal from the ignition device. For setting adjustment, a first signal stream (F△ _T ) is fed from the signal source to the integrator, and in a subsequent delay period that starts simultaneously with said command signal in all detonators, the first signal stream ( F△ _T )
a second signal stream (F _T ) in a predetermined relationship to
is applied to the integrator until reaching the integral value of the first signal stream already loaded into the integrator or until this integral value is reduced to zero, at which point the ignition is triggered. In the method of staggered triggering of stage blasting detonators, the first signal stream to each integrator of all detonators is started at the same time, and a separate delay time (△T) is set for each detonator in time. The electronic stage blasting cap is characterized in that it is determined solely by the end state of the supply of the first signal stream depending on the signal and by the ratio between the characteristic values of the first and second signal stream. How to trigger with . 2. An electronic stage according to claim 1, in which the ignition device generates a series of n pulses and in each detonator an individual delay time (ΔT) is formed by subtracting a corresponding number m of these pulses. A method of triggering blasting caps at different times. 3. A method for staggered triggering of an electronic stage blasting cap according to claim 2, wherein the igniter generates an adjustable irregular pulse train. 4. A method for staggered triggering of an electronic stage blasting cap according to claim 2, wherein the igniter generates a regular pulse train. 5. The signal stream has a pulse repetition frequency, with a fixed frequency division smaller than 1 between the pulse repetition frequency of the first signal stream (F△ _T ) and the pulse repetition frequency of the second signal stream (F _T ). The electronic stage blasting cap according to any one of claims 1 to 4 is triggered with a time difference, in which a ratio is set and the frequency division ratio determines the individual delay time. Method. 6. A method of triggering an electronic stage blasting cap at different times according to any one of claims 1 to 4, using a constant current as a signal flow. 7 Let the first signal stream be the same as the second signal stream, and the feed of the first signal stream to the integrators of all detonators:
Trigger the electronic stage blasting cap according to any one of claims 2 to 4 with a time difference, which continues for a time determined individually for each detonator by a time signal of an ignition device. Method. 8 transmitting a first predetermined number of enable pulses during a first time sequence prior to the time signal from the ignition device and integrating one of both signal streams during the first time sequence; Subsequently, a second predetermined number of start pulses different from the first predetermined number are transmitted during a second time sequence different from the first time sequence but having the same length, also during this period. said one signal stream is integrated, and the deviation between the integral value formed during the second time sequence and the integral value formed during the first time sequence is a predetermined value after receiving a predetermined total number of pulses. 2. A method for staggered triggering of an electronic stage blasting cap as claimed in claim 1, wherein ignition is triggered only when the voltage is below a limit value. 9. The electronic stage according to claim 8, wherein the first time sequence is a predetermined first constant frequency and the second time sequence is a predetermined second constant frequency. A method of triggering blasting caps at different times. 10 The first and second time sequences are repeated one or more times in succession, and at the end of at least one second time sequence, the output pulse is generated only if the deviation between both integral values is below a predetermined limit value. The electronic stage blasting cap according to claim 8 or 9, wherein the electronic stage blasting cap according to claim 8 or 9 is configured such that when the deviation between the two integral values is larger than a predetermined limit value, the integral value is reset to the initial value. How to turn on and trigger. 11 the minimum duration of the at least first time signal provided by the ignition device is greater than the maximum duration of the enable pulse by a predetermined factor;
by the first pulse received after the end of one or a predetermined number of second time sequences when the integral value of the signal flow exceeds a second predetermined limit value at the end of the pulse of the ignition device. A method for triggering an electronic stage blasting cap with a time difference according to any one of claims 8 to 10, wherein the received signal is evaluated as a time signal. 12. Comparing the integral value reached at the end of the first time sequence with a predetermined limit value and resetting the integral value to the initial value if the integral value exceeds this limit value. A method of triggering the electronic stage blasting cap described in item 11 with a time difference. 13. An electronic stage according to claim 12, in which the integral value reached at the end of the loading period or at the end of each first time sequence is replaced by a value of opposite sign or polarity, and thereafter integrated in the same direction as before. A method of triggering blasting caps at different times. 14. If the stage blasting detonator is equipped with an energy store, which is supplied with energy from the outside and supplies energy for the elements of the electronic stage blasting cap and for the ignition of the ignition element, the energy storage limiting the value of the energy supply to the accumulator to a value between the value for the power supply of each electronic element and the value for the ignition of the ignition element, the limit being determined by one or a predetermined number of second time sequences; The electronic stage blasting is carried out at different times until the deviation between both integral values falls below a predetermined limit value and maximum energy is supplied to the energy accumulator at the end of the electronic stage blasting process. How to trigger. 15 An electronic stage blasting cap connected to an igniter ZM supplying at least one time signal (T) loads the first signal stream into the integrators Z, CT during a load period defined by the time signal. signal sources IG, FT; KSQ1, KSQ2, and a delay in which the second signal stream for unloading or new loading of the integrator is provided by the signal source after the loading period has elapsed. A control device S ₁ , S ₂ is provided for starting a period, in which the value of the integrator is reduced to a predetermined value by unloading, or the integral value for a new loading of the integrator is already loaded in the loading period. In a device for triggering an electronic stage blasting cap with a time difference, the ignition signal is generated when an integral value is reached, each signal source IG, FT; KSQ1, KSQ2,
1. A device for triggering an electronic stage blasting cap with a time difference, characterized in that the device is configured to be switchable and controllable to generate two signal streams with different values according to a predetermined ratio. 16 The signal sources IG, FT are equipped with a pulse generator IG, to which a frequency divider FT is downstream connected, and the first signal stream is routed via the frequency divider FT to the pulse generator. From the pulse generator IG, an integrator Z configured as a counter is supplied, and a second signal stream is supplied directly from the pulse generator IG to the integrator Z configured as a counter. 16. A device for triggering the electronic stage blasting cap according to item 15 at different times. 17. The electronic stage blasting cap according to claim 16, wherein the signal source has two constant current sources KSQ1 and KSQ2 having different current values, and the integrator has a charging capacitor ZT. A device that triggers at different times. 18 An electronic stage blasting cap connected to an ignition device ZM providing at least one time signal T provides a first signal stream for loading the integrators Z, CT during a loading period defined by the time signal. Equipped with signal sources IG, FT; KSQ1, KSQ2,
and a control device which, after the expiration of the loading period, initiates a delay period during which a second signal stream for unloading or new loading of the integrator is supplied from the signal source.
S ₁ and S ₂ , and the value of the integrator is reduced to a predetermined value by unloading, or the integral value at the time of new loading of the integrator reaches the integral value already loaded during the loading period. In a device for staggered triggering of electronic stage blasting detonators, _the ignition signal _is generated when The first signal stream is configured to start at the time of the pulse and maintained until the time of the mth pulse unique for each detonator, and the second signal stream is configured to start at the time of the nth pulse of the time signal. device for triggering electronic stage blasting caps at different times, characterized in that m≦n. 19. Apparatus for staggered triggering of an electronic stage blasting cap according to claim 18, wherein the first and second signal streams are the same. 20 the control device S ₁ , S ₂ includes a counter 106 and is provided with a first memory element;
The sum of the number of pulses transmitted by the igniter during the time sequence and the following second time sequence corresponds to a predetermined count position NE of the counter 106, and during the first time sequence the integrator Z,
the first memory element is switched if the difference between the integral value formed at ZT and the integral value formed during the second time sequence is less than a predetermined value;
19. An apparatus for staggered triggering of an electronic stage blasting cap as claimed in claim 18, wherein the memory element 164 is configured to trigger ignition only in the switched state. 21 Monitoring circuit 132, 134, 136, 13
8,140 are provided, and the integral value at the end of the first time sequence is a first respective predetermined limit value.
The electronic stage blasting cap according to claim 20, wherein the monitoring circuit is configured to reset the integrator Z, ZT, 130 and the counter 106 to initial values when the electronic stage blasting cap is outside ZEU, ZEO. A device that triggers at different times. 22 After switching the memory element, the integral value at the end of one time signal is equal to the second predetermined limit value ZPO, ZPU.
The monitoring circuits 132, 134, 1
36, 138, 140 are integrators Z, ZT, 130
22. An apparatus for staggered triggering of an electronic stage blasting cap as claimed in claim 21, wherein the device is configured to reset the detonator and the counter to initial values. 23 An externally supplied energy storage is provided for the actuation of each electronic element and the ignition element, the first memory element 164 in the switched state first setting the energy storage 172 to the ignition element ZE.
23. A device for staggered triggering of an electronic stage blasting cap according to any one of claims 20 to 22, which is configured to charge the detonator to a value sufficient for ignition of the detonator.