JPH0467374B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a programmable frequency divider that divides an input clock pulse according to externally applied data.

Conventional configurations and their problems In recent years, programmable frequency dividers have been used in a variety of electronic devices, and as the functions of devices have diversified, the number of frequency dividers used per device has gradually increased. Tend.

FIG. 1 shows an example of the configuration of a conventional programmable frequency divider. In the figure, 1 is an N-stage presettable counter that counts clock pulses (hereinafter simply referred to as a clock), 2 is an N-input NAND gate, and 3 is a data setter that supplies arbitrary data to the N-stage presettable counter 1.

Output Q ₁ ~ _{Q N} of N-stage presettable counter 1
is connected to the input of the N-input NAND gate 2, and the output of the N-input NAND gate 2 becomes a frequency-divided output and is also connected to the LOAD terminal of the N-stage presettable counter 1. D ₁ to D _N of data setter 3
The data set by is input to data inputs D ₁ to D _N of the N-stage presettable counter 1.

The operation of the conventional programmable frequency divider configured as described above will now be described with reference to the timing chart of FIG. The N-stage presettable counter 1 sequentially counts the clocks input to its CK terminal and outputs them to outputs Q ₁ to Q _N . Output Q ₁
~Q _N is connected to the input of N-input NAND gate 2,
Therefore, the output Q ₁ of N-stage presettable counter 1
~Q Only when all _N become "1", the N-input NAND gate 2 becomes active and outputs "1". Since the output of the N-input NAND gate 2 is connected to the LOAD terminal of the N-stage presettable counter 1, the outputs Q ₁ to Q _N of the N-stage presettable counter 1 are connected to the data setter 3 at the next clock timing. The data that matches the data input D ₁ to D _N is preset according to the data set in Q ₁ to D N.
Q Output to _N. At the same time, the output of the N-input NAND gate 2 becomes "0", and the N-stage presettable counter 1 sequentially counts the input clocks from the setting data. Thereafter, the above operation is repeated, and a frequency divided waveform according to the data set by the data setter 3 appears in the frequency division output, and the set data D and the frequency division number
The relationship between C _{and N} is as follows.

Frequency division number C _N = Setting data + 1 When dividing multiple clock trains by an arbitrary frequency division number, conventionally, the required number of programmable counters as shown in Figure 1 were simply provided to achieve the purpose. Achieved. However, in general N
The stage presettable counter has a complex configuration, and as the number of stages increases, the number of constituent elements also increases, and when multiple such frequency dividers are used, problems such as an enormous number of elements arise. have.

Purpose of the Invention As mentioned above, the present invention provides a programmable frequency divider that has the same function with a relatively small number of elements, to replace the conventional programmable frequency divider, which requires an enormous number of elements as the number of stages and components increases. The purpose is to realize a frequency converter.

Configuration of the Invention Before explaining the configuration of the present invention, the basic principle of the present invention will be explained.

Generally, if the period of the divided clock is T _i , the division number is C _N , and the period of the divided output is T ₀ , then T ₀ = T _i ×C _N ...(1). . Now, assuming that C _N =x ₁ +x ₂ =2 ^M ×x ₁ /2 _M +x ₂ =2 ^M ×X ₁ +x ₂ ...(2) (however, X ₁ =x ₁ /2 ^M ), then T ₀ = T _i × (2 ^M × X ₁ + x ₂ ) = {T _i × 2 ^M ) × X ₁ } + ₍ T _i × x ₂ ) = T _{i M ×} However, T _iM = T _i ×2 ^M ). Equation (3) above describes a clock with a period of T _i .
Instead of counting (dividing) C _N times, T _iM is obtained by counting a clock with a period of T _i 2 ^M times.
This shows that it is possible to count a clock with a period of T _i x ₁ times and add a clock with a period of T i x ₂ times.

This relationship is shown in FIG. Clock 1 in the figure shows a clock with a period T _i , and clock 2 shows a clock with a period T _iM.
Clock 3 is a clock obtained by counting the clock with a period of T _i x ₂ times, and the output is a clock with a period of T ₀ = T _i ×C _N = T _iM ×X ₁ + T _i ×x ₂ . This shows that a divided output can be obtained.

FIG. 4 is an example of a circuit that realizes the above-mentioned idea, and is a circuit that is the basis of the configuration of the programmable frequency divider of the present invention. FIG. 4 shows an M-stage counter 4 (first counting means) that counts a clock with a period T _i 2 ^M times to create a clock with a period T _iM ;
An N-M stage presettable counter 5 (second counting means) that counts the output of the M-stage counter 4 a predetermined number of times (X ₁ time), the M-stage counter 4 and the N-
An M-stage presettable counter 6 starts counting a predetermined number of times (x ₂ times) at the same time as the M _- stage presettable counter 5 finishes counting 2 ^M x X ₁ times. (third counting means) and an N-M presettable counter 5 and a data setter 3 for setting a predetermined count number to an M-stage presettable counter 6, and an M-stage counter 4 and an N-M stage counter. When the presettable counter 5 is in counting operation, M
The stage presettable counter 6 is not counting, and conversely, when the M stage presettable counter 6 is counting, the M stage counter 4 and the N-M stage presettable counter 5 are not counting. Configured to stop working.

FIG. 5 shows another circuit that realizes the same operation as FIG. 4, in which the operations of the M-stage counter 4 and the M-stage presettable counter 6 in FIG. The presettable counter 7 can switch between counting ^2M clocks and counting x ₂ times, and switches its operation with reference to the output of a switching flag 8. This flag 8 is M as described above.
In addition to switching the operation of the stage presettable counter 7, it also switches whether the count output of the M stage presettable counter 7 is supplied to the N-M stage presettable counter 5 or used as the final frequency division output. This signal is used as a control signal for the demultiplexer 9, and is set when the N-M stage presettable counter 5 counts a predetermined number of times x ₁ , and is reset when the final divided output is output.

What should be noted in the circuits of FIGS. 4 and 5 is that the frequency T _iM of the clock input to the N-M stage presettable counter 5 is the same as that of the M stage counter 4 or the M stage presettable counter 7. can be freely selected by selecting the number of stages M. That is,
When configuring a plurality of programmable counters, a plurality of M-stage counters 4 and M-stage presettable counters 6 or M-stage presettable counters 7 shown in FIG. The number of stages M is such that, instead of using a plurality of stage presettable counters 5, there is sufficient margin even if multiple counting operations are performed in a time-sharing manner using one counter.
By setting , the number of circuit elements can be significantly reduced.

Based on the above-mentioned principle, the present invention makes it possible to implement programmable frequency division of a plurality of clocks with a smaller number of elements by sharing the second counting means by time division. It is something.

DESCRIPTION OF THE EMBODIMENT FIGS. 6 and 7 show an embodiment of the present invention in which a plurality of programmable frequency dividers are configured based on the above-mentioned principle, and FIG. 8 is a timing chart for explaining its operation. It is.

In FIG. 6, 4 is an M-stage counter, and 6 is an M-stage presettable counter, L of each are provided, and clocks CK ₁ , CK ₂ . . . CK _L are supplied to each of them. 10 is a synchronous circuit, 11 is an AND gate, 12 is a flag, 18 is a multiplexer composed of an AND gate 13 and an OR gate 14;
15 is a latch, 16 is an adder, 17 is a RAM, 19 is a synchronous circuit 10, an AND gate 11,
flag 12, multiplexer 18, latch 15,
This is a time division programmable counter consisting of an adder 16 and a RAM 17.

The operation of the programmable frequency divider of the present invention configured as above will be described next.

The M-stage counter 4 outputs a pulse every time it counts the input clock by ^2M , and the pulse sets the flag 12. The outputs of the L plugs 12 are connected to the inputs of the multiplexer 18, and the outputs of the L plugs 12 are connected to the outputs of the multiplexer 18 in a time-division manner by timing pulses RD1 to RDL as shown in FIG. transmitted to. The transmitted signal is latched by the latch 15 at the WRA signal. Also, one of the L data contents read out by the RAM read signals RD1 to RDL and held in the RAM 17 is latched into the adder 16 by the write signal WRA. The adder 16 adds the signal latched by the latch 15 and the signal read from the RAM 17 and latched in the adder 16, and sends the result to the RDA.
It is output to the bus 20 at the timing of . Output to bus 20. The addition result output to bus 20 is WR
RAM17 and 1 are written by the write signal from 1 to WRL.
It is written to the location corresponding to ~L.

As shown above, time division programmable counter 1
In the operation 9, L inputs are counted in a time-division manner, and the result is held in the RAM 17.

Also, the output of latch 15 is connected to the input of AND gate 11, and when the output of latch 15 is active, it is connected to the RAM represented by WR1 to WRL.
The flag 12 is reset at the timing of writing to the flag 17.

Now, one of the L flags 12 has a frequency division result of L times longer than the period of the timing at which the flag is set (that is, 2 ^M times the shortest period among the L input clocks). If the cycle of accessing the held RAM 17 (that is, the cycle of RD1) is made shorter, the result of counting (dividing) the signals set in L flags 12 will be used when flag 12 is set next. Be sure to use RAM1 until
7 is written. At the same time, the flag 12 is reset, so that the adder 16 and RAM 17 count up only once due to the setting of the flag 12, and therefore no counting error occurs. Furthermore, if the flag 12 is not set (reset), the data in the RAM 17 input to the adder 16 will be written to the RAM 17 as is, and this operation is equivalent to refreshing the RAM. It is.

The count results written to RAM17 are calculated by time division, so CK1~
Although it is not synchronized with CKL, after each count end signal obtained by time-division calculation is output from the RAM 17, the M-stage counter 4
Using the synchronization circuit 10 that operates to detect and output the timing when the ^2M count end pulse is output, the time division programmable counter 19 detects the timing when the output of the synchronization circuit 10 becomes active.
If the count is ended by CK1 to CKL, then a count end signal will be obtained based on the time-division programmer division period 19 synchronized with each input clock represented by CK1 to CKL.

After the M-stage counter 4 and the time-division programmable counter 19 finish counting, the M-stage presettable counter 6 starts counting and performs the counting operation for the set count number. After the M-stage presettable counter 6 finishes counting, the M-stage counter 4 is reset and starts counting, data is set in the M-stage presettable counter 6, and the M-stage counter 4 and the time-sharing programmable counter 19 are set. Counting starts from the end of the counting operation.

Further, the setting of the initial value to the RAM 17 may be performed after the M-stage presettable counter 6 finishes counting and before the flag 12 is set next.The operation of one embodiment will be described below.

After the M-stage presettable counter 6 finishes counting, the first corresponding RD1 to RDL read timing Instead of reading the data in the RAM 17, the initial setting value is read out and the adder 16 is read out through the bus 20.
The initial setting value is latched at , and addition is performed with the signal latched at latch 15, but flag 12 has not been set yet, so the same value is set at RDA.
WR1~ responded through bus 20 at the timing of
The data is written to the RAM 17 by the WRL write pulse, and the initial setting is completed. This action is flag 12
It only needs to be done once before the
Further, this is always performed once until the M-stage counter 4 counts ^2M and the flag 12 is set.

FIG. 7 shows a second embodiment of the present invention, in which M in FIG.
Instead of the M-stage counter 4 and the M-stage presettable counter 6, an M-stage presettable counter 7 is used, and its operation mode is changed to make it similar to the M-stage counter 4 and the M-stage presettable counter 6 in FIG. The demultiplexer 9 performs the operation of M
It operates to distribute the output of the stage presettable counter 7 according to its operation mode,
The operation of the time-division programmable counter 19 is the same as that described with reference to FIG. 6, so a redundant explanation will be omitted.

Effects of the Invention According to the present invention, L presettable counters with N stages are used to count a predetermined number of L types of clocks, but L presettable counters with M stages are used. It can be configured with a divided programmable counter and L demultiplexers, and the number of elements can be significantly reduced. or,
Conventional N-stage presettable counters require a static configuration because the cycle becomes longer in later stages, but the RAM of the time-division programmable counter in the present invention is considered to be constantly refreshed, so a dynamic configuration is required. This is also effective in reducing the number of elements.

Furthermore, it goes without saying that a microcomputer may be applied to the time division programmable counter 19 in the embodiment.

According to the present invention, the larger the predetermined count number and the more types of clocks to be counted, the greater the effect of reducing the number of elements. It's large.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional programmable frequency divider, FIG. 2 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a diagram showing the basic idea of the present invention, and FIG. 5 and 5 are diagrams showing the circuits that are the basis of the present invention, respectively, FIG. 6 is a first embodiment of the present invention, FIG. 7 is a second embodiment of the present invention,
FIG. 8 is a timing chart explaining the operations of FIGS. 6 and 7. 1...N stage presettable counter, 2...N
Input NAND gate, 3...Data setter, 4...
M stage counter, 5... N-M stage presettable counter, 6, 7... M stage presettable counter, 8, 12... Flag, 9... Demultiplexer, 10... Synchronous circuit, 11, 13 ...And gate, 14...Or gate, 15...Ratsuchi, 1
6... Adder, 17... RAM, 18... Multiplexer, 19... Time division programmable counter, 20... Bus.

Claims (1)

[Scope of Claims] 1. A plurality of first counting means each counting a plurality of clock pulse trains, and a plurality of outputs obtained from the first counting means each counted a predetermined number of times by time division. a programmable second counting means for counting the plurality of clock pulse trains a predetermined number of times, a plurality of programmable third counting means for counting the plurality of clock pulse trains a predetermined number of times, and a synchronization circuit that takes timing so that the second counting means is synchronized with the input clock. By performing pre-counting with the first counting means, the second counting means completes counting each input by time sharing the clock cycle input to the second counting means. By making the time longer than the time required for counting, it is possible to use the counting in a time-sharing manner, and after the counting operation by the first counting means and the second counting means, the third counting means operates. A programmable frequency divider that programmably counts each clock pulse train. 2. A control circuit is provided for switching and controlling the operation of the first counting means to a programmable operation of counting clock pulses a predetermined number of times, so that the first counting means is also used as the third counting means, and the first counting means is also used as the third counting means. After the counting operation by the means and the second counting means, the operation of the first counting means is switched to a programmable counting operation and the counting operation is performed, thereby programmably counting each of the plurality of clock pulse trains. A programmable frequency divider according to claim 1. 3. The second counting means includes a readable and writable storage means having a plurality of addresses, an arithmetic means for adding or subtracting a constant value from a value stored in the memory means, and a timing for using the arithmetic means in a time-sharing manner. 2. A programmable frequency divider according to claim 1, further comprising synchronization means for controlling the frequency divider, thereby enabling time division multiplexing of a plurality of counting operations.