JPH0467656B2 - - Google Patents

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of controlling a timer mechanism in an information processing device that logically multiplexes a single hardware timer, and particularly relates to a method for controlling a timer mechanism that logically multiplexes a single hardware timer. This invention relates to a hardware timer control method that can significantly reduce the frequency of control interrupts and improve system throughput.

[Prior Art] Conventionally, as a control method for a timer mechanism that uses a single hardware timer by logically multiplexing it, interrupts are generated at fixed time intervals regardless of the set time of the timer, and an interrupt is generated on a control table. The set time of each software timer registered in is subtracted, and when the value becomes [0], a timeout is detected.

However, the conventional timer control means as described above has the following drawbacks.

That is, since the above-described timer control means is configured to generate an interrupt at fixed time intervals and subtract the set time of the software timer placed on the control table, Therefore, the smaller the unit of set time is, the more the number of interrupts will occur, resulting in a reduction in system throughput.

[Problems to be Solved by the Invention] The present invention significantly reduces the frequency of occurrence of interrupts for timer count control in a timer mechanism that logically multiplexes a single hardware timer. The present invention provides a hardware timer control method that can improve system throughput.

[Means and effects for solving the problems] The present invention provides a register for storing timer setting values;
Prepare timer hardware consisting of a counter that performs time counting in response to a time signal at a fixed timing, and a comparator that generates an interrupt request when the count value of this counter reaches the set value of the register above. When a timer activation request occurs while the counter is executing a counting operation, the remaining count time value obtained by subtracting the current count value of the counter from the setting value stored in the register above and the new setting value due to the above request are combined. If the new set value is smaller than the remaining time value, the set value stored in the register is saved as a timer count wait state, and the count value of the counter is set to the new set value. A control means sets the added value in the register as a new comparison target, and when the new set value is larger than the remaining time value, a value obtained by adding the count value of the counter to the new set value. A control means that saves the count value of the counter as a timer count wait state and uses it as a comparison target without changing the count value of the counter, and when an interrupt request is generated from the comparator, from each timer setting value in the count interrupt wait state. Initialize the above counter by subtracting the count value of the above counter, search for the minimum timer setting value from each timer setting value in the above timer count waiting state, and set the same timer setting value in the above register as a new comparison target. The present invention has means for executing timer control and timer management for each timer activation request, thereby effectively utilizing the above hardware functions and eliminating the need for constant interrupts for timer control. The frequency of interrupt occurrence can be significantly reduced, and system throughput can be improved accordingly.

[Example] An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a hardware configuration for realizing an embodiment of the present invention.

In FIG. 1, numeral 11 is a count register that increases by +1 in response to a time signal T _P from a hardware circuit (not shown), and is hereinafter simply referred to as a counter. Reference numeral 12 denotes a maximum value register that stores a timer setting value (that is, the maximum value that the counter 11 should reach) in accordance with a timer activation request, and is hereinafter simply referred to as a register. Reference numeral 13 denotes a control register for controlling start/stop of the counter 11. 14 compares the count value of the counter 11 and the set value of the register 12, and the count value of the counter 11 is compared with the set value of the register 12.
This is a comparator that generates an interrupt request IRQ when the set value of IRQ is reached.

2 to 7 are for explaining the operation of the above embodiment, respectively, and FIGS. 2 to 5 are for explaining the time relationship between each timer element,
FIG. 6 and FIG. 7 are flowcharts showing the operation processing flow, respectively. Of these, FIGS. 2 and 3 show cases in which a new timer activation request occurs while the counter 11 is executing a counting operation using the set value stored in the register 12 as the final count value. Each time value is shown in Figure 2, where the set value (set time) T ₂ due to a new timer activation request is the remaining time value T _L obtained by subtracting the count value of the main memory 11 from the set value of the register 12. (T _L > T ₂ ) _, and as shown in FIG. ( _{T L <} T ₂ ). Here, in the case of FIG. 2 (that is, when T _L > T ₂ ), the timer setting value of the communication channel 12 is changed, and the third
In the case shown in the figure (ie, T _L ≦T ₂ ), the timer setting value is not changed.

4 and 5 show changes in the setting states of the counter 11 and register 12 when an interrupt occurs and after the interrupt occurs. register 1
(When the interrupt request IRQ is output from the comparator 14 when the set value of 2 is reached), Figure 5 shows the result after the interrupt has occurred, and T ₁ , T ₂ , and T ₃ each indicate the timer set value by the timer start request. It shows.

Also, Fig. 6 shows the processing flow when a new timer activation request is made in the above embodiment, and Fig. 7 shows an interrupt request.
Each figure shows the processing flow when an IRQ occurs.
In the figure, T _C is the timer setting value (stored in counter 11) that is being compared with the current timer count, T _N is the timer setting value due to a new timer activation request, and T _O is the timer setting value that is being compared with the timer count. The timer setting value that is temporarily saved, C is the count value of the counter 11, and R is the setting value of the register 12.

Here, the operation of one embodiment will be explained with reference to the above figures.

In the initial state, the counter 11 stops counting under the control of the control register 13. Therefore, the comparator 14 does not generate an interrupt request IRQ.

At the first timer activation request, the timer setting value is set in the register 12, and the counter 11 starts counting.

Here, if there is no timer activation request while the counter 11 is executing the counting operation, the counter 11
When the count value reaches the set value of the register 12, the comparator 14 generates an interrupt request IRQ.

Further, when a timer activation request is received while the counter 11 is performing a counting operation, the process shown in FIG. 6 is executed.

This process begins with the set value T _C of register 12.
The remaining time value T _L is obtained by subtracting the count value C of the counter 11 from the time value C, and this remaining time value T _L is compared with the timer setting value T _N based on the new timer activation request.

Here, the timer setting value T _N due to the new timer activation request is smaller than the remaining time value T _L (T _N <
T _L ), the timer setting value T _C stored in the register 12 is temporarily saved as a timer count wait state (T _O ← T _C ), and the timer setting value T _N of the counter 11 is changed by a new timer activation request. Add the new timer setting value by adding the count value C to register 1.
Set to 2 (R←T _N +C).

As a result, from now on, timer counting is started using the timer setting value _TN based on a new timer activation request.

The time relationship of each timer element at this time is shown in FIG. Here, the timer setting value T _N based on the new timer activation request is indicated by T ₂ .

In addition, the timer setting value T _N resulting from the above new timer activation request is larger than the remaining time value T _L (T _N >
T _L ), the value obtained by adding the count value C of the counter 11 to the timer setting value T _N due to a new timer activation request is temporarily saved as a timer count wait state (T _O ←T _N +C), and the current timer setting is The timer continues counting for the value T _C.

The time relationship of each timer element at this time is shown in FIG.

Next, the count value of counter 11 is set to register 1.
When the set value of 2 is reached, the comparator 14 requests an interrupt.
When an IRQ is generated, the process shown in FIG. 7 is executed.

In this process, first, the temporarily saved timer setting value T _p is subtracted by the count value C of the counter 11 (T _p ← T _p −C), and then the counter 11 is initialized (cleared). Ru.

Then, each timer setting value (T _p ,
T _p ,...), search for the smallest setting value and use this as the new timer setting value in register 1.
Set to 2.

As a result, a new timer count is started again using the temporarily saved timer setting value.

Counter 1 when the interrupt request IRQ occurs at this time
1 and the states of the register 12 are shown in FIG.
FIG. 5 shows the same state after the occurrence of the interrupt.
Note that the temporarily saved timer setting values (T _p , T _p , . . . ) are shown here as T ₁ , T ₂ , T ₃ .

The above-described processing is repeatedly executed each time an event occurs, and a timer using a single hardware timer logically multiplexed functions.

Since the timer processing is executed as described above, there is no need for interrupts at regular intervals, and the frequency of occurrence of interrupts can be reduced to improve system throughput.

In the above embodiment, the counter 11 is counted up in accordance with the time signal _TP , but for example, when the timer is started, a set value is set in the counter,
A timer operation similar to that of the above embodiment can be realized even with a configuration in which 1 is subtracted and counted according to the time signal T _P.

[Effects of the Invention] As detailed above, according to the hardware timer control method according to the present invention, in a timer mechanism that logically multiplexes a single hardware timer, a register for storing timer setting values is used. In addition, we prepare timer hardware consisting of a counter that performs time counting in response to a time signal at a fixed timing, and a comparator that generates an interrupt request when the count value of this counter reaches the set value of the above register. , when a timer start request occurs while the above counter is performing a counting operation,
Compare the value of the remaining count time obtained by subtracting the current count value of the counter from the set value stored in the register with the new set value according to the above request,
When the above new set value is smaller than the above remaining time value, the set value stored in the above register is saved as a timer count wait state, and the value obtained by adding the count value of the above counter to the above new set value is set. A control means sets the register as a new comparison target, and when the new set value is greater than the remaining time value, the new set value plus the count value of the counter is set as a timer count wait state. A control means that saves the count value of the counter and uses it as a comparison target without changing the count value of the counter, and when an interrupt request is generated from the comparator,
Initialize the above counter by subtracting the count value of the above counter from each timer setting value in the above timer count interrupt wait state, search for the minimum timer setting value from each timer setting value in the above timer count wait state, and By having a means for setting the timer setting value in the above register as a new comparison target and executing timer control and timer management for each timer start request, the above hardware function can be effectively utilized and the timer control can be performed. The frequency of interrupt occurrence can be significantly reduced without requiring constant interrupts, and system throughput can be improved accordingly.

[Brief explanation of the drawing]

The figures are for explaining one embodiment of the present invention. Fig. 1 is a block diagram showing the hardware configuration, and Figs. 2 to 5 are for explaining the time relationships among each timer element. , FIG. 6, and FIG. 7 are flowcharts showing the processing flow, respectively. 11...Counter (count register), 12...
Register (maximum value register), 13...control register, 14...comparator.

Claims (1)

[Scope of Claims] 1. In a timer mechanism that logically multiplexes a single hardware timer and uses the following: This counter has a comparator that generates an interrupt request when the count value of this counter reaches the set value of the above register, and when a timer start request is generated while the above counter is performing counting operation, it is stored in the above register. Find the remaining count time by subtracting the current count value of the above counter from the set value,
The value of the remaining count time is compared with the new setting value according to the above request, and if the new setting value is smaller than the remaining time value, the setting value stored in the above register is set as the timer count waiting state. The value obtained by adding the count value of the counter to the above new set value is set in the above register as a new comparison target, and when the above new set value is larger than the above remaining time value, the new setting is The value obtained by adding the count value of the above counter to the value is saved as a timer count wait state, and the count value of the above counter is used as a comparison target without changing, and when an interrupt request is generated from the above comparator, a timer count interrupt is generated. Initialize the counter by subtracting the count value of the counter from each timer setting value in the waiting state, search for the minimum timer setting value from each timer setting value in the waiting state for timer count, and set the same timer setting value. A method of controlling a hardware timer that is set in the above register as a new comparison target.