JPH0467659B2 - - Google Patents

Description

Detailed Description of the Invention [Summary] In an information processing device equipped with a processing device peripheral circuit such as an external register that can be accessed from the processing device, and a diagnostic interface, when the processing device stops due to a failure, the external register The system is configured so that the error status (abnormal state) of the external circuit stored in the diagnosing device can be directly referenced from the diagnostic device without going through the processing device.

[Industrial Application Field] The present invention relates to an information processing device, and particularly to an information processing device that includes a processing device peripheral circuit and a diagnostic interface that can be accessed from the processing device.

In information processing devices, the processing device (processor) has various registers such as instruction registers and work registers built in. For example, work registers hold logical addresses for main memory access and store dots before and after processing. It is used for temporary storage.

In addition, in case address conversion is required when accessing the main memory, it is also used as a control register for various operations such as address conversion and memory protection, and as a status register to hold error status that occurs at that time. For use as a status register, an external register is usually provided outside the processing device.

Instructions for accessing external registers are also stored in the control memory as microinstructions, and by setting these in the instruction register, it is possible, for example, to write data to the external registers.

In this way, the processing device accesses the main memory, external registers, and other external devices, but if an error in the address is detected, for example, by a parity check, the access is inhibited. At the same time, the error status is recorded in a status register provided in an external register, and this is notified to the processing device by an interrupt (external machine check).

Furthermore, error detection such as parity check of the program counter is carried out inside the processing unit, and in order to hold the abnormal status etc. obtained by these processes, the processing unit also has a built-in status register. The presence or absence of the external machine check is also held.

At this time, if the processing device falls into an inoperable state due to various failures, it is desirable that peripheral circuits of the processing device such as external registers can be referenced by access from the diagnostic device.

[Conventional technology]

FIG. 3 is a configuration diagram of a conventional example, in which the processing device 1,
an external register 2A and a main memory access control unit 2B as peripheral circuits that can be accessed from the processing device 1;
In addition to the diagnostic interface 4' between the diagnostic device 3 and the diagnostic device 3, in particular the diagnostic device 3 and the external register 2
A condition monitoring line 7 is provided between the terminal A and A.

The diagnostic interface 4' includes an instruction register (IR) built into the processing unit 1.
12, a signal for reading the contents of a specified register in the processing device 1 and outputting it to the data bus (scanout), and a signal for detecting the stoppage of the processing device 1. A signal (halt status signal), a signal (halt signal) for stopping the processing device 1 from the outside, etc. are included, and by using these, the status of the processing device 1 can be read and the processing device 1 can be It is possible to rewrite the instruction register 12 to execute only one instruction.

Therefore, if the processing device 1 stops due to some kind of failure, for example, this will be detected by the halt state signal, and the instruction register built into the processing device 1 will be updated using the scan-out function. 12
The contents of the failure can be known by reading the contents of the processor 1, checking the instruction being executed when the processor stopped, and further checking the status register (SR) 11 inside the processing device 1.

The status register 11 on the processing device 1 side indicates whether there is an external machine check as described above, in addition to errors detected internally such as parity errors in the instruction register 12 or the program counter (not shown). It also maintains the status.

Therefore, when it is detected that an external machine check has occurred, the cause of the failure can be known by referring to the status register 21 in the external register 2A.

However, if there is a serious hardware failure such as an abnormality in the address transmission system (address bus) of the processing device 1, even if the processing device 1 is started and the external register 2A is accessed, the obtained contents may not be reliable. There is no gender.

In addition, if there is such a serious problem,
In order to prevent the processing device 1 from running out of control, the processing device 1 is usually placed in a state where it cannot execute instructions unless it is initialized externally.
Although the side status register 11 can be referenced, the external register 2A cannot be referenced.

Therefore, in such a case, the condition monitoring line 7
The configuration is such that the contents of the status register 21 in the external register 2A can be taken into the diagnostic device 3 using the .

[Problem that the invention seeks to solve]

In the conventional example described above, the status monitoring line 7 is required to be able to take in the contents of the status register 21 bit by bit.

However, when the processing device peripheral circuit is made into a high-density integrated circuit, the number of signal lines of the status monitoring line 8 is restricted due to the restriction on the number of terminals, so the processing device 1 may fall into an inoperable state. In some cases, there is a problem in that the contents of the external register 2A cannot be completely checked.

That is, an object of the present invention is to enable the contents of the peripheral circuits of the processing device, such as the external register 2A, to be checked as completely as possible even if the processing device 1 falls into an inoperable state.

[Means for solving problems]

As shown in the principle diagram of FIG. 1, the information processing device according to the present invention includes a processing device 1, a processing device peripheral circuit 2 that can be accessed from the processing device 1, and a processing device 1 and the processing device peripheral circuit 2. In an information processing device equipped with a diagnostic interface 4 provided between a diagnostic device 3, in response to a signal output before the processing device 1 stops and indicating that the processing device 1 is stopped, A first circuit 5 prohibits the processing device 1 from accessing the processing device peripheral circuit 2, and an address line 41 in the diagnostic interface 4 is connected from the diagnostic device 3 to the processing device peripheral circuit according to the signal. A bidirectional second circuit 6 that switches in the direction toward the circuit 2 is provided.

[Effect]

When the processing device 1 is in a stopped state, access to the processing device peripheral circuit 2 from the processing device 1 side is prohibited, and the processing device peripheral circuit 2 is accessed from the diagnostic device 3 side, thereby achieving status monitoring in the conventional example. The diagnostic device 3 monitors the processing device peripheral circuits 2 such as external registers without using wires.

〔Example〕

FIG. 2 shows a circuit diagram of the embodiment.

In the figure, the same symbols as in FIGS. 1 and 2 represent the same objects, OR represents an OR circuit, AND represents an AND circuit, and PC represents a parity checker.

~ are each a main memory access request,
is the access specification of the external register 2A by the processing device 1, and ' is the access specification of the external register 2A by the diagnostic device 3.
A's access designation is the address and read/write selection,' is the write designation from the diagnostic device 3,
is a data bus, is a signal indicating that the processing device 1 is stopped, and when the processing device 1 is in a stopped state, it outputs this halt signal and then stops. The setting instruction indicates an instruction to capture the internal status (state) of the processing device 1 to a data bus, etc., the selection of the captured data, and the address bus parity error.

In addition, the first circuit 5 and the second circuit 6 are each constructed of tri-state elements connected as shown in the figure and controlled by signals. A bidirectional driver 7 is provided.

With the above configuration, during normal operation, the processing device 1 accesses the main memory access control section 2B or the external register 2A by a signal via the first circuit 5.

In this case, the bidirectional second circuit 6 is switched so that the direction of the signal is from the processing device 1 to the diagnostic device 3, so that the diagnostic device 3 receives address information from the processing device 1. However, it is not possible to specify access from the diagnostic device 3 to the external register 2A.

Therefore, the external register 2A will not be accessed by the diagnostic device 3 by mistake during the normal operation of the processing device 1.

Next, in the event of a failure in the processing device 1, the processing device 1 outputs a halt signal before stopping, so this signal indicating that the processing device 1 is stopped causes the first circuit 5 to main memory access control unit 2B or external register 2 by abnormal data through a signal from the processing device 1.
Prohibit access specification to A.

On the other hand, in the second circuit 6, the signal direction is switched from the diagnostic device 3 to the external register 2A, so that the second circuit 6 can access the external register 2A instead of the processing device 1.

Details of access between the processing device 1 and the diagnostic device 3 will be explained below.

(1) To access the main memory device, after issuing a signal, the address and read/write selection are instructed by the signal, and data is sent and received via the data bus.

(2) Access to the external register 2A from the processing device 1 is performed by specifying access using signals, selecting addresses and reading/writing using signals, and transmitting and receiving data via the data bus.

(3) When accessing the external register 2A from the diagnostic device 3, the access is designated by the signal ', and the address and read/write selection are designated by the signal, and data is transmitted and received by the data bus.

(4) Setting of the instruction register 2A from the diagnostic device 3 is instructed by a signal, and the instruction code to be set is sent via the data bus.

(5) For scan-out, an instruction is given through a signal line while the processing device 1 is stopped, and information to be scanned out is selected by the signal. For example, when the signal is "1", the contents of the instruction register 12 are taken in, and when the signal is "0", data selected according to the contents of the instruction register 12 is taken in.

The parity checker (PC) is for ensuring the reliability of access from the diagnostic device 3 to the external register 2A.

By providing the first circuit 5 and the second circuit 6, the processing device 3 can read the contents of the external register 2A even when the processing device 1 is stopped, but if the fault is on the address bus for,
The data read by the diagnostic device 3 cannot be trusted.

When the diagnostic device 3 accesses the external register 2A, it detects a failure by checking the address sent by itself on the address bus.

〔Effect of the invention〕

As described above, in the information processing apparatus of the present invention, even when the processing apparatus is stopped, the peripheral circuits of the processing apparatus such as external registers can be completely referenced through the diagnostic interface.

Further, since there is no need to provide individual status monitoring lines for each bit as in the conventional example, the number of signal lines of the interface can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a circuit diagram of an embodiment, and FIG. 3 is an explanatory diagram of a conventional example. In the figure, 1 is a processing device, 2 is a processing device peripheral circuit,
2B is a main memory access control circuit, 2A is an external register, 3 is a diagnostic device, 4 is a diagnostic interface, 5 is a first circuit, and 6 is a second circuit.

Claims (1)

[Claims] 1. A processing device 1, a processing device peripheral circuit 2 that can be accessed from the processing device 1, and a diagnostic interface provided between the processing device 1, the processing device peripheral circuit 2, and a diagnostic device 3. ace 4
In the information processing device, the processing device 1 accesses the processing device peripheral circuit 2 in response to a signal that is output before the processing device 1 stops and indicates that the processing device 1 is stopped. a first circuit 5 for inhibiting the processing, and a bidirectional second circuit for switching the address line 41 in the diagnostic interface 4 from the diagnostic device 3 to the processing device peripheral circuit 2 in response to the signal. 6. An information processing device characterized by comprising: 6.