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JPH0468778B2 - - Google Patents
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JPH0468778B2 - - Google Patents

Info

Publication number
JPH0468778B2
JPH0468778B2 JP62179084A JP17908487A JPH0468778B2 JP H0468778 B2 JPH0468778 B2 JP H0468778B2 JP 62179084 A JP62179084 A JP 62179084A JP 17908487 A JP17908487 A JP 17908487A JP H0468778 B2 JPH0468778 B2 JP H0468778B2
Authority
JP
Japan
Prior art keywords
chip
fpc
base plate
solder
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62179084A
Other languages
Japanese (ja)
Other versions
JPS6423543A (en
Inventor
Katsumichi Ueyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP62179084A priority Critical patent/JPS6423543A/en
Publication of JPS6423543A publication Critical patent/JPS6423543A/en
Publication of JPH0468778B2 publication Critical patent/JPH0468778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、レーザによる溶着方法に関し、詳し
くは、フレキシブルプリント基板上にICチツプ
を実装する場合のレーザを用いてはんだ付けする
溶着方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a laser welding method, and more particularly to a laser welding method for mounting an IC chip on a flexible printed circuit board.

〔従来の技術〕[Conventional technology]

従来、この種の作業には一般に高度の技術が要
求されるところであり、ポリイミドフイルム等に
よるフレキシブルプリント基板(FPC)上にIC
基板を高密度でかつ高精度で接続するには十分な
信頼性の得られることが必要である。また、IC
チツプ上の電極数の増加にともない省力化、均質
化を図る必要があり、自動化が可能な接続方法が
開発されなければならない。
In the past, this type of work generally required advanced technology, and ICs were mounted on flexible printed circuit boards (FPC) made of polyimide film, etc.
In order to connect substrates with high density and high precision, it is necessary to obtain sufficient reliability. Also, IC
As the number of electrodes on a chip increases, it is necessary to save labor and achieve uniformity, and a connection method that can be automated must be developed.

すなわち、以上のことを更に具体的に述べる
と、接続部に電気的、機械的な高信頼性の保たれ
ることが肝要であり、軽い荷重が加わつてもすぐ
に接続不良となるようでは困る。また、微細配線
における電極面積をいかに小さくするか、更に電
極間のすき間寸法をいかに短かく保つかに関連し
て接続に必要なスペースを極力微細化する必要が
ある。更にまた、接続方法の簡易化、そして、そ
れにより連続かつ迅速な作業が可能なことが望ま
れるところであり、またそのような自動化によつ
てコストの低減が図られなければならない。
In other words, to put the above in more detail, it is important that the electrical and mechanical reliability of the connection parts is maintained, and it is not desirable for the connection to fail immediately even when a light load is applied. . Furthermore, it is necessary to miniaturize the space required for connection as much as possible in connection with how to reduce the area of the electrodes in the fine wiring and how to keep the gap between the electrodes as short as possible. Furthermore, it is desirable to simplify the connection method and thereby enable continuous and rapid operation, and it is also necessary to reduce costs through such automation.

第4図〜第6図は従来の溶着技術による実施方
法を示す。すなわち、第4図はワイヤボンデイン
グ方式によるもの、第5図はビームリード線方式
によるもの、第6図はリフロー方式によるはんだ
付けの場合をそれぞれ示す。第4図において、1
は補強板2上に載置されたFPC、3はFPC1上
の電極部に設けられたパツドであり、この場合は
まずFPC1上の所定の位置にICチツプ4を接着
した後、ICチツプ4上のパツド、すなわちはん
だ用のバンプ5とFPC1上のパツド3との間を
ボンデイングワイヤ6によつて接続、いわゆるボ
ンデイングするものである。
Figures 4-6 illustrate the method of implementation using conventional welding techniques. That is, FIG. 4 shows soldering by the wire bonding method, FIG. 5 shows the soldering by the beam lead wire method, and FIG. 6 shows the case of soldering by the reflow method. In Figure 4, 1
is the FPC placed on the reinforcing plate 2, and 3 is the pad provided on the electrode part on the FPC 1. In this case, first, the IC chip 4 is glued to a predetermined position on the FPC 1, and then the IC chip 4 is glued on the IC chip 4. The solder bumps 5 and the pads 3 on the FPC 1 are connected by bonding wires 6, so-called bonding.

また、第5図において、7はICチツプ4の電
極部に形成されているビーム状リード線であり、
8はFPC1の導体パターンであつて、本例はIC
チツプ4を微移動させることにより導体パターン
8とビーム状リード線7とを一致させ、しかる後
熱圧着させる方式のものである。
Further, in FIG. 5, 7 is a beam-shaped lead wire formed in the electrode part of the IC chip 4.
8 is the conductor pattern of FPC1, and this example is an IC
In this method, the conductive pattern 8 and the beam-shaped lead wire 7 are aligned by slightly moving the chip 4, and then they are bonded by thermocompression.

更にまた、第6図において、9はICチツプ4
の側に設けられたはんだバンプ、10はFPC1
の導体パターン8上にプリントされたペーストは
んだであつて、この場合はペーストはんだ10上
にICチツプ4のはんだバンプ9を一致させるよ
うにして固定した後、部品全体を高温雰囲気11
内で加熱し、溶融接続するものである。
Furthermore, in FIG. 6, 9 is the IC chip 4.
Solder bump provided on the side of , 10 is FPC1
In this case, after fixing the solder bumps 9 of the IC chip 4 on the paste solder 10 so as to match them, the entire component is placed in a high temperature atmosphere 11.
It is heated inside and melted and connected.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、第4図に示すワイヤボンデイン
グ方式によるものでは、ボンデイングワイヤ6に
よる接続部自体の機械的構造が強度的に弱いため
に、フレキシブルなFPC1の特徴を生かすよう
なところに、このような方法によつて得られたも
のを実装するのは不向きであり、その点で信頼性
に欠ける。
However, in the wire bonding method shown in FIG. 4, the mechanical structure of the bonding wire 6 itself is weak, so this method is not suitable for use in places where the characteristics of the flexible FPC 1 can be utilized. It is unsuitable to implement what has been obtained, and in that respect it lacks reliability.

また、第5図に示す方法ではICチツプ4上に
ビーム状リード線7を精密に配設しなければなら
ず、工程も複雑であると共に手間かかり、経済的
にも不利である上、熱圧着時にFPC1が高温に
さらされるので変形し易い。
Furthermore, in the method shown in FIG. 5, the beam-shaped lead wire 7 must be precisely arranged on the IC chip 4, and the process is complicated and time-consuming, which is economically disadvantageous. Since the FPC 1 is sometimes exposed to high temperatures, it is easily deformed.

更にまた、第6図に示す方法は電子部品全体を
炉などの高温雰囲気内で加熱するため、FPC1
は勿論のこと、その他の電子部品の電気的、機械
的特性が損われることがある。
Furthermore, since the method shown in Figure 6 heats the entire electronic component in a high-temperature atmosphere such as a furnace, FPC1
Of course, the electrical and mechanical properties of other electronic components may be impaired.

そこで、本発明の目的は、上述の問題点に着目
し、その解決を図るべく、局部加熱によりICチ
ツプのはんだバンプとFPC電極との間のはんだ
付けが迅速にかつ容易に実施でき、しかも高い信
頼性が保証されるレーザによる溶着方法を提案す
ることにある。
Therefore, an object of the present invention is to focus on the above-mentioned problems, and to solve the problems, it is possible to quickly and easily perform soldering between the solder bumps of an IC chip and an FPC electrode by local heating, and at a high cost. The purpose of this invention is to propose a laser welding method that guarantees reliability.

〔問題点を解決するための手段〕[Means for solving problems]

かかる目的を達成するために、本発明は、フレ
キシブルプリント基板上にICチツプを実装する
にあたり、はんだバンプを有するICチツプを台
板の位置決め部に収納し、台板上にフレキシブル
基板をその電極がはんだバンプの対向位置にくる
ように位置決めし、台板の位置決め部と対向する
位置にマスク付きガラスを具えた押圧板をフレキ
シブル基板に重ね合せて位置決めした状態で電極
をはんだバンプに圧接させ、マスク付きガラスの
透光窓からレーザ光を照射して、はんだバンプお
よび電極のみを加熱させることにより双方間を溶
着させることを特徴とする。
In order to achieve such an object, the present invention, when mounting an IC chip on a flexible printed circuit board, stores the IC chip having solder bumps in the positioning part of the base plate, and places the flexible circuit board on the base plate with its electrodes. Position the electrode so that it is facing the solder bump, and position the pressing plate with a masked glass at the position facing the positioning part of the base plate overlapping the flexible board, press the electrode against the solder bump, and press the mask. It is characterized by irradiating a laser beam through a light-transmitting window of the attached glass to heat only the solder bump and electrode, thereby welding them together.

〔作 用〕[Effect]

本発明レーザによる溶着方法によれば、台板の
位置決め部にICチツプを位置決めした上にFPC
を重ね合せ、マスク付きガラスを有する押え板に
よつて、双方を圧接させた状態に保ちながら、マ
スク付きガラスの透光窓からレーザ光を溶着部の
みに投射させるので、はんだバンプにレーザ光が
集中的に照射されて良好なはんだ付け状態が得ら
れ、その他の部分はマスクによつてレーザ照射が
さえぎられるので、特に熱容量の低いFPCをそ
の焼損から保護する効果が大きい。
According to the laser welding method of the present invention, an IC chip is positioned at the positioning part of the base plate, and then the FPC is
are placed one on top of the other, and while keeping them in pressure contact with each other using a holding plate with a masked glass, the laser beam is projected only onto the welded area through the transparent window of the masked glass, so that the laser beam does not reach the solder bumps. Since laser irradiation is concentrated and a good soldering condition is obtained, and other parts are blocked from laser irradiation by a mask, it is particularly effective in protecting FPCs with low heat capacity from burning out.

〔実施例〕〔Example〕

以下に、図面に基づいて本発明の実施例を詳細
かつ具体的に説明する。
Embodiments of the present invention will be described in detail and specifically below based on the drawings.

第1A図は本発明を適用するFPCの一例を示
し、第1B図は本発明を実施するための溶着治具
の一例を示す。第1A図に示すようにFPC1上
にははんだメツキされた導体パターン12が配設
されており、またその空白部には位置決め用のピ
ン孔13が穿設されている。更に第1B図におい
て、14は位置決めピン15が立設された台板で
あり、台板14の中央部には後述するようにして
ICチツプを収納保持する凹部16が設けられて
いる。
FIG. 1A shows an example of an FPC to which the present invention is applied, and FIG. 1B shows an example of a welding jig for implementing the present invention. As shown in FIG. 1A, a solder-plated conductor pattern 12 is provided on the FPC 1, and a pin hole 13 for positioning is bored in the blank space. Furthermore, in FIG. 1B, 14 is a base plate on which a positioning pin 15 is erected, and the center part of the base plate 14 is provided with a positioning pin 15 as will be described later.
A recess 16 is provided to accommodate and hold an IC chip.

17は位置決めピン15に合わせたピン孔18
を有する押圧板であり、押圧板17の中央部には
台板14の凹部16と対向する位置に貫通窓19
が穿設されており、この貫通窓19の段付部19
Aにマスク付きガラス20が嵌め込まれている。
マスク付きガラス20のマスクは第1C図、第1
D図に示されているとおり、このマスク付きガラ
ス20の透光窓23によつて後述するレーザ光照
射のときにレーザ光が導体パターン12のみに選
択的かつ集中的に照射されるようにするもので、
マスク22自体によつてレーザ光が吸収されない
ようにマスク22には反射率の高いものを使用す
る。
17 is a pin hole 18 that matches the positioning pin 15
The press plate 17 has a through window 19 in the center thereof at a position facing the recess 16 of the base plate 14.
is bored, and the stepped portion 19 of this through window 19
A masked glass 20 is fitted into A.
The mask of the masked glass 20 is shown in FIG.
As shown in Figure D, the light-transmitting window 23 of the masked glass 20 allows laser light to be selectively and intensively irradiated only on the conductor pattern 12 during laser light irradiation, which will be described later. Something,
The mask 22 is made of a material with high reflectance so that the laser beam is not absorbed by the mask 22 itself.

ついで、第2図を参照し、本発明にかかる溶着
方法をその実施過程と共に説明する。ここで、マ
スク付きガラス20は、そのマスク22がFPC
1側に形成されており、それによりレーザ光がガ
ラス内での屈折と更にマスク22のエツジでの回
折とによつて影響されるのを抑制するようにして
いる。いま、このような治具の台板の凹部16に
まずフリツプチツプ方式のICチツプ4を嵌めこ
み、そのはんだバンプ9が台板上から突設するよ
うに位置決めし、次にこの上にFPC1をそのは
んだメツキされた導体パターン12がそれぞれは
んだバンプ9の対向位置にくるように位置決めす
る。なお、このような位置決めはFPC1のピン
孔13に台板14の位置決めピンを貫通させるこ
とによつて得られる。
Next, referring to FIG. 2, the welding method according to the present invention will be explained together with its implementation process. Here, in the masked glass 20, the mask 22 is an FPC
1 side, thereby suppressing the influence of the laser beam by refraction within the glass and further diffraction at the edge of the mask 22. Now, first fit the flip-chip IC chip 4 into the recess 16 of the base plate of such a jig, position it so that its solder bumps 9 protrude from the base plate, and then place the FPC 1 on top of it. The solder-plated conductor patterns 12 are positioned so as to face the solder bumps 9, respectively. Note that such positioning can be achieved by passing the positioning pins of the base plate 14 through the pin holes 13 of the FPC 1.

ついで、押圧板17が同様にして台板14の位
置決めピン15により位置決めされながらFPC
1上に重ねられ、押圧板17を介して押圧力が加
えられる。なお、この場合の押圧力は押圧板17
自体の自重によつてもよいし、あるいは別途に押
圧板17の外部から加えられる力であつてもよ
い。かくして、はんだバンプ9と導体パターン1
2とを圧接させた状態に保ちながら、貫通窓19
の上方からレーザ光21を下方に向けて照射する
と、マスク付きガラス20の透光窓23を介して
レーザ光21が溶着部に照射されるので溶着部以
外の部分はレーザ光21の影響を受けず、従つて
焼損されるようなことがない。また、溶着部は上
述したように圧接状態に保たれているのでレーザ
21の熱が効率よくはんだバンプ9に伝達さ
れ、良好なはんだ付けを実施することができる。
Next, the pressing plate 17 is similarly positioned by the positioning pins 15 of the base plate 14 while pressing the FPC.
1 and a pressing force is applied via a pressing plate 17. In addition, the pressing force in this case is the pressing force of the pressing plate 17.
This may be due to its own weight, or it may be a force applied separately from the outside of the press plate 17. Thus, solder bump 9 and conductor pattern 1
2, while maintaining the state in which they are in pressure contact with each other, the through window 19
When the laser beam 21 is irradiated downward from above, the welded area is irradiated with the laser beam 21 through the light-transmitting window 23 of the masked glass 20, so parts other than the welded area are affected by the laser beam 21 . Therefore, there is no risk of burnout. Further, since the welded portion is maintained in a press-contact state as described above, the heat of the laser beam 21 is efficiently transmitted to the solder bump 9, and good soldering can be performed.

第3図は、本発明の他の実施例を示す。本例は
台板14上に複数の凹部16を形成し、それぞれ
にICチツプ4をはめこみ、レーザ光21により
連続的にFPC1へのチツプ実装を実現しようと
するものである。従つて貫通窓19およびマスク
付きガラス20もそれだけの領域を広くカバーす
るだけの面積を有していなければならない。な
お、溶着方法の手順については第2図に示したも
のと変わりがない。
FIG. 3 shows another embodiment of the invention. In this example, a plurality of recesses 16 are formed on a base plate 14, IC chips 4 are fitted into each recess, and the chips are successively mounted on the FPC 1 using a laser beam 21 . Therefore, the through window 19 and the masked glass 20 must also have an area large enough to cover such a wide area. Note that the procedure of the welding method is the same as that shown in FIG. 2.

また、第2図および第3図の例ではレーザ光を
上方から照射させるようにしたが、光フアイバー
伝送部の保持構造等の都合によつては、第2図お
よび第3図のような状態に保つたまま天地して下
方から照射させるようにしてもよいことはいうま
でもない。
In addition, in the examples shown in Figs. 2 and 3, the laser beam is irradiated from above, but depending on the holding structure of the optical fiber transmission section, etc., the state shown in Figs. 2 and 3 may be changed. It goes without saying that the light may be irradiated from below while the light is held vertically.

〔発明の効果〕〔Effect of the invention〕

以上説明してきたように、本発明によれば、台
板と押圧板との間にICチツプおよびFPCを互い
に位置決めされた状態に重ね合わせて保持させる
ことによりICチツプ上のはんだバンプとFPC上
のはんだ電極とが圧接状態に保たれるようにな
る。そして、押圧板に設けられたマスク付きガラ
スが圧接状態に保たれた上記はんだバンプとはん
だ電極との上方に位置決めされ、さらにマスク付
きガラスの透光窓を介してその圧接部のみにレー
ザ光を照射する。このときのはんだの溶融により
ICチツプをFPC上に溶着させるので、FPCを熱
による焼損から保護しながら良好なはんだ付けを
実施することができ、しかも台板と押圧板とを治
具とすることによりFPCとICチツプの位置合わ
せを極めて容易に実施することができる。
As explained above, according to the present invention, the IC chip and the FPC are held between the base plate and the pressing plate in a mutually positioned state, so that the solder bumps on the IC chip and the FPC are overlapped. The solder electrode is kept in pressure contact with the solder electrode. Then, a glass mask provided on the press plate is positioned above the solder bump and solder electrode which are kept in pressure contact, and a laser beam is applied only to the pressure contact area through the transparent window of the mask glass. irradiate. Due to the melting of the solder at this time,
Since the IC chip is welded onto the FPC, it is possible to perform good soldering while protecting the FPC from burnout due to heat. Moreover, by using the base plate and the pressing plate as jigs, the position of the FPC and IC chip can be The alignment can be carried out very easily.

【図面の簡単な説明】[Brief explanation of the drawing]

第1A図は本発明実施用のフレキシブルプリン
ト基板(FPC)の構成の一例を示す平面図、第
1B図は本発明を実施するための治具の構成の一
例を示す断面図、第1C図はマスク付きガラスの
平面図、第1D図は同側面図、第2図は第1B図
に示す治具により本発明にかかる溶着方法を実施
する段階の説明図、第3図は本発明の他の実施例
の説明図、第4図ないし第6図は従来技術に係わ
り、第4図はワイヤボンデイング方式、第5図は
ビームリード線方式、第6図はリフロー方式によ
る溶着方法のそれぞれ説明図である。 1…FPC、4…ICチツプ、9…はんだバンプ、
12…導体パターン、13…ピン孔、14…台
板、15…位置決めピン、16…凹部、17…押
圧板、18…ピン孔、19…貫通窓、19A…段
付部、20…マスク付きガラス、21…レーザ
光、22…マスク、23…透光窓。
FIG. 1A is a plan view showing an example of the configuration of a flexible printed circuit board (FPC) for implementing the present invention, FIG. 1B is a sectional view showing an example of the configuration of a jig for implementing the present invention, and FIG. 1C is a plan view showing an example of the configuration of a flexible printed circuit board (FPC) for implementing the present invention. FIG. 1D is a plan view of the glass with a mask, FIG. 1D is a side view of the same, FIG. The explanatory diagrams of the embodiment, FIGS. 4 to 6, relate to the prior art. FIG. 4 is a wire bonding method, FIG. 5 is a beam lead wire method, and FIG. 6 is a reflow welding method. be. 1...FPC, 4...IC chip, 9...solder bump,
12... Conductor pattern, 13... Pin hole, 14... Base plate, 15... Positioning pin, 16... Recess, 17... Press plate, 18... Pin hole, 19... Penetration window, 19A... Stepped part, 20... Glass with mask , 21...Laser light, 22...Mask, 23...Transparent window.

Claims (1)

【特許請求の範囲】 1 フレキシブルプリント基板上にICチツプを
実装するにあたり、 はんだバンプを有する前記ICチツプを台板の
位置決め部に収納し、 前記台板上に前記フレキシブル基板をその電極
が前記はんだバンプの対向位置にくるように位置
決めし、 前記台板の位置決め部と対向する位置にマスク
付きガラスを具えた押圧板を前記フレキシブル基
板に重ね合わせて位置決めした状態で前記電極を
前記はんだバンプに圧接させ、 前記マスク付きガラスの透光窓からレーザ光を
照射して前記はんだバンプおよび前記電極のみを
加熱させることにより双方間を溶着させることを
特徴とするレーザによる溶着方法。
[Claims] 1. When mounting an IC chip on a flexible printed circuit board, the IC chip having solder bumps is stored in a positioning section of a base plate, and the flexible circuit board is mounted on the base plate so that its electrodes are connected to the solder. The electrodes are positioned so as to face the bumps, and the electrodes are pressed against the solder bumps while a pressing plate having a glass with a mask is superposed and positioned on the flexible substrate at a position facing the positioning portion of the base plate. and irradiating a laser beam through a transparent window of the masked glass to heat only the solder bump and the electrode to weld them together.
JP62179084A 1987-07-20 1987-07-20 Soldering by use of laser Granted JPS6423543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62179084A JPS6423543A (en) 1987-07-20 1987-07-20 Soldering by use of laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62179084A JPS6423543A (en) 1987-07-20 1987-07-20 Soldering by use of laser

Publications (2)

Publication Number Publication Date
JPS6423543A JPS6423543A (en) 1989-01-26
JPH0468778B2 true JPH0468778B2 (en) 1992-11-04

Family

ID=16059801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62179084A Granted JPS6423543A (en) 1987-07-20 1987-07-20 Soldering by use of laser

Country Status (1)

Country Link
JP (1) JPS6423543A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02247076A (en) * 1989-03-20 1990-10-02 Fujitsu Ltd Laser beam soldering device
JP2601102B2 (en) * 1992-05-08 1997-04-16 松下電器産業株式会社 Lead bonding method for IC parts
DE102004038401B4 (en) * 2003-10-14 2017-07-06 Conti Temic Microelectronic Gmbh Method for connecting a flexible flat conductor to a printed circuit board
JP2007243005A (en) * 2006-03-10 2007-09-20 Ricoh Microelectronics Co Ltd Electrode bonding method and apparatus
JP6124758B2 (en) * 2013-10-07 2017-05-10 株式会社ミマキエンジニアリング Manufacturing method of pressure buffer
KR102901510B1 (en) * 2019-11-21 2025-12-17 레이저쎌 주식회사 Laser reflow apparatus and method thereof
JP7406911B2 (en) * 2019-12-25 2023-12-28 株式会社ディスコ Laser reflow equipment and laser reflow method

Also Published As

Publication number Publication date
JPS6423543A (en) 1989-01-26

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