JPH0469423B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a bipolar transistor, and more particularly to an improvement of a method of manufacturing a bipolar transistor in which a base contact and an emitter opening are formed in a self-aligned manner.

(b) Prior art and problems On the surface of the active region provided on the surface of the semiconductor substrate,
A bipolar semiconductor device structure has already been proposed in which an emitter opening and a base contact can be formed in a self-aligned manner using a selectively formed polycrystalline silicon layer. FIG. 1 is a sectional view of a main part showing a semiconductor device having the above structure, in which 1 is a semiconductor substrate, for example, a silicon (Si) substrate, 2 is a substrate, 3 is an epitaxial growth layer having one conductivity type, and 3 is an epitaxial growth layer having one conductivity type. 2 has a conductivity type opposite to that of the epitaxially grown layer 3. Reference numeral 4 indicates an inter-element insulation isolation region formed by a selective oxidation method or the like, 5 an element region defined by the inter-element insulation isolation region 4, 6 an active region within the element region 5, and 7 an active region 6. 8 is a high concentration buried diffusion layer of one conductivity type, 9 is a low concentration layer of one conductivity type, 10 is a base region having an opposite conductivity type, 11 is an emitter region having one conductivity type, and 12 is an insulating isolation region defining a conductivity type. A polycrystalline silicon layer containing impurities of opposite conductivity type at a high concentration, 13 a silicon oxide film, and 14 an emitter electrode.

A bipolar transistor with this structure has impurities of opposite conductivity type on the surface of the active region 5 [for example, boron (B) if the epitaxial growth layer 3 is n-type].
A polycrystalline silicon layer 12 containing a high concentration of p-type impurities such as p-type impurities is formed, and this is selectively removed using the oxide film as a mask to form an opening, and then thermal oxidation is performed to form a silicon oxide film 13. Form the sidewall portion and perform base contact compensation diffusion at the same time.
Next, using the remaining polycrystalline silicon layer 12 and oxide film 13 as a mask, after opening the emitter part, an impurity of opposite conductivity type (for example, boron (B) in this example) is applied using an ion implantation method, and then an impurity of one conductivity type is added. [In this example, an n-type impurity such as arsenic (As)] is introduced, and then heat treatment is performed. This forms activated base region 10 of opposite conductivity type and emitter region 11 of one conductivity type. Thereafter, an emitter electrode 14 is formed on the emitter region 11, and a base wiring 15 and a collector electrode 16 are formed in ohmic contact with the polycrystalline silicon layer 12, thereby completing a bipolar transistor as shown.

The bipolar transistor manufactured by the above manufacturing method uses the polycrystalline silicon layer 12 as it is as a base lead electrode, but the positions and dimensions of the emitter region 11 and emitter electrode 14 are also based on the polycrystalline silicon layer 12. Determined by layer 12. That is, the base extraction electrode 12, the emitter electrode 14, and the emitter region 11 are all formed in a self-aligned manner, and therefore are formed with good precision, and the manufacturing process thereof is simplified. Furthermore, since the distance between the base contact and the emitter contact becomes extremely short, the external base resistance Rbext and the collector-base capacitance _CCB can be reduced, improving the electrical characteristics of the device.

However, in the above structure, the polycrystalline silicon layer 1
2 is used as a base extraction electrode, no matter how high the impurity concentration it contains, its resistance value is still large compared to when a metal layer is used, so it is low enough to satisfy the external base resistance. It's hard to say that I was able to do that.

(c) Object of the Invention An object of the invention is to provide a method for manufacturing a bipolar transistor that can further reduce the external base resistance.

(d) Structure of the Invention The present invention is characterized by laminating a predetermined metal layer and a polycrystalline silicon layer thereon on a semiconductor substrate or layer on which a collector layer having one conductivity type is formed, and then laminating the polycrystalline silicon layer thereon. Selectively forming a mask film made of a silicon nitride film in a region on the silicon layer where an emitter is to be formed, and then introducing impurities of opposite conductivity type into the semiconductor substrate or layer surface by ion implantation using at least the mask film as a mask. forming a reverse conductivity type impurity-introduced layer that will become an external base region, oxidizing the exposed portion of the polycrystalline silicon layer to convert it into a first silicon dioxide film, and then removing the mask film, a step of removing the remaining polycrystalline silicon layer and metal layer under the mask film to form an opening that will become an emitter region; forming a second silicon dioxide film on the side surface of the opening; exposing the semiconductor substrate or layer surface; and exposing the first and second semiconductor layers through the opening.
The method of manufacturing a bipolar transistor includes the step of introducing impurities of opposite conductivity type and then one conductivity type using a silicon dioxide film as a mask to form a base region and an emitter region.

(e) Embodiments of the Invention An example of manufacturing an npn transistor as an embodiment of the present invention will be described below with reference to the drawings.

FIGS. 2 to 6 are cross-sectional views showing the state of the active region 6, which is the main part of the above embodiment, in the order of manufacturing steps.

In this embodiment, first, as shown in FIG.
After forming an n ⁺ type buried layer 8 on the surface of the p type substrate 2, an n ^- type layer 9 is formed by epitaxial growth. Next, insulating isolation regions 7 for defining inter-element isolation regions 4 and active regions 6 are formed using a selective oxidation method or the like. The steps up to this point are no different from conventional manufacturing methods, and may proceed according to normal manufacturing steps.

After that, for example, titanium (Ti) is deposited on the entire surface of the silicon substrate 1 to a thickness of several 100 Å by using a sputtering method, and on top of this, titanium nitride (TiN) is deposited to a thickness of approximately 1000 to 3000 Å. The metal layer 21 is formed by laminating the metal layer 21 to a thickness of . Then a reactant gas such as monosilane (SiH ₄ ) is applied thereon.
A low pressure chemical vapor deposition method (low pressure CVD method) is performed using
Form to a thickness of [Å]. Furthermore, a chemical vapor deposition method (CVD method) is applied to the film using an ammonia (NH ₃ )-based reactive gas to form a silicon nitride film (SiN film).
23 is formed to a thickness of approximately 500 to 1000 [Å].

Next, as shown in FIG. 3, the SiN film 23
Selective photoresist film (or SiO ₂ film) on top
24 is formed, and using this as a mask, the exposed portions of the SiN film 24 are selectively removed by reactive ion etching. This process allows it to remain.
The SiN film 23 defines the position and dimensions of the emitter region that will be formed in the active region 6 in a subsequent step, and therefore the photoresist film 24
determines the location of the emitter region.

Next, the photoresist film 24 and the remaining
Using the SiN film 23 as a mask, a p-type impurity such as boron (B) is introduced into the surface of the active region 6 through the polycrystalline silicon layer 22 and the metal layer 21 by ion implantation. In this example, the implantation energy was approximately 100 to 140 [keV], and the dose was approximately 1 to 5.
×10 ¹⁴ [cm ^-2 ]. In this way, p ⁺ type impurity introduced region 25 is formed.

Next, after removing the photoresist film 24 used as the mask, a thermal oxidation method is performed using the SiN film 23 as a mask to oxidize the polycrystalline silicon layer 22. As a result, as shown in FIG. 4, the exposed portion of the polycrystalline silicon layer 22 is oxidized and converted into a silicon dioxide (SiO ₂ ) film 26, and only the portion immediately below the SiN film 23 is covered with the polycrystalline silicon layer 2.
It remains as 2. Thereafter, the SiN film 23 used as the mask is removed to expose the remaining polycrystalline silicon layer 22.

Next, as shown in FIG. 5, only the exposed polycrystalline silicon layer 22 is removed by treatment with a mixed solution of nitric acid (HNO ₃ )-based and hydrofluoric acid (HF)-based chemicals.
The underlying metal layer 21 is exposed and then SiO ₂
Using the membrane 26 as a mask, aqua regia (nitric acid HNO ₃ and hydrochloric acid)
The exposed portion of the metal layer 21 is selectively removed and the surface of the n ^- type layer 9 is exposed. Next, SiO ₂ was deposited by CVD method.
A film 27 is deposited on the surface of the n ^- type layer 9 and the entire surface of the SiO ₂ film 26. Note that before forming the SiO ₂ film 27 in this step, a thermal oxidation method is applied to the exposed n ^- type layer 9 surface to form a thin SiO ₂ film, and then the above-mentioned CVD method is performed. You can also apply it. Although the latter increases the number of steps, the interfacial characteristics between the n ^- type layer 9 and the SiO ₂ film are better than when the SiO ₂ film is directly deposited on the surface of the n ^- type layer 9 by CVD. Become.

Next, as shown in FIG. 6, the SiO ₂ film 27 is selectively removed by anisotropic etching, such as reactive ion etching. The amount of etching is set to such an extent that the thickness of the SiO ₂ film 27 deposited by the above CVD method is removed. Through this step, out of the SiO ₂ film 27,
The portions of the SiO ₂ film 26 and the metal film 21 that adhere to the side walls remain, and the portions that adhere to the surface of the n ^- type 9 are all removed to form the openings 28. 29 in the same figure
remains after the above etching process.
A SiO ₂ film is shown.

The subsequent steps may proceed according to normal manufacturing steps. That is, ion implantation is performed using the SiO ₂ film 29 and the underlying metal film 21 as a mask, and boron (B) as a p-type impurity is first applied to the surface of the n ^- type layer 9 within the opening 28, and then boron (B) is injected as an n-type impurity. Arsenic (As)
will be introduced. Next, heat treatment is performed to obtain the above-mentioned
While activating the p ^- type impurity, that is, boron (B) in the p + -type impurity introduced layer 25, a new n ^- type layer 9 is activated.
The p-type impurity boron (B) and the n-type impurity arsenic (As) introduced into the surface are activated. In this way, a p-type internal base region 30, a p ⁺ -type external base region 31 continuous thereto, and an n ⁺ -type emitter region 32 are formed.

As described above, an npn transistor element was formed according to this example. The subsequent steps are further carried out according to normal manufacturing steps, and emitter, base, and collector electrodes are formed to complete the semiconductor device having the structure shown in FIG. 1. However, in this embodiment, the base lead-out electrode 12 was formed using a polycrystalline silicon layer in FIG. 1, whereas the metal layer 21 was formed in the semiconductor device manufactured according to this embodiment.
The difference is that the points formed by

According to the present embodiment described above, the base extraction electrode and the emitter opening can be formed in a self-aligned manner, without any loss of the advantage that the distance between the emitter and the base can be extremely short.
Moreover, since the base extraction electrode could be made of a metal layer, the resistance of the base extraction electrode was significantly reduced, and as a result, Rbext was significantly reduced. According to this embodiment, impurities are introduced into the external base region 31 at a high concentration, so that the metal layer 21 forms good ohmic contact with the external base region 31.

FIG. 7 and FIG. 8 are diagrams shown to explain the effects of this embodiment, and show a conventional bipolar transistor and a bipolar transistor in which the base extraction electrode and emitter openings are formed in a self-aligned manner, respectively. The structure of In both figures, a is a plan view of the main part, and b is a sectional view of the main part.

In the conventional bipolar transistor shown in FIG. 7, an emitter electrode 33 and a base electrode 34
The distance L between the
[μm], and the insulating film 36 at the periphery of the emitter and base openings (contact windows) 33 and 34 and the emitter and base electrodes 14 and 1
5 also requires approximately 1 [μm] if positioning accuracy and the like are taken into account. Therefore, the distance between the openings 33 and 34 in the emitter and base is approximately 4 [μm].
Of these, the length L ₁ of the inner base region 30 from the end of the emitter opening 33 is approximately 2 [μm], and the length of the outer base region 31 from the end of the base opening 34
L ₂ is approximately 2 [μm]. Further, the width d of the openings 33 and 34 in the emitter and base is 3 [μm].

The area that contributes to the resistance component of the external base is the rectangular area sandwiched between the emitter and the openings 33 and 34 of the base (area 3 surrounded by a dashed line in the figure).
5) resistance. These resistances are such that the sheet resistance of the internal base region 30 is approximately 400 [Ω/□],
If the sheet resistance of the base contact compensation region 31 is approximately 400 [Ω/□], then Rbext=900×2/3+400×2/3≒870 [Ω] On the other hand, the base extraction electrode 21 shown in FIG.
In a bipolar transistor in which the emitter electrode 14 and the emitter opening 33 are formed in a self-aligned manner, the emitter electrode 14
The distance L between the base electrode 15 and the base electrode 15 is set to 2 as in the above example.
[μm], and the overlap and width d of the lower layer insulating film at the ends of both electrodes 14 and 15 are also 1 [μm] and 3 [μm] as in the above example, the end of the emitter opening 33 and the base drawer The distance L ₂ from the end of the electrode 21 is approximately 0.3 [μm] and the length of the base extraction electrode 21, that is, from the end of the base extraction electrode 21 to the base opening 34.
The distance _L3 to the end of is approximately 3.7 [μm]. Therefore, when the external base extraction electrode 21 is manufactured using the conventional manufacturing method, that is, using polycrystalline silicon, its sheet resistance is approximately 100 [Ω/□], so Rbext=400×0.3/3+100×3.7/3≒ It becomes 163 [Ω].

Furthermore, when the base extraction electrode 21 is made of the metal layer of this embodiment, the resistivity of titanium nitride (TiN) is approximately 30 to 100 [μΩ·cm], so the film thickness is approximately 2000 μΩ·cm. ~3000 [Å], the sheet resistance is approximately 1 to 5 [Ω/□]. Therefore, in this embodiment, Rbext=400×0.3/3+1-5≈40+1-5 [Ω], and the resistance of the base extraction electrode 21 has almost no effect on Rbext.

As can be seen from the three numerical examples above, it will be understood that according to this embodiment, Rbext can be significantly reduced.

Note that the present invention is not limited to the above-mentioned embodiment, and can be implemented with various modifications.

For example, to manufacture a pnp type semiconductor device using the present invention, all n-type and p-type in the description of the above embodiment may be reversed.

The metal layer is also made of titanium nitride (TiN).
Various selections can be made without being limited to these.

(f) Effects of the Invention As explained above, according to the present invention, it is possible to significantly reduce Rbex of a bipolar transistor in which the base extraction electrode and the emitter opening are formed in a self-aligned manner.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor device in which a base extraction electrode and an emitter opening are formed in a self-aligned manner, and FIGS. 2 to 6 are schematic diagrams showing an embodiment of the present invention in the order of its manufacturing process. Partial sectional view, Figures 7 and 8
The figure is a sectional view of a main part showing the effect of the above embodiment. In the figure, 1 is a semiconductor substrate consisting of a semiconductor layer having one conductivity type and a semiconductor substrate having an opposite conductivity type, 4 and 7 are insulating isolation regions, 8 is a buried layer having one conductivity type, and 9 is one conductivity type. type low concentration semiconductor layer, 14, 15, 16 are emitters, respectively.
Base and collector electrode, 21 is a metal layer, 22
2 is a polycrystalline silicon layer, 23 is a silicon nitride film, and 2 is a polycrystalline silicon layer.
4 is a photoresist film or a silicon dioxide film;
25 is a reverse conductivity type impurity introduced layer, 26, 27, 29
is a silicon dioxide film, 28 is an emitter opening, 30
and 31 are inner and outer base regions having opposite conductivity types, 32 are emitter regions having one conductivity type, and 3
3 and 34 are emitter and base openings, 35 is a region acting as a base parasitic resistance, and 36 is an insulating film.

Claims (1)

[Claims] 1. A predetermined metal layer and a polycrystalline silicon layer are laminated on a semiconductor substrate or layer on which a collector layer having one conductivity type is formed, and then a region on the polycrystalline silicon layer where an emitter is to be formed is A mask film made of a silicon nitride film is selectively formed, and then, using at least the mask film as a mask, a reverse conductivity type impurity is introduced into the semiconductor substrate or layer surface by an ion implantation method to form a reverse conductivity type impurity that will become an external base region. forming an introduction layer, oxidizing the exposed portion of the polycrystalline silicon layer to convert it into a first silicon dioxide film, and then removing the mask film and removing the remaining polycrystalline silicon layer under the mask film. forming an opening to serve as an emitter region by removing the silicon layer and the metal layer; and forming a second silicon dioxide film on the side surface of the opening to expose the surface of the semiconductor substrate or layer within the opening. manufacturing a bipolar transistor, comprising the step of introducing impurities of opposite conductivity type and then one conductivity type through the opening using the first and second silicon dioxide films as masks to form a base region and an emitter region. Method.