JPH0469834B2 - - Google Patents
Info
- Publication number
- JPH0469834B2 JPH0469834B2 JP11888686A JP11888686A JPH0469834B2 JP H0469834 B2 JPH0469834 B2 JP H0469834B2 JP 11888686 A JP11888686 A JP 11888686A JP 11888686 A JP11888686 A JP 11888686A JP H0469834 B2 JPH0469834 B2 JP H0469834B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- wiring board
- component mounting
- antistatic agent
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0257—Overvoltage protection
- H05K1/0259—Electrostatic discharge [ESD] protection
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、基板ソケツトとの接触不良を起すこ
とがなく、かつ外観良好な電子部品実装配線基板
に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an electronic component mounting wiring board that does not cause poor contact with a board socket and has a good appearance.
（従来の技術）
従来から、第２図ａ，ｂに示すように、端子部
分１と半導体チツプ部品２の実装部分を除く表裏
両面に斜線で示すレジスト３の被覆された配線基
板４に、半導体チツプ部品２等の電子部品を搭載
し、金ワイヤ５により半導体チツプ部品２と配線
パターン６とを電気的に接続して回路を形成した
COB（チツプオンボード）モジユールが汎用され
ている。そしてこのようなCOBモジユールのな
かでも、近年特にメモリーチツプを搭載したもの
の需要が増加している。(Prior Art) Conventionally, as shown in FIGS. 2a and 2b, a semiconductor is coated on a wiring board 4 covered with a resist 3, which is indicated by diagonal lines on both the front and back surfaces, excluding the terminal portion 1 and the mounting portion of the semiconductor chip component 2. An electronic component such as a chip component 2 is mounted, and a circuit is formed by electrically connecting the semiconductor chip component 2 and a wiring pattern 6 with a gold wire 5.
COB (chip on board) modules are commonly used. Among such COB modules, demand has particularly increased in recent years for those equipped with memory chips.
ところでこのようなCOBモジユールでは、基
板が５×1015Ω−cm程度の体積固有抵抗を有する
紙フエノール、紙エポキシ、あるいはガラスエポ
キシなどの材料からなつており、帯電しやすい。
このため、基板に実装された電子部品の静電破壊
を防止する目的で、従来から半導体チツプ部品の
実装側と反対側の配線基板表面の端子部分１に帯
電防止剤を塗布することが行なわれていた。 By the way, in such a COB module, the substrate is made of a material such as paper phenol, paper epoxy, or glass epoxy, which has a volume resistivity of about 5×10 15 Ω-cm, and is easily charged.
For this reason, in order to prevent electrostatic damage to electronic components mounted on a board, an antistatic agent has traditionally been applied to the terminal portion 1 of the wiring board surface on the side opposite to the mounting side of semiconductor chip components. was.
（発明が解決しようとする問題点）
しかしながらこのように配線基板の端子部分に
帯電防止剤を塗布すると、往々にして端子とソケ
ツト間の接触不良を生じるという問題があつた。
またこの端子は外部に露出しているので帯電防止
剤の塗布むらや汚れがあると製品外観を損なうと
いう問題もあつた。(Problems to be Solved by the Invention) However, when an antistatic agent is applied to the terminal portion of a wiring board in this manner, there is a problem in that poor contact between the terminal and the socket often occurs.
Furthermore, since this terminal is exposed to the outside, there is a problem in that uneven application of the antistatic agent or dirt can impair the appearance of the product.
本発明はこのような問題を解決するためなされ
たもので、ソケツトとの接触不良がなく、製品外
観を損なうおそれのない電子部品実装配線基板を
提供することを目的とする。 The present invention has been made to solve these problems, and an object of the present invention is to provide an electronic component mounting wiring board that is free from poor contact with a socket and is free from the risk of damaging the appearance of the product.
［発明の構成］
（問題点を解決するための手段と作用）
本発明は、端子部分と電子部品実装部分を除く
全面にレジストの被覆された電子部品実装配線基
板において、電子部品搭載側の配線パターンとそ
の裏面の端子とを接続するスルーホールの電子部
品搭載側のランド部にレジストを被覆することな
く帯電防止剤を塗布して成ることを特徴としてい
る。[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides an electronic component mounting wiring board in which the entire surface of the electronic component mounting wiring board except the terminal portion and the electronic component mounting portion is coated with a resist. It is characterized in that an antistatic agent is applied to the land portion of the electronic component mounting side of the through hole that connects the pattern and the terminal on the back side without coating it with resist.
上記の帯電防止剤としては、市販の各種のもの
が使用可能である。そのような市販の帯電防止剤
としては、たとえばコルコート515（商品名。コル
コート株式会社製）などがあり、これを塗布する
ことにより、107〜108Ωの表面抵抗値が得られ
る。 Various commercially available antistatic agents can be used as the antistatic agent. Examples of such commercially available antistatic agents include Colcoat 515 (trade name, manufactured by Colcoat Co., Ltd.), and by applying this, a surface resistance value of 10 7 to 10 8 Ω can be obtained.
このように本発明においては、帯電防止剤を端
子部分に塗布せずに、電子部品実装側のスルーホ
ールランド部分にレジストをかけないで、この部
分に帯電防止剤を塗布したので、配線基板上の電
子部品静電破壊が防止され、かつ端子部分の接触
不良および製品外観が防止される。 In this way, in the present invention, the antistatic agent is not applied to the terminal portion, and the through-hole land portion on the electronic component mounting side is not coated with resist, but the antistatic agent is applied to this portion. Electrostatic damage to electronic components is prevented, as well as poor contact at terminals and poor product appearance.
（実施例） 次に本発明の実施例を図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
本発明においては第１図ａ，ｂに示すように、
配線基板４の両面に斜線で示すレジスト４が被覆
されている。そしてこのレジスト４は、配線基板
４の製品表面側の端子部分１と半導体チツプ部品
２の実装部分、および配線基板の製品表面側の端
子と半導体チツプ部品実装側の配線パターン６と
を接続するスルーホール７の半導体チツプ部品実
装側のランド部分８（ランドとその周辺部）が除
去されており、ランド部分８には帯電防止剤が塗
布されている。 In the present invention, as shown in FIGS. 1a and b,
Both surfaces of the wiring board 4 are coated with a resist 4 shown by diagonal lines. This resist 4 is a through-hole that connects the terminal portion 1 on the product surface side of the wiring board 4 and the mounting portion of the semiconductor chip component 2, and the terminal on the product surface side of the wiring board and the wiring pattern 6 on the semiconductor chip component mounting side. A land portion 8 (the land and its surrounding area) on the semiconductor chip component mounting side of the hole 7 has been removed, and an antistatic agent has been applied to the land portion 8.
なお配線基板４上の実装部分には半導体チツプ
部品２が搭載され、金ワイヤ５により半導体チツ
プ部品２と配線パターン６とが電気的に接続され
ている。 Note that the semiconductor chip component 2 is mounted on the mounting portion on the wiring board 4, and the semiconductor chip component 2 and the wiring pattern 6 are electrically connected by the gold wire 5.
このように構成された実施例の配線基板では、
ランド部分８には帯電防止剤が塗布されているの
で電子部品の静電破壊が防止され、かつ製品表面
側の端子部分に帯電防止剤が塗布されないので端
子の接触抵抗が低下するようなことがなく、製品
外観も良好である。 In the wiring board of the embodiment configured in this way,
Since the land portion 8 is coated with an antistatic agent, electrostatic damage to electronic components is prevented, and since no antistatic agent is coated on the terminal portion on the surface side of the product, the contact resistance of the terminal is prevented from decreasing. The appearance of the product is also good.
［発明の効果］
以上説明したように本発明の電子部品実装配線
基板は、端子部分に帯電防止剤を塗布しないので
端子部分の接触不良がなく、また帯電防止剤の塗
布むらによる製品外観を損なうことなく電子部品
の静電破壊を防止することができる。[Effects of the Invention] As explained above, the electronic component mounting wiring board of the present invention does not apply an antistatic agent to the terminal portion, so there is no contact failure at the terminal portion, and the product appearance is not damaged due to uneven application of the antistatic agent. Electrostatic damage to electronic components can be prevented without causing damage.
第１図ａ，ｂは本発明の電子部品実装配線基板
を説明するための図で、同図ａは配線基板の電子
部品実装側を示す平面図、同図ｂは配線基板の製
品表面側を示す平面図、第２図ａ，ｂは従来方法
を説明するための図で、同図ａは配線基板の電子
部品実装側を示す平面図、同図ｂは配線基板の製
品表面側を示す平面図である。
１…端子部分、２…半導体チツプ部品、３…レ
ジスト、４…配線基板、５…金ワイヤ、６…配線
パターン、７…スルーホール、８…ランド部分。
Figures 1a and 1b are diagrams for explaining the electronic component-mounted wiring board of the present invention. Figure 1a is a plan view showing the electronic component mounting side of the wiring board, and Figure 1b is a plan view showing the product surface side of the wiring board. Figures 2a and 2b are diagrams for explaining the conventional method, where figure a is a plane view showing the electronic component mounting side of the wiring board, and Figure 2b is a plane view showing the product surface side of the wiring board. It is a diagram. DESCRIPTION OF SYMBOLS 1...Terminal part, 2...Semiconductor chip component, 3...Resist, 4...Wiring board, 5...Gold wire, 6...Wiring pattern, 7...Through hole, 8...Land part.
Claims (1)
ジストの被覆された電子部品実装配線基板におい
て、電子部品搭載側の配線パターンとその裏面の
端子とを接続するスルーホールの電子部品搭載側
のランド部にレジストを被覆することなく帯電防
止剤を塗布して成ることを特徴とする電子部品実
装配線基板。1. In an electronic component mounting wiring board whose entire surface is coated with resist except for the terminal area and the electronic component mounting area, the land portion of the electronic component mounting side of the through hole that connects the wiring pattern on the electronic component mounting side and the terminal on the back side thereof. An electronic component mounting wiring board characterized in that the electronic component mounting wiring board is formed by applying an antistatic agent to the substrate without coating it with a resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61118886A JPS62274793A (en) | 1986-05-23 | 1986-05-23 | Electronic parts mounting wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61118886A JPS62274793A (en) | 1986-05-23 | 1986-05-23 | Electronic parts mounting wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62274793A JPS62274793A (en) | 1987-11-28 |
| JPH0469834B2 true JPH0469834B2 (en) | 1992-11-09 |
Family
ID=14747575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61118886A Granted JPS62274793A (en) | 1986-05-23 | 1986-05-23 | Electronic parts mounting wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62274793A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014024428A (en) * | 2012-07-26 | 2014-02-06 | Mitsubishi Cable Ind Ltd | Alarm display lamp |
-
1986
- 1986-05-23 JP JP61118886A patent/JPS62274793A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014024428A (en) * | 2012-07-26 | 2014-02-06 | Mitsubishi Cable Ind Ltd | Alarm display lamp |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62274793A (en) | 1987-11-28 |
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