JPH046992B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a program-controlled digital computer,
In particular, the present invention relates to a digital computer (hereinafter referred to as a vector processor) suitable for executing vector operations at high speed. [Prior Art] Vector processors have been devised for high-speed processing such as large matrix calculations that frequently appear in scientific and technical calculations. In particular, a vector processor with vector registers and a chaining function has been proposed in order to effectively utilize the high speed of multiple pipeline arithmetic units and improve the transfer ability of arithmetic data (U.S. Pat. No. 4,128,880). . A: Conventional devices have the following problems with chaining. This will be explained using a simple example of vector calculation. FORTRAN statement DO 10 I=1,L 1OY(I)=A(I)+B(I)*C(I) Expressing this process in the form of a vector instruction is 1 Vector Load VR ₀ ←A 2 Vector Load VR ₁ ←B 3 Vector Load VR ₂ ←C 4 Vector Multiply VR ₃ ←VR ₁ *VR ₂ 4 Vector Add VR ₄ ←VR ₀ +VR ₃ 4 Vector Store VR ₄ ←Y Here, VRi represents the i-th vector register. Each vector instruction repeatedly executes calculations and data transfers for L elements. In the above example, the multiplication result of vectors B and C, which is an intermediate result before obtaining the final result, is stored in the vector register.
It is temporarily stored in VR3, and only the addition result Y of this and vector A is kept in main memory. Generally, in a vector processor equipped with a vector register, a vector of intermediate results of an operation is temporarily stored in the vector VR1, and only the final result vector is stored in the main memory. This substantially reduces the number of data transfers to and from the main memory.
Therefore, by speeding up the write and read operations of the vector register, it is possible to ensure sufficient data transfer capacity necessary for calculations even if the access capacity of the main memory device is relatively low compared to this. By the way, if we focus on the fourth and fifth vector instructions in the above example, the vector register VR3 that stores the multiplication result of the preceding instruction 4 also becomes the vector register that should read the operant of the subsequent vector addition instruction 5. ing. If the fourth vector multiplication instruction causes all L results to be stored in vector registers,
If you wait until it is written to VR3 and then start the subsequent vector addition instruction 5, you will not be operating multiple arithmetic units (for example, multipliers and adders) in parallel, and the processing time will be reduced. Extends. In this way, the waiting state that occurs because subsequent vector instructions continue to use the vector register that stores the operation result or fetch vector data of the preceding vector instruction as an operand is the same as in vector instructions 2, 3, and 4 in the above example. It also exists between 1 and 5, and between 5 and 6. The chaining function reduces this waiting time. In the prior art, as a chaining operation, the arithmetic result obtained by the preceding vector instruction is written into the vector register VR ₁ , for example, and at the same time, it is immediately transferred to the arithmetic unit as the operand of the subsequent vector instruction. If chaining is possible, the operation result of the first element of the preceding vector instruction can be outputted and the subsequent vector instruction can be started without waiting until the completion of the operation of the last element of the preceding vector instruction. Thereby, even in polynomial vector calculations, a plurality of arithmetic units can be operated in parallel to increase the parallelism of calculations and perform high-speed processing. However, in chaining in the prior art, the vector register for the subsequent vector instruction is completely synchronized with the time when the first element of the operation result vector or fetch vector data of the preceding vector instruction is written to a certain vector register. had started reading. Therefore, when an instruction is activated, it is determined whether the vector register from which the operand of the instruction is to be read is used for writing by the preceding instruction, and if this determination is positive, it is determined whether or not the above-mentioned chaining is possible. If chaining is possible, that instruction is activated, but if not, activation of that instruction is delayed until the writing of all elements by the preceding instruction is completed and the vector register is released. Activation of a chainable instruction occurs when the result of the preceding vector instruction or the first element of fetch data arrives at its vector register. This is sometimes called chain slot time. Therefore, it is determined that chaining is possible only when it is predicted that writing of the preceding instruction can be completely synchronized with reading of the subsequent instruction for all elements at this chain slot time. In such conventional vector processors, each element of vector data is successively read from a vector register in response to successive clock signals, and each element of the corresponding resultant vector data is also read out from a vector register in response to successive clock signals. and written to the vector register. However, as a vector processor, each element of vector data is intermittently read from the vector register.
It has been found that there are cases in which it is desirable to read out data even at irregular intervals. For example, if each element of the execution result vector data of a preceding instruction is not obtained every clock for some reason but is obtained discontinuously, each element of the resulting vector data arrives at the vector register intermittently. When performing a vector operation for a subsequent instruction on this vector data, all elements of the resultant vector data of the preceding instruction are written to the vector register.
Adopting a method of reading from what has already been written is effective in accelerating the start of execution of subsequent instructions. In such a case, reading of vector elements for the subsequent instruction will be performed intermittently. Furthermore, apart from the above-mentioned circumstances, depending on the type of operation or its structure, the arithmetic unit may not be able to receive clock vector elements every time. Even in such a case, vector elements must be read out from the vector register to the arithmetic unit intermittently. However, conventional vector processors cannot read vector elements intermittently from vector registers. In particular, how to operate the arithmetic unit for vector elements that are read out intermittently, or how to store only the effective output in the vector register since the valid output of the arithmetic unit inevitably changes only intermittently. There is a problem to be solved: whether to write to [Object of the Invention] An object of the present invention is to read operand vector elements from a vector register at irregular intervals, supply them to an arithmetic unit, and, as a result, read out operand vector elements from the arithmetic unit at irregular intervals to the vector register. An object of the present invention is to provide a writable data processing device. [Summary of the Invention] Therefore, the present invention provides a means for reading operand vector elements from a first vector register in response to each of a plurality of signals that can be input at unequal intervals, and a means for reading operand vector elements from a first vector register, and a means for reading operand vector elements from a first vector register in response to each of a plurality of signals that can be input at unequal intervals. means for writing a result vector element outputted from the arithmetic means into a second vector register in synchronization with the timing of the output, with respect to a certain read vector element while the arithmetic means is in operation; Established. As a result, it is possible to perform readout at irregular intervals and write results in synchronization with the readout at unequal intervals while the arithmetic unit remains in operation. [Examples of the Invention] The present invention will be described in detail below with reference to Examples. Schematic device configuration In FIG. 1, a main memory control unit U1, an instruction reading unit U2, a memory requester U1
0, memory request from U11 (reading or storing vector data and reading vector instructions)
Performs a predetermined operation depending on the situation. The instruction read unit U2 sends an instruction read request to the main memory control unit U1 via the signal line 1.
The command address is sent via signal line 2. In response, the main memory control unit U1 reads a plurality of instructions specified by the instruction address, and returns the read instructions on signal line 4 with a signal indicating that the instruction is valid. The instruction reading unit U2 puts the read instructions into an instruction buffer (not shown) and sends these instructions one by one to the instruction control unit U3. A signal is placed. The instruction reading unit U2 reads out instructions one after another and sends them to the instruction control unit U3, unless the instruction control unit U3 requests to stop sending the instructions via the signal line 7. The instruction control unit U3 decodes the instruction and, depending on the instruction, sends the memory requesters U10, U11,
Vector register unit U4, arithmetic unit U20,
Sends a start signal etc. to U21. Outline of operation (2) Instruction execution start When the instruction control unit U3 starts instruction execution, it sets the necessary data on the signal lines 11 to 14, sets it on the start signal line 10, and sends the data to the memory requesters U10 and U11 and the vector register unit. U4 or arithmetic unit U20, U21
and activates the vector register unit U4. Here, the conditions for starting the instruction are that the necessary memory requester U10 or U11 or the arithmetic unit U20 or U212 is not currently in use, and the vector register in the vector register unit U4 is
This means that the registers necessary for the instruction in VR are ready for use. Here, whether or not a certain vector register can be used differs from whether or not that vector register is currently in use, as will be described later. Even if it is not in use,
Some vector registers cannot be used, and others can be used even though they are in use. Instructions for which activation conditions are not met are registered in a sequence of instructions waiting to be activated, and subsequently, when an instruction that satisfies the activation conditions is decoded, this decoded instruction is activated first. The signal line 11 sends out an instruction code specifying the type of operation of the instruction to be executed, such as addition, multiplication, vector read, vector write, etc. Signal line 12 specifies register F used by the instruction. Here, each instruction can specify up to three registers. In this embodiment, the vector register unit U4 has eight vector registers.
VR ₀ to VR ₇ are provided, and the same number of vector address registers U5 and vector address increment registers U are provided.
6 are connected to memory requesters 0 and 1. Numbers 0 to 7, 8 to 15, and 16 to 23 are assigned in advance to these vector registers, vector address registers, and vector address increment registers, respectively. The signal line 13 specifies the number of the memory requester or arithmetic unit to be activated. Here, there are three signal lines 13: one specifies the memory requester, one specifies the arithmetic unit, and the other specifies the number of either the memory requester or the arithmetic unit used by the instruction. do. Since the number of memory requesters or arithmetic units is two each, only one line is required to specify these numbers. Color signal 14 specifies the number of vector elements to be processed. Memory requesters U10 and U11, vector register unit U4, and arithmetic units U20 and U21 perform the following operations in response to the activation signal on line 10. () Reading vector data from main memory When the execution of an instruction for this purpose is specified by the instruction code on line 11, the memory requester U10, for example,
According to the third register number, one of each of vector address register U5 and vector address increment register U6 is selected to set the vector address and its increment therein. Memory requester U10 sends a read command, a vector address, and an address valid signal to main memory control unit U1 via signal lines 20, 21, and 23, respectively. The main memory control unit U1 reads the vector element data specified by this vector address from the main memory (not shown here), and transmits the data FD and a data valid signal via signal lines 24 and 25, respectively. Return to memory requester U10. Memory requester U10
sends this data and a data valid signal to the vector register unit U4 on signal lines 29 and 30, respectively. In the vector register unit U4, the first
The vector element data input from line 29 is stored in the vector register with register number . Memory requester U10 updates the vector address based on the set vector address increment value, and similarly reads the next vector element data based on the updated address. This operation is performed on signal line 1
It is repeated for the number of vector elements specified in 4.
Memory requester U10 sends a final vector data signal on line 32 when sending the final vector element address to main memory control unit U1. Main memory control unit U1 sends this signal on line 33 when outputting the final vector element. Memory requester U10 places the final vector data signal on signal line 26 simultaneously with sending out the data valid signal of the final vector element. This signal is sent to the instruction control unit U3 to inform it that this memory requester U10 is vacant, and is also sent to the vector register unit U4, where it is also used to control the end of vector register writing. To finish writing the vector register,
Via signal line 15, it is also known from the vector register unit U4 to the command control unit U3. () Storing vector data in main memory When an instruction to store vector data in main memory is executed, the vector address and its increment are set in the memory requester U10 as in (). In case of storage, vector register unit U
At step 4, vector data is read out one after another from the vector register with the number indicated by the signal line 12 and placed on the signal line 27, and a data valid signal is placed on the line 28 and sent to, for example, the memory requester U10. It will be done. The memory requester U10 further attaches a vector address to these, and sends a write command, vector address, vector element data, and data valid signal to the main memory control unit U1 on signal lines 20, 21, 22, and 23, respectively. When the vector data element to be sent is the final element, line 3
2, the final vector data signal is sent out. The main memory control unit U1 further controls storage in the main memory. When the required number of vector elements has been sent out from the vector register unit U4, the final vector data signal is sent to the memory via the signal line 31.
It is sent to the requester U10, and the memory requester U10 puts it on the signal line 26 and notifies the instruction control unit U3, as in the case of (). () Vector operation When operation U20 or U21 (here referred to as U20) and vector register unit U4 are activated to execute a vector operation instruction,
These work as follows. Note that each arithmetic unit is capable of executing a plurality of types of operations required by various instructions. Vector register unit U4 receives signal 12
In general, the first element data is read from the vector register with the two register numbers specified by
Send to 20. After calculating the two sets of vector element data according to the OP code on the line 11 in the calculating unit U20,
The result and the data valid signal are sent back to the vector register unit U4 on signal lines 45 and 46, respectively. Vector register unit U
4, the result is stored in the vector register of the signal specified by the signal line 12. These processes are sequentially performed on the next element data. When the last vector element is reached, the final vector data signal is sent from the vector register unit U4 to the arithmetic unit U20 via the signal line 40.
Synchronized with the final result from 20, it is again returned to vector register unit U4 via signal line 44. At the same time, this signal is transmitted to the command justice unit U.
3 is also notified, and is notified of the availability of the arithmetic unit and the availability of the vector register. In the above, vector element data is transferred in response to the machine clock, but if a pair of vector element data to be transferred is not available in two vector registers, the vector register unit U4 prohibits transfer until the pair of vector element data is available. do. Therefore, vector elements are read or stored intermittently. Note that the memory requester U11 and the arithmetic unit U2
1 each have a memory requester U10,
It is exactly the same as the arithmetic unit u20, and the signal lines marked with a prime (') in FIG. 1 respond to those without primes. Register Before explaining the detailed operation, the formation of necessary registers will be described below. FIG. 2a shows the structure of an instruction register (register) in which instructions are set. Here, the OP field instruction code is
R1, R2, and R3 fields indicate register numbers.
Of course, the instruction itself has the fields shown in this figure. The registers indicated by the R1 to R3 fields are a vector register, a vector address register, and a vector address increment register, and which register is specified depends on the type of instruction as follows. () Instructions that perform calculations in the arithmetic unit (addition, multiplication instructions, etc.) R1: Vector register number in which the calculation result vector is to be stored R2: Vector in which the vector data to be calculated (addend, multiplicand, etc.) is stored Register number R3: Vector register number in which vector data to be calculated (addend, multiplier, etc.) is stored Here, different vector registers are specified for the R1, R2, and R3 fields. Note that the R3 field may not be used depending on the instruction. (Transfer orders, etc.). () Instruction to read data from main memory R1: Vector register number where data should be stored R2: Vector address register number R3: Vector address increment register number () Instruction to store data in main memory R1: When data is stored R2: Vector address register number R3: Vector address increment register number Figure 2b is used to control arithmetic units U20, U21 and memory requesters U10, U11 (hereinafter sometimes referred to collectively as resources). The registers involved, namely the decode resource register (DS
register), queue resource register (QS register), executable resource register (ES register),
Indicates the format of the register unit resource register (RS register). Here, the S, A, and N fields specify the use of a memory requester, the use of an arithmetic unit, and the number of the memory requester or arithmetic unit, respectively. Note that the DS register and QS register do not have an N field. Figure 2C shows the format of the registers involved in vector register control, namely the decode register register (DG register), queue register register (QS register), memory requester register register (MB register), and register unit register register (RG register). shows. Here Vi
(i = 1 to 3) The field specifies whether there is valid data in the Wi, GNi field. Wi is a field that specifies whether the vector register specified in the next GNi field is used for writing or reading. This field specifies whether the command is to be executed, and becomes "1" or "0" when writing or reading, respectively, and the Ri field of the instruction itself is set in the GNi field. Furthermore, the MG register is
Has only GN2 and GN3 fields. FIG. 2d shows the format of the resource status word register (RSSW register) that controls the status of resources. Here, the S0 and S1 fields indicate whether the memory requesters U10 and U11 are in use, respectively, and the A0 and A1 fields indicate whether the memory requesters U10 and U11 are in use, respectively.
20, indicates whether U21 is in use (set to "1" when in use). FIG. 2e shows the format of the register status word register (RGSW register) that controls the status of vector registers. Here, the W0-W7 fields indicate whether vector registers VR0-VR7 are in use for writing, respectively, and the R0-R7 fields indicate whether vector registers VR0-VR7, respectively, are in use for reading (not in use). (Set as “1” when Details of Command Control Units The details of each unit shown in FIG. 1 will be explained below. Note that the main memory control unit (U in Figure 1)
1) The instruction reading unit (U2 in Fig. 2) is
In response to access requests from two memory requesters U10 and U11, and when access requests are made by these requesters at the same time,
The main memory is accessed by giving priority to one of them, and it is equivalent to what has been achieved conventionally.
I will not explain it here. Also, timing input to the flip-flop register is omitted. It is assumed that inputs of flip-flops and registers to which no control signals are input are always set at predetermined timings. Referring to FIG. 3, the instruction reading unit U2
The vector instruction read out by the vector instruction and the valid signal for the instruction are sent via lines 6 and 5, respectively, the instruction is set in the instruction register (I register) r301, and the instruction valid signal is set in the flip-flop f301. Ru. The instruction valid signal is also used as a set signal to register IR,r301.
Unless a command transmission stop request is sent, commands are sent one after another from the command reading unit U2. This interval is controlled so that the next instruction is input as soon as the instruction in the I register r301 is transferred to the decode instruction register (DI register) r302. The instruction set in the I register r301 is divided into four routes and transferred. The OP field is transferred to DI register r302.
At this time, the output of flip-flop f301 is
It controls the setting of DI register r302 and is also transferred to flip-flop f302 via AND gate g307. Here, the output of the specified exception detection circuit b316 is input to the AND gate g307 in addition to the output of the flip-flop f301, and this circuit b316 is connected to the I register r3.
R ₁ to _{R 3} of vector instructions set to 01
Checks the field and outputs "1" only if there is no register specification exception. As a result, an instruction valid signal is set in flip-flop f302. The instruction in register IR,r301 is also
It is sent to decoder b301, the resource to be used is determined based on its OP field, and the result is stored in the decoder source register (DS register).
Set to r303. DS register r303
has S and A fields as shown in FIG. 2b. However, it is not an N field. decoder b30
1 means this OP field is memory requester U
10 or U11, enter 1 in the S field, and this instruction
Or, if U21 is used, enter 1 in the A field. The output of AND gate g307 is also used to set these data in DS register r303. The command in I register r301 is further sent to decoder b303, where its OP code and the contents of R1, R2, and R3 fields are decoded, and the result is set in decode register register (DG register) r305. As shown in FIG. 2c, the DG register r305 contains a field GNi (I
= 1 to 3), whether the register is used for continuous output,
The decoder b30 has a field Wi (i=1 to 3) indicating whether it is for writing and a field Vi (i=1 to 3) indicating whether these fields are valid or not.
3 decodes the instruction in the I register r301 and outputs the information in these fields. That is, since it is determined in advance by the OP code of the instruction whether or not fields R1 to R3 of the instruction are valid as register specifications, the decoder b303 determines Vi based on the OP code. Also, whether or not the register field Ri determined to be valid is for writing is also available.
It is predetermined by the code.
Decoder b303 looks at the OP code and
can be determined. The decoder b303 inputs the contents of the field Ri to the GNi field.
In this way, the input to the DS register r303 is determined. Also for setting control to DG register r305,
The output of andgade g307 is used. As is clear from the above explanation, the decoding results set in the DS register r303 and DG register r305 are for the same instruction as the instruction code set in the DI register r302, and below, the decoding results set in the DS register r303 and DG register r305 are for the same instruction. Each piece of data may be called an instruction, or they may be collectively called an instruction in the DI register r302. DI register r302; DS register r
303: When the instruction is set in the DG register r305, it is checked whether the next resource can be activated. Instruction queue register (QI register) q301
stores the OP code of the instruction waiting for execution in the DI register r
It consists of three registers QIR0 to QER2 for receiving and storing from 302. Similarly, the queue resource register (QS register) q302 receives resource use requests for the OP codes in these three registers QIR0 to QIR2 from the DS register r303, and stores them in the three registers QSR0.
~2, and the queue register (QG register) q303 is the register QIR0~2.
Vector register usage request for OP code
It consists of three registers QGR0-3 that receive and store data from DG registers R and r305. in the end,
Three instructions waiting to be executed are stored in registers q301 and q302. Hereinafter, for the sake of simplicity, these three queue registers may be collectively referred to as the instruction queue register or instruction queue register q301. As described above in the DI register r302, whether or not a resource can be activated for a newly set instruction is determined based on different criteria depending on whether or not an instruction is already stored in these instruction queue registers. That is, there are the following cases. (a) When there is no instruction in the instruction queue register (a-1) When the instruction in DI register r302 is activated immediately. (a-2) When the instruction in the DI register r302 cannot be activated immediately and the instruction must be placed in the instruction queue register. (b) When the instruction queue register contains an instruction. (b-1) When starting an instruction in the instruction queue register. (b-2) A case where the instruction in the DI register r302 is activated even though there is an instruction in the instruction queue register. The device operation in each case will be described below. (a-1) When there is no instruction in the instruction queue register q301 and the instruction in the DI register r302 is activated. This indicates the resources (operating unit or memory) required by the instruction in the DI register r302.
Requester) and vector registers are both available. In this embodiment, each resource is configured so that it can be used only by one instruction at a certain time.
Therefore, whether a resource is available or not depends on whether the resource is not in use or in use. The resource availability status is determined as follows. Roughly speaking, the requested resource specified by the DS register r303 and the RSSW register r30
A resource use check circuit b305 checks the status of the resources managed in step 4, and outputs to line 310 whether the requested resource is free, and outputs the vacant resource number to line 309. Details will be explained with reference to FIG. S field r30 in DS register r303
The output of 31 is AND gate g320, g321
and these AND gates g320,g
321 each further has an RSSW register r3.
The outputs of S0 field r3041 and S1 field r3042 in 04 are each inverted gate g3.
35, g336. Therefore, the outputs of AND gates g320 and g321 become "1" when the use of memory requesters 0 and 1 is requested, and when memory requesters 0 and 1 are empty, respectively. and gate g32
The output of 0,g321 is input to OR gate g328. Therefore, the output of OR gate g332 is the memory requester 0 or 1 requested for use.
It becomes "1" when is vacant. In addition, the output of AND gates g320 and g321 is output from encoder b3.
20 is also input, and the available memory requester number is output. In other words, and gate g3
When the output of 20 is “1”, AND gate g3
Regardless of the output of the encoder b320, the output of the encoder b320 is "0" (indicating that the memory requester U0 is empty). When the output of the AND gate g320 is "0" and the output of the AND gate g321 is "1", the output of the encoder b320 becomes "1" (indicating that memory requester 1 is empty) (in this embodiment, the memory requester Since there are only two, there is only one encoder output line). and gate g329,
When the outputs of g321 are both 0, any value of the output of encoder b321 may be used. Similarly, regarding the empty state of the arithmetic unit, the DS register r30
3 A field r3032 output and RSSW register r304 A0, A1 field r304
3, from the output of r3044 to the inverting gate g33
7, g338, and gate g322, g32
3. Checked by OR gate g329 and air coder b321, a command requests the use of the arithmetic unit, and if the requested arithmetic unit 0 or 1 is open, the output of the OR gate g329 becomes "1".
The arithmetic unit number is output from the encoder b321. The outputs of the outputs of OR gates g328 and g329 are input to OR gate g332, whose output line 310 indicates that the alternated resource is free. On the other hand, encoders b320, b32
One of the outputs of 1 is selected by the selector S310 and placed on the line 3093, and the OR gate g3
28, g309 output lines 3091, 3092
It is also output as a line 309. Here, the selector S is selected by the output of the OR gate g329.
310, a request to use the arithmetic unit is made, and when the arithmetic unit is vacant, the memory requester number is selected when the arithmetic unit number is other than that. Note that the contents of line 309 are selected by selector S302 and output to line 320. The line 320 consists of a signal line 3201 indicating the availability of the memory requester, a signal line 3202 indicating the availability of the arithmetic unit, and a signal line 3203 indicating the number of the memory requester or the arithmetic unit. It is selectively output in S302. The selector S302 selects the lines 309 and 311 depending on whether the input line 321 is "0" or "1", and in this case, the input line 321 is "0" as will be described later.
In this way, vacant resource numbers among the requested resources are output on line 320. The line 320 is
Also input to decoder b302 and RSSW register r
It is used to set each bit of 304. Here, the decoder b302 consists of a memory requester number decoder b3022 and an arithmetic unit number decoder b3021, each of which has a decoder valid terminal E, and requires a decode input signal only when E is "1". decode. decoder b32
Of the lines 320, the decode valid terminal E of 01 has a line 3202 indicating the vacant space of the arithmetic unit, and the input signal terminal to be decoded has a line 3203 indicating the number.
is connected. Similarly, decoder b3022
Of the lines 320, the decode valid terminal E of
Line 3201 indicating memory requester availability
However, a line 3203 indicating a number is connected as a signal to be decoded. decoder b302
1. The output of B3022 is the four fields r3041 that make up the corresponding RSSW register r304.
~ r3044 (all of which consist of flip-flops) is connected to the set terminal S of line 3.
One of the fields S0, S1, A0, and A1 corresponding to the vacant resource number input from 201 and 3203 is set. In this way, the resource use check is performed by the circuit b305, and the RSSW register r304 is updated according to the check result. Next, returning to FIG. 3, a check regarding the use of vector registers used by instructions in the DI register r302 will be described. The first check is based on the use request vector register number and usage type (read/write) shown in the DG register r305, and the vector register usage status in the RGSW register r306. The first step is to check whether the vector register required by the instruction is currently available. In this case, it is assumed that there is no instruction in the instruction queue register q301. However, generally the instruction queue register q3
A resource free wait instruction is stored in 01,
When the instruction in the DI register r302 is executed by overtaking the instruction already stored in the instruction queue register q301, the register conflict check circuit b3 checks whether there is any inconsistency in the order of vector register use.
It is necessary to check from 09 to b311. This is the second check. In this embodiment, the first and second checks are performed only on the vector register, and the vector address register U
5. Not performed for vector address increment register U6. In this example, for simplicity,
The contents of these registers are not changed, and the configuration is such that two memory requesters can read these registers simultaneously (details will be described later). Therefore, there is no need to check whether these registers can be used. FIG. 6a shows a check circuit b30 using a register.
7, including the DG register r305 and the RGSW register r306. R1 field r3051 in DG register r305,
Based on the output of RGSW register r306, the first
The register usage check b3071 determines that the register can be used only in the case shown in FIG. 6b. In other words, when the register use request is for writing to a vector register (V1=W1=1 GN1<8), when the vector register with number GN1 is unused (Wi=Ri=0, i=GN1), the use request is When reading the vector register (V1=1, W1=0
GN1<8), the vector register with the number GN1 is unused or is being written to (Ri=0,
i=GN1), and outputs "1" to AND gate g343. When the V1 bit is “0”, the vector register can be used, and in this case, AND gate g343 is set to “1”.
Output. Similarly, R2 of DG register r305
Field r3052, R3 field r305
3 is also checked using the same criteria in the second and third used check circuits b3072 and b3073, respectively, and the result is input to the ant gate g343. In this way, when the vector registers designated by the R1, R2, and R3 fields are all usable, a signal "1" indicating that the vector registers are usable is output to the line 313. Note that the register usage check b circuit 307 is
The feature is that even if a vector register required by an instruction in DI register r302 is currently being written to by a preceding instruction, that register is determined to be usable. This is because, as will be described later, in this embodiment, the vector registers are chained so that a read operation can be performed in parallel with the write operation to the vector register in which a vector element is being written. FIG. 7 shows register conflict check circuit b309,
Details of b311 are shown. The register conflict check circuit b309 consists of first to third register conflict check circuits b3091 to b3093, each of which uses the vector register use request instructed by the R1 to R3 fields r3051 to r3053 of the DG register r305 to the QG register q303. Check for conflicts in directed vector register use requests. The outputs of these circuits become "1" when there is no competition. (Details later). AND gate g353 connects these check circuits b3091 to
Both outputs of b3093 output "1" to line 315 via OR gate g359. On the other hand, the output of the inversion gate g356 is also input to the OR gate g359. Therefore, the inversion gate g
Even when the input line 325 to the input line 356 is "0", a signal "1" indicating no conflict is output to the line 315. Register conflict check circuits b310 and b311 also have the same configuration as circuit b309, and include AND gates g354 and g355, inversion gates g357 and g358, and OR gate g36.
0, g361 outputs the conflict check result on lines 316, 317. Lines 323-325 represent the flip-flop f
304 to f306 (FIG. 3).
These flip-flops are connected to registers QIR0 to QIR in instruction queue register q301 (Figure 7).
2, and is set when an instruction exists in these registers (details will be described later). In this case, it is assumed that there is no instruction in the instruction queue register q301, so these flip-flops are not set, and their output line 32
3,324,325 are "0".
Therefore, the outputs on lines 315-317 are all 1's. In this way, instruction queue register q30
If there is an instruction in 1, the conflict check circuit b30
A signal indicating that there is no vector register conflict is generated regardless of the outputs of 9 to b311. The explanation will be given by returning to FIG. 3 again. Output line from register conflict check b309 to b311, 315
317 is set to "1" as described above. Therefore, the output 322 of the AND gate g301 inputting these is 1. In this case, the output line 313 of the register usage check circuit b307 is also set to "1" on the premise that the vector register can be learned to be used.
Therefore, the output of AND gate g302 is also “1”
It is. In addition, resource usage check circuit b30
The output line 310 of No. 5 is also set to "1" on the premise that the resource can be used. Furthermore, output line 3 of flip-flop f302 indicates that there is a valid instruction in DI register r302.
02 is also "1". As will be described later, since the output of the AND gate g305 is "0", the output of the inversion gate g310 is "1". In this state, the output of the AND gate g304 also becomes "1", and therefore the flip-flop, f3, is output via the output line 330 of the OR gate g306.
03 is set. This flip-flop f3
03 is a D type flip-flop that can be set/reset only by timing, and the instruction start signal ST
By line 10, vector register unit U
4. Send to memory requesters U10, UYY, and chainers U20, U21 (see FIG. 1). Also,
Since there is no instruction in the instruction queue register q301, when there is an instruction in the registers QIR0 to QIR2, the outputs of the corresponding flip-flops f307 to f306, which are set to "1", are all "0".
The output of the selector S303 to which the output lines 323 to 325 are input is also the selector S3.
It is set to "0" regardless of the selection operation of 03 (details will be described later). Therefore, the output line 32 of AND gate g305 to which this output line 326 is input
1 also becomes “0”. Selector S301, S30
2, S304 is each DI register r302
The operation code on the output line 303 of the resource use check circuit b305, the resource use request (resource type, number) on the exit line 309 of the resource use check circuit
The vector register use request (register number, usage type) on the output line 307 of register r305 is selected and set in EI register r308, ES register r309, and EG register r312, respectively. The set is indicated by line 330. In addition, the vector length register (VLR) r307 has the following information:
It is assumed that the vector length (VL) to be processed is stored in advance by another means (not shown).
The contents of these registers are sent by lines 11-14 to vector register unit U4 and to each resource U10, U11, U20, U21. This will issue a command to start executing the command. Note that here, since the instruction in the DI register r302 can be started immediately, there is no need to put it in the instruction queue register q301. In this case, since the output of AND gate g303 is "1", the output of inverting gate g308 is "0",
AND gate g303 to which this output is input
The output line 327 of is set to "0". In this way, the DI register r302 to the instruction queue register q301 controlled by this signal line 327
Input of the contents of is suppressed, and new input to registers q302 and q303 is also prohibited. Flip-flops f304 to f indicating that an instruction exists in the instruction queue register q301
306, an inpointer indicating the location in the instruction queue register q301 to be set next.
Suppress updates to aIP, r310, etc. Furthermore, as the instruction is activated, it is necessary to change the FSSW register r304 that manages the state of the resources to be used and the RGSW register r306 that manages the state of the vector register. this house,
Regarding the change of RSSW register r304, please refer to the fifth
RGSW register r30 mentioned in the explanation of the figure
To change the state in step 6, proceed as follows. That is, the selector selected by S304
The output of DG register r305 is sent to decoder b30
4, where the vector register number,
Reads, writes, etc. are decoded and the corresponding RGSW
The bit in register r306 is set to "1". That is, for each field Ri (i=1 to 3) of the DG register r305, Wj (j=GNi) or Rj of the RGSW register R305 is set depending on whether Wi is 1 or not, on the condition that Vi=1. Set it to 1.
Furthermore, as will be described later, when a signal indicating that writing or reading of the vector register is completed is input from the vector register unit U4 via lines 15 and 16, the RGSW register inputs the field Rj or the field specified by this signal. Reset Wj. (a-2) When there is no instruction in the instruction queue register q301, the instruction in the DI register r302 cannot be activated, and the instruction is placed in the instruction queue register q301. This occurs when the instruction in DI register r302 requires a resource (operator or memory requester) or vector register that is not available. To check the usage status of resources and vector registers used by instructions in DI register r302, follow (a-1) according to Figures 5 to 7.
As stated in the explanation. In this case, as a result of checking the usage status of resources and vector registers, the resource requested by the instruction in the DI register r302 is in use, so the output 310 of the resource usage check circuit b305 becomes "0". In addition, if the vector register required by the instruction in the DI register r302 is usable, the output 313 of the register usage check circuit b307
becomes “0”. In both cases, and gate g
The output of 304 is “0”, therefore, the inverting gate g3
The output of 08 becomes "1". Also, since there is no instruction in the instruction queue register, as described in (a-1), the output line 3 of selector S303
Since 26 is “0”, AND gate g305
The output of is "0". Therefore, flip-flop f303 is not set to anything, and the instruction activation signal is not set.
ST is not output on line 10. Reversing gate g3
Since the output of 08 is "1" and the output of flip-flop f302 is also "1", the output line 327 of AND gate g303 becomes "1". As a result, the operation of putting an instruction into the instruction queue register is performed as follows. Details of the instruction queue register q301 are shown in FIG. 4. In FIG. 4, the set signal S to the instruction queue register is on the line 327, and the output IP of the inpointer (IP) register r310 is on the line 328. When the signals are sent via the decoder b330, they are input to the decoding enable terminal E and the data terminal of the decoder b330, and are decoded. As a result, the contents of line 328 are decoded when line 327 is "1";
The contents of input line 303 are set to one of the designated registers r350 to e352. The above is the setting to the instruction queue register q301. Note that the read operation of the instruction queue register, which will be described later, will also be described here. Reading refers to out pointer (OP) register r311 (third
By outputting the contents of the registers r350 to r351 with the numbers specified by the output OP in Figure), this controls the selection control of the selector S350 to which the outputs of each register r350 to r352 are connected.
This can be realized by using the output line 329 of the register r311. In addition, QS register q302 is register r35.
It has the same structure as the instruction queue register q301 except for the difference in the number of bits required by 0 to r352. QG register q303 is register r350
~In addition to the difference in the number of bits required by r352,
Selector S350 from registers r350 to 352
The only difference from the instruction queue register q301 is that a signal line for direct output without going through the instruction queue register q301 is further provided. The explanation will be given by returning to FIG. 3 again. In this way, when the instruction code, the type of resource used by the instruction, and the register number are registered in the instruction queue registers q301 to q303, the currently registered The flip-flop corresponding to the registered register QIRi (i=0, 1or2) is set. This behavior is
The line 327 becomes “1” and this is the decoder b3.
Flip-flops f304 to f3 whose numbers are input to the decoding enable terminal of 12 and specified by the IP above (output line 328) input to the data terminal.
06 is set by the decoder b312. When the above steps are completed, the IP register r310 is updated. Output line 328 of IP register r310 is ternary counter b
314, the next IP value is created, and when the line 327 becomes "1", the IP register r31
The value of the next pointer is set to 0. The ternary counter b314 has inputs of 0, 1, and 2.
It outputs 1, 2, 0. Note that once all instructions have been placed in the instruction queue register (up to three instructions can be queued here), no more instructions can be placed in the instruction queue register (here, up to three instructions can be queued). It is necessary to suppress instruction sending. This is accomplished by inputting the outputs of flip-flops f304-306, which specify the presence of an instruction in the instruction queue register, to AND gate g309, and sending this output line 7 to instruction reading unit U2. As described above, instructions waiting to be activated are stored in the instruction queue register q301 according to their decoding order. (b-1) When starting an instruction in the instruction queue register. This occurs when there is an instruction in instruction queue register q301 and the resources and vector registers it requires are available. This is regardless of whether there is an instruction in the DI register r302 or whether the instruction can be activated. In this case, if there is an instruction in the DI register r302, that instruction will not be executed, so the instruction in the DI register r302 is registered in the instruction queue register q301 according to the procedure described in (a-2).
The following describes the process of taking out and activating an instruction from the instruction queue register q301. The process of fetching and activating an instruction from the instruction queue register q301 is very similar to the process of activating an instruction in the DI register r302. That is,
The instruction specified by the out pointer register r311 in the instruction queue register r301 and the instruction in the DI register r302 may be exchanged. As mentioned in (a-1), in order to activate an instruction, necessary resources and vector registers must be available for use. Checking for free resources used by instructions in the instruction queue register q301 is performed by the resource usage check circuit b306 in FIG. 3, and checking for availability of vector registers is performed by the register usage check circuit b308, also shown in FIG. . The details of the resource usage check circuit b306 are as follows.
This is the same as the check circuit b305 shown in FIG. The type of resource required by the instruction in the instruction queue register q301 selected by the out pointer, OP, is input via line 318 from the QS register q302. On the other hand, the resource status is input from the RSSW register r304. These are AND gates g324 to g32
7 to check resource availability, and as a result, or gates g330 and g33
1, g333, encoder b322, b323,
The result is finally placed on a line 312 indicating that the resource is vacant and a line 311 indicating the type and number of the resource by the selector S311 and the like. The above operation is performed using DS register r303.
Since the operation is exactly the same as that of the resource use check circuit b305 which places the results on lines 310 and 309 by checking with the RSSW register r304, detailed explanation will be omitted. The configuration of the register-using check circuit b308 is the same as that of the check circuit b307, and its operation is as follows.
In FIG. 6a, instead of the output of DG register r305, QG register q30 in FIG.
Circuit b30 when output line 319 of No. 3 is connected
The operation is the same as No.7. The check result is sent to the output line 314 of the register-using check circuit b308.
(Figure 3). The explanation will be given by returning to FIG. 3 again. "1" is output from the resource usage check circuit b306 to the signal line 312 indicating that there is a vacant resource, and the type and number of the resource at this time is output to the line 311, and further, the register usage check circuit b3
08 outputs "1" to the signal line 314 indicating that the vector register can be used, and the output line of the selector S303 selects the outputs of the flip-flops f304 to f306 when the out pointer OP is 0 to 2. When 326 becomes "1" (meaning that there is an activated instruction in the register QIRi in the instruction queue register specified by the out pointer), the AND gate g
The output line 321 of 305 becomes "1". When this output line 321 becomes "1", the selector S30
1, S302, and S304 are the output line 304 of the instruction queue register q301, the output line 311 from the resource usage check circuit b306, and
Select the contents of output line 319 from QG register q303 and write them to EI register r308 and ES, respectively.
The instruction code, resource type and number, register number, and usage pattern are set in register r309 and EG register r312. Therefore, it can be seen that if the instruction in the instruction queue register q301 is activated, the former instruction will be activated regardless of whether the instruction in the DI register r302 is activated or not. Also, the line 321 is the or gate g
A flip-flop f303 is set via line 10, and an instruction activation signal ST is sent to the vector register unit and each resource via line 10.
The output line 330 of the OR gate g306 is also used to control the settings of the EI register r308, the mES register 309, and the EG register r312. The instruction activation is exactly the same as the explanation in (a-1). Further, the "1" signal on line 321 causes inverting gate g310 to close AND gate g301. As a result, the inversion gate g30
8 becomes “1” and DI register r302
If there is an instruction in (flip-flop f3
02 is “1”), set line 327 to “1”
The instruction is controlled to be registered in the instruction queue register. This process is as described in (a-2). Also, line 321 represents decoder b
The decoder b313 is also connected to the decode valid terminal of the out-pointer OP. This is because the instruction in the instruction queue register specified by OP is taken out and activated. Finally, line 321 is used to set OP register r311 and update the out pointer. This update control is performed in ternary format, as in the case of the inpointer. Generation of the ternary value is performed in a circuit b315 having the same configuration as the circuit b314. (b-2) Even though there is an instruction in the instruction queue register, the instruction in DI register r302 is activated first. (1) The resource or vector register required by the instruction in the instruction queue register is available and cannot be used to service this instruction. and (2) the resource or vector register required by the instruction in the DI register r302 is possible, and the vector register is shared between the instruction provided in the instruction queue register q301 and the instruction in the DI register r302. There is no competition. In order to overtake the instruction in the instruction queue register q301 and start the instruction in the DI register r302 first, it is necessary to make sure that there is no register conflict. r3
It is necessary that the instruction in 02 is not used, and that the vector register read by the instruction in the instruction queue register q301 is not changed by the instruction in the DI register r302. There is no problem with reading a vector register that is only used for reading by an instruction in the instruction queue register with an instruction in the DI register because even if the instruction is overtaken, the register reading order is simply reversed. The circuits that perform the register conflict check described above are circuits b309 to b311 in FIG.
The details will be explained based on FIG. 7. The details of the circuit in FIG. 7 are as follows: circuits b3091 to b3
The details of 093 have already been explained. The first register conflict check circuit b3091
RI field r3051 of DG register r305
and the R1 to R3 fields of the QGR0 register g3030, and if any of the following conditions is not met, a signal "1" indicating no register conflict is output to the AND gate g353. (1) When DG register V1=1, W1=0,
In one field Rj of register QGR0, VJ = WJ = 1, GNJ = GN1 of DG register (2) When V1 = 1, W1 = 1 of DG register,
In one field Rj of register QGR0, Vi=1, GNj=GN1 of DG register Similarly, R2 field r305 of DG register
2nd and 3rd register conflict check circuits b309 for R3 field r3053, respectively
2, b3093 performs a similar check. On the other hand, flip-flop f30 indicates that an executable instruction is contained in the instruction queue register.
4 (see FIG. 3) is input to the AND gate g353 via the line 323, and the AND gate g
When all the inputs of 353 are "1", the output is put on line 315 via OR gate g356. In this way, it is checked whether the vector register specified by DG register r305 does not conflict with any vector register specified by register QGR0. Similarly,
A check circuit b310 checks the competitive relationship between the vector register specified by the DG register r305 and the vector register specified by the register QGR1.
The competitive relationship between the vector register specified by DG register r305 and the vector register specified by register QGR2 is checked in check b311, and the results are respectively applied to AND gate g35.
4, via g355, orgate g360, g3
It is placed on the output lines 316 and 317 of 61. The details of checking the resources and register usage status required by the instruction in the DI register r302 are as described in the description of the process (a-1). As a result of the check, in FIG. 3, as the output of the resource use check circuit b305, a signal of "1" indicating that the resource is available is shown on the line 310, and the type and number of the resource is shown on the line 309 as the output of the register use check circuit b307. As a result, a signal of "1" is output on line 313 indicating that the vector register can be used. On the other hand, since either one or both of the resource and vector register used by the instruction specified by the out pointer OP in the instruction queue register is unavailable, the output line 312 of the resource usage check circuit b306 or the resource usage check circuit b
At least one of the output lines 314 of 308 is set to "0". Also, since there is an instruction in the instruction queue register, the selector S303
The output line 326 of DI register r3 is set to “1”.
Since there is an instruction in 02, the line 302 is also set to "1". Even in this situation, and gate g30
The output line 321 of No. 5 does not become "1". In this case, it is assumed that there is no conflict between the registers required by the instruction in the DI register and the instruction in the instruction queue register, so lines 315 to 317 are "1" and the output of AND gate g301 is "1". ”. The output of AND gate g301,
The output of the AND gate g302 to which the line 313 is input becomes “1”, and this output “1” and the line 31
0, a line 302 indicating that the DI register contains a valid instruction, and the output of the AND gate g304, which is inverted by the inverting gate g310 from the line 321, outputs "1". Become. From then on, the process until starting the instruction is (a-
This is exactly the same as the instruction activation process in the DI register in 1). In addition, and gate g304
Since the output of is “1”, the output is inverting gate g
Since the output line 327 of the AND gate g303 to which the result inverted at 308 is input, and the line 321 mentioned above are both "0", neither IP nor OP is updated, and
The states of flip-flops f304 to f306 indicating that an instruction exists in the instruction queue register do not change either. Modified Example of Instruction Control Unit In this embodiment, in which the details of the instruction control unit U3 (see FIG. 1) have been described above, instruction execution is overtaken only between the DI register r302 and the instruction queue register. Once an instruction enters the instruction queue register, it is taken out using an out pointer in the order in which it entered the instruction queue register, so instruction execution is not overtaken between instruction queue registers. However, overtaking execution between instructions in this instruction queue register also
How can I control overtaking execution between instructions in the DI register and instructions in the queue register?
This can be easily achieved. In this case, it is necessary to remember the execution order of the instructions on the instruction queue register. In addition, registering instructions in the instruction queue register is also done using the interpointer (IP).
It is not registered in the order specified by , but is registered in an empty register. FIG. 8 mainly shows the parts of the circuit for realizing this that are different from the circuit shown in FIG. 3. In the figure, flip-flops f304, f
Reference numerals 305 and f306 indicate that a valid instruction is stored in the instruction queue register. After the output is inverted by the inversion gates g380 to g382, it is input to the Brioliday encoder b395, and the output is the number i of the register with the smallest number among the empty instruction queue registers. Instead of the IP register r310 and ternary counter b314 in Figure 3, the inversion gate g380~
g381 and a priority encoder b395 are used, and the output of the priority encoder is used as an inpointer IP instead of the IP in FIG. Also, it is necessary to remember the starting order of the instructions in the instruction queue register q301.
In this modification, flip-flops f380 to f3
82 and an execution order changing circuit b393 are added to the circuit of FIG. to instruction queue register q301
The instructions set for IP = 0 to 2 are named Q0, Q1, and Q2. These instructions are Q0→Q1→Q2 Q0→Q2→Q1 Q1→Q2→Q0 Q1→Q0→Q2 Q2→Q0 →Q1 It is possible that Q2→Q1→Q0 are activated in this order. These six states are stored in flip-flops f380 to f381. Flip flop f380, g381, f3
The relationship between the storage information of 82 and the instruction execution order at this time is shown in the following table.

【table】

[Table] To change the execution order of instructions, use the flip-flop f.
This is performed when 304 to f306 change from "1" to "0" (from being in use to not in use). The change control circuit b393 controls this change. The circuit b393 includes flip-flops f304 to f.
Outputs 323-325 of 306 and flip-flops f380-f382 representing the current activation state
The next activation state is output on lines 376-378 and is again set in flip-flops f380-382. Inside the circuit b393, one instruction in the instruction queue register q301 is activated and the line 323
-325 changes from "1" to "0", output is created from the contents of lines 396-398 as follows, and placed on lines 376-378. That is, the remaining two instructions in the instruction queue register q301 are activated first, and at this time,
The activation order of these two instructions is the order previously specified by flip-flops f380 to f382, and after the activation of these two instructions, the newly stored instruction in the instruction queue register is executed in place of the currently activated instruction. Set flip-flops f380-f382 to activate.

【table】

[Table] Note that lines 323 to 325 are “1” at the same time →
It never becomes “0”. This is because each instruction is activated one by one. In order to enable any instruction in the instruction queue register q301 to be activated, the usage status of resources and vector registers is checked for all instructions in the instruction queue register,
In addition, it is necessary to check for vector register conflicts among all instructions on the instruction queue register.
3022 (QSR0/1/2) holds the type of resource required by the instruction in the instruction queue register q301, and is located in the QS register q302 in FIG. However, in this modification, from each register q3020 to Q3030,
A signal line is provided that directly sends a resource use request regardless of the OP. The resource requests and resource status of each instruction are managed. The contents of the RSSW register r304 are the resource usage check circuits b380 to b382 provided in this modification instead of the resource usage check circuit b306 in FIG.
and a signal indicating whether the resource is free is sent from each line 380 to 382.
The available resource types and numbers are line 38.
3 to 385. Resource use check circuits b380 to b382 have exactly the same configuration as circuit b305 explained in FIG. 5. 8th
In the figure, QGR0 to QGR2 register q303
0 to q3032 store the register numbers required by each instruction in the instruction queue, and are in the QG register q303 in FIG. RGSW register r306 that manages register requests for each instruction and the state of vector registers
The contents of are checked by register usage check circuits b383 to b385 newly provided in this modification, and signals indicating whether or not all requested vector registers are available are checked by register usage check circuits b383 to b385, which are newly provided in this modification.
88. These register use check circuits are exactly the same as the circuit b307 explained in FIG. Further, in order to check conflicts between vector registers required by each instruction, register conflict check circuits b386 to b391 newly provided in this modification are used. We want to allow the execution of each instruction in the instruction queue register in any order. If three instructions can be held in the instruction queue register, two check circuits are required to activate one instruction with priority over the next two instructions, and these check circuits are required for three instructions, so a total of six check circuits are required. Register conflict check circuit b386
~b391 is required. The circuit b386 is
R1 to R3 fields of QGR0 and R1 to R3 of QGR1
fields are input, the former performs a register conflict check on each of the latter, and outputs a "1" on line 390 when no register conflict is detected in any field. It has the same configuration as the register conflict check circuit b309 in FIG.
The output line 324 of the flip-flop f305 is also input to the circuit b386, and the circuit b309
(FIG. 7), this signal line 324 is “0”
When , "1" is outputted to line 390 unconditionally. Similarly, circuit b387 is a circuit that checks whether each field of QGR1 has register conflict with each field of QFR0.
Similarly, circuits b688 to b391 are each QGR2
QGR1 for QGR1, QGR2 for QGR1,
QGR2 for QGR0 QGR2 for QGR2
0, to check for register contention.
These register conflict check circuits b386-b
Output lines 390 to 395 of 391 are input to an instruction selection circuit b394. Instruction selection circuit b394
In this case, the resource usage check circuit b mentioned above is used.
Output lines 386 to 388 of output lines 383 to b385 of 380 to b382, outputs of flipflops f380 to f382 that specify the order of starting instructions, and flipflop f30 that indicates that an executable instruction is contained in the instruction queue register.
The output lines 323 to 325 of 4 to f306 are also input, and the instruction selection circuit b394 selects an instruction in the instruction queue register in which the vector register and resources are free and there is no conflict in use of the vector register. The number in the instruction queue register of the selected instruction is an out pointer.
As OP 329, a signal is output on line 321 indicating that an instruction has been selected in the instruction queue register. Details of the instruction selection circuit b394 are shown in FIG.
The AND gate g383 has a flip-flop f
Output line 323 of 304, output line 386 of resource usage check circuit b383, output line 39 of register conflict check circuits b386 and b391
0,395 are input, and when these inputs are all "1", the output line 370 of AND gate g383 becomes "1". This indicates that the 0th instruction Q0 in the instruction queue register may be executed. Similarly, and gate g384, g385
Signal lines relating to the first and second instruction queue registers are inputted to the signal lines 371 and 372, respectively, and outputted to lines 371 and 372. Lines 370-327 are “1” at the same time
It is possible that it will become. The latter 370 to 372 are input to the OR gate g387, and when any one of the instructions can be executed, the OR gate g387
The output line 321 of is set to "1". Line 370~
The instruction execution order determining circuit b395 determines which one is selected from among the signals outputted to the instruction executable 372. In addition to lines 370 to 372, output lines 396 to 398 of flip-flops f380 to f382, which indicate the instruction execution order, are input to circuit b395.
29. The line 329 actually consists of two lines 3290 (upper) and 3291 (lower), and the two lines represent the binary numbers 00, 01, 10,
It indicates the number of the instruction in the instruction queue register.

[Table] Line 32 which is the output of the instruction selection circuit b394
9. Line 321 may be used in place of the output of out pointer (OP) register r311, line 329, and output line 321 of AND gate g305 in FIG. 3, respectively. Therefore,
The out pointer register r311, ternary counter b315, selector S303, and AND gate g305 shown in FIG. 3 are no longer needed. Note that the selector S380 in FIG. 8 indicates the type of resource required by the instruction in the instruction queue register;
The number is selected according to the out pointer (on line 329), and this output line 311 is
It is used in place of the output line of the resource use check circuit b306 in FIG. As described above, the instruction control unit according to the present invention decodes read instructions one after another, activates instructions that can be activated one after another, and places instructions that cannot be activated into the instruction queue register. And when the resource is free and the vector register becomes available,
By activating instructions regardless of the order in which they are decoded, provided that there are no restrictions on the order in which vector registers are used, the time that resources and vector registers are free is shortened, and instructions can be processed in a shorter time. can be done. Vector register unit (1) Overview Figure 10 shows vector register unit U4.
is divided into a vector register control unit U40 and a vector register data unit U41. The vector register control unit U40 reads necessary data from the vector register VR in the vector register data unit U41 based on the command from the instruction control unit U3, and then outputs the data to the arithmetic units U20, U21 and the memory requester U1.
0, U11 (FIG. 5), arithmetic units U20, U21, and memory requester U1.
Control is performed to write the data sent from 0 and U11 into the vector register VR. It also notifies the instruction control unit U3 of the end of use of the vector register VR. Each of the vector registers VR holds a large number of vector elements, and here it is assumed that it is composed of a memory element as in the prior art. Therefore, an address counter (details will be described later) for indicating a write or read address is provided for each vector register VR. These address counters are controlled by the vector register control unit U4.
Controlled from 0. Reading of vector elements from vector register VR is performed by vector register control unit U40.
It should be noted that under the control of In this embodiment, when an element of vector data is being written to a certain vector register VR by executing a certain instruction, if there is a subsequent instruction that wants to read that vector register, any number of elements will be written to this vector register. When it is inserted,
Vector register chaining is performed so that a read operation is started in parallel with a write operation.
Moreover, with this chaining, if the write operation by the preceding instruction is performed intermittently,
Accordingly, reading by subsequent instructions is also performed intermittently. Furthermore, if an instruction uses two vector registers for reading, even if only some vector register elements have been written to at least one of these vector registers, these vector registers are Among the vector elements written in the vector element, the operation of reading elements with the same number as a pair is started. Furthermore, if the remaining elements to these vector registers are written intermittently, a pair of elements with the same number is read out every time the pair of elements becomes readable simultaneously. The vector data supplied to the arithmetic unit is usually
It is read from the main memory, temporarily stored in a vector register, and then supplied to the arithmetic unit from there. Data reading is performed in synchronization with the machine clock, but vector elements read from main memory are stored in vector registers every machine cycle due to read contention on main memory (for example, occurring when two memory requesters operate simultaneously). may not be written consecutively. At this time, vector element data to be supplied to the arithmetic unit intermittently arrives at the vector register and is written therein. Even under these conditions, read operations (chaining) are performed in parallel with writes, and when an instruction requires two vector registers, two
By simultaneously supplying vector data of the same vector element number of two vector registers, execution of an instruction can be started earlier. () Overview of vector register control unit The vector register control unit U40 is the 11th
As shown in the figure, an instruction activation control circuit b400,
Vector register control circuits b410 to b417 corresponding to vector registers VR0 to VR7, respectively
, operand control circuits b420 and b423 corresponding to the arithmetic units U20 and U21 and memory requesters U10 and U11, respectively, flip-flops f400 to f407 that hold outputs from the operand control circuits b420 and b423, respectively, and resource registers. Conversion circuit (hereinafter referred to as SG conversion circuit) b401, b404, b405,
It consists of a register-resource conversion circuit (hereinafter referred to as a G-S conversion circuit) b402 and b403. G-S
The conversion circuits b402 and b403 convert signals from any two of the vector register control circuits b410 to b417 to one or two vector register numbers for reading specified by the instruction control unit U3. It is sent to one of the operand control circuits b420 to b427 for the resource number to be sent to the SG conversion circuit b401 (or 404 and b4
05) corresponds to the vector register number for writing specified by the instruction control unit U3, in response to the signal sent from the resource with the number specified by the instruction control unit U3 (or the operand control circuits b420 to b427 for this). It is sent to one of the vector register control circuits b460 to b467 (or the vector register with this number). First, the instruction activation control circuit b400 receives an activation signal (on line 10), an instruction code (on line 11), a register number (on line 12) from the instruction control unit U3.
above), a resource type number (on line 13), and a processing vector length (on line 14), and when the instruction code requires the use of a vector register, the operation is as follows. (1) SG conversion circuit, b401, b404, b4
05, G-S conversion circuit, sends the resource number and vector register number necessary for conversion, and their set signals to b402 and b403. (2) Vector register control circuit b410 to b41
7, a write or read activation signal is issued to the specified vector register number. (3) Out of the operand control circuits b420 to b423, instruct the circuit for the specified resource type and number to receive the vector length data, its set signal, and for instructions that use only one operand. give a signal. When executing an instruction, control signals are transmitted as follows. Here, an explanation will be given of the operation when executing an instruction to read data from vector registers 0 and 1, perform arithmetic operations on arithmetic unit 0, and write the result to vector register 7. When it becomes possible to read a certain vector element in vector register 0, the vector register control circuit
A vector register read enable signal is output from br10 to line 480. Similarly, a vector register read permission signal for vector register 1 is outputted to line 481 from vector register control circuit b411. G-S conversion circuit b402, b4
At 03, signals on lines 480 and 481 are connected to output lines 490 and 500 for arithmetic unit 0, and are input to operand control circuit b420.
The operand control circuit b420 creates a vector data sending signal for each vector element and outputs it to the line 520 on the condition that these vector register read permission signals are present at the same time. This signal is once received by the flip-flop f401 and then sent to the arithmetic unit 0 via a line 43 as a data valid signal. On the other hand, the data sending signal on line 520 is also input to SG conversion circuits b404 and b405, and vector register numbers 0,
It is output to lines 540 and 551 corresponding to 1,
Or gates g400 or 401 and lines 470 and 471, respectively, are used to update read address counters (described below) for vector registers 0 and 1 in vector register data unit U41 (see FIG. 10). One of the features of the present invention is that the address counter (described later) for reading vector data is updated to the next address only after the vector element data sending signal (on line 520) is created. . The actual data reading operation is performed after confirming that it is now possible to read data from the two operands (vector registers 0 and 1 in this case). Now, the data valid signal V (on the line 43) and the vector element data are sent to the arithmetic unit 0, and the result of the operation is sent to the vector register data unit U41 via the line 45 (FIG. 10) as the data valid signal. V is returned via line 46 to vector register control unit U40. This data valid signal V is transmitted by the SG conversion circuit b401 to the line 437 corresponding to write vector register #7. In response to the signal on line 437, vector register control circuit b417 sends a write address counter update signal to vector register 7 to line 4.
27 to the vector register data unit U
It is located in the vector register control circuit b417 and is used to manage a pointer (described later) to indicate which vector element in vector register #7 has been written. This pointer is used to control reading up to the written vector element when the vector register 7 is written and used for reading this vector register in a subsequent instruction. When sending the final vector element to arithmetic unit 0,
To designate that it is final, operand control circuit b420 issues a final vector data signal E on line 510 in synchronization with the vector data send signal. That is, the circuit b420 is configured to memorize the processing vector length that is set at the start of instruction execution, and output the final vector data signal after outputting this number of vector data output signals. This signal is once stored in flip-flop f400 and then sent to arithmetic unit 0 via line 40.
It is sent back to the SG conversion circuit b401 via line 44 in synchronization with the final calculation result. The line 44 is transmitted to the line 427 corresponding to the vector register 7 by the SG conversion circuit b401, and is input to the vector register control circuit b417. The control circuit b417 terminates the write operation to the vector register 7, and notifies the instruction control unit U3 via line 16 that the write operation to the vector register 7 has been completed. On the other hand, the final vector data signal E on the output line 510 from the operand control circuit b420 is transmitted to the S-G conversion circuit b4.
04, b405 and output to lines 530 and 531 corresponding to vector registers 0, 1, and further OR gates g410, g411
It is then input to the vector register control circuits b410 and b411 via lines 460 and 461 to complete the read operation of the vector register, and is input to the instruction control unit U3 via line 15.
is notified that reading of vector registers 0 and 1 has been completed. () Instruction activation control circuit As shown in FIG. 12, instruction activation control circuit b4
00 is each line 1 from the command control unit U3.
a command activation signal ST input via 0 to 14;
The register number and type used by the instruction code, the type and number of resources used, and the processing vector length are stored in flip-flop f410 and registers RGR and r4, respectively.
00, RIG, r401, RST, r402,
Both RVIR and r403 are set in response to the instruction activation signal ST. The output of flip-flop f410 is S-G/
It is sent out via a line 419 as an information set signal to the G-S switching circuits b402 to b405 (FIG. 14) and others, and is also used to create various data signals internally. From the contents of RGR, r400, the SG conversion circuit,
A register number to be given to the G-S conversion circuit (FIG. 11) and an initialization/activation signal to be given to the vector register control circuit and vector register data unit are created. In a normal vector instruction, the R1 field uses the write vector register, and the R2/R3 fields use the read vector register. Therefore, the SG conversion circuit b401 in FIG.
R1 field register number, G-S conversion circuit b402, S-G conversion circuit b404, R'' field register number, G-S conversion circuit b40
3. The register number of the R3 field may be given to the SG conversion circuit b405. However, the second
As mentioned in the explanation with the figure, in the instruction to store vector data in main memory, the R1 field specifies the vector register number for reading, so the register number of the R1 field and the register number of the normal R2 field are used. It is necessary to transfer it to the outgoing signal line. For this purpose, RGRr400
GN1 field and V1 field together are line 4
39, it is sent to the SG conversion circuit b401, and is also input to the selector S400 as the first set. On the other hand, Gn2 of register r400 and
V2 field has selector S40 as the second set
0, one of them is selected and sent on a line 449 to the SG conversion circuit b404 and the GS conversion circuit b402. This sector S40
Decoder b438 performs selection control of 0, and RIRr
The director S40 selects the former or the latter depending on whether it is for an instruction code in 401 or not.
0 is controlled. The GN3 and V3 fields of the RGRr 400 are sent as they are to the SG conversion circuit b405 and the GS conversion circuit b403 via a line 459. Vector register control circuit b410 to b417
The R1-R3 fields of RGR, r400 are sent to decoder b430 to initiate a write to the vector register. decoder b
430 is a decode enable terminal E with AND gate A
The decoder is enabled when all input lines to AND gate A are "1". AND gate A of decoder b430 contains the V1 field, the W1 field, and the flip-flop f
The outputs of 410 are connected to lines 580, 581, and
419 is connected, and the GN1 field is input via line 439 as a signal to be decoded. decoding is enabled i.e.
The data in the GN1 field has meaning (V1 field = “1”), writing is specified (W1 field = “1”), and the instruction is activated (419 =
1), the contents of the GN1 field input via line 582 are decoded, and when this GN1 field has a number from one of vector registers 0 to 7, eight output lines 410 to 4 are input.
One of the 17 becomes "1". here,
When GN1 field is “0”, output line 41
When 0 is “1”, the output line 411 is “1”,
Assume that the output line 412 is decoded as "1" when it is "2". In the instruction we are currently considering as an example, the R1 field in RGR, r400 instructs writing to vector register 0 (W1 = 1,
GN1=0), so only line 410 is “1”
becomes. Output line 410 of decoder b430~
417 is a vector register control circuit b410~
b417 (FIG. 11) and the vector register data unit U41. decoder b4
33 to b435 are for starting reading of the vector register. These decoders have a decode enable terminal with AND gate A,
Instead of W1, W2, W3 fields, each is inverted gate g4 with inverted gates g420 to g422.
The inverted output from 20 to g422 is line 580,5
91 and the decoding is valid only when the field Ri of RGR, r400 is for reading (Wi=0), and the rest is the same as the Matsutaku decoder b430. The outputs of decoders b433 to b435 are output from OR gate g44.
0 to g447, and lines 400 to 407 respectively to the vector register control circuit b410.
~b417 and the vector register data unit U41 as a read start signal. In the above embodiment, the decoder b433 is omitted,
The output of selector S400 may be input to decoder b434. At this time, selector S40
0, the outputs of the W1 field and W2 field must also be input and selected together with the GN1 and GN2 fields, respectively. Decoder b436 is operand control circuit b4
20 to b423. Decoder valid terminal E has line 419
However, the resource type and number are input from RSR, r402 to the data terminal DI, and these are decoded and one of the lines 440 to 443 becomes "1".
becomes. Signal “1” on this line 440-443
are operand control circuits b420 to b4, respectively.
This serves as an activation signal for 23. Decoder b437 is operand control circuit b4
20 to b423 are provided to indicate cases where it is not necessary to synchronize two vector elements. Cases where synchronization of two operands is not required include, for example, storing vector data from one vector register to main memory, transferring vector data between a pair of vector registers, or converting vector data in one vector register. When there is only one vector register to read and the R3 field of the instruction is not required, such as when converting vector data to be stored in one other vector register,
At this time, the V3 field of RGR, r400 is "0". The decoder b437 has a decode enable terminal E with a 2-input AND gate A.
There, in addition to line 419, RGR, r400
An output obtained by inverting the output of the V3 field of 1 by an inverting gate g423 is input. decoder b437
deciphers the resource type and number given from RSR,r 402 and outputs "1" to one of lines 450 to 453. The output of decoder b437 is
They are connected to operand control circuits b420 to b423 via lines 450 to 453, respectively. The resource type number in RSR, r402 is also the SG conversion circuit b401, b via line 429.
404, b405, G-S conversion circuit b402, b
403 is commonly input. The processing vector length in RVLR, r403 is determined by line 469 for each operand control circuit b420.
~b423 are commonly input. () SG conversion circuit FIG. 13 shows a circuit in the SG conversion circuit b401 that supplies the data valid signal given from each resource to the vector register control circuit for the register number specified by the instruction control unit U3. It shows. In Figure 13, the resource type number is line 4.
29 is input to the data terminal of decoder b439, and the vector register number for writing is input to line 4.
Register r4 provided for resource via 39
10 to r413, and the command activation signal ST is
It is inputted to the decode valid terminal E of the decoder b439 through a line 419. Registers r410 to r4
13 are provided corresponding to memory requesters 0 and 1 and arithmetic units 0 and 1, respectively. On the line 439, in addition to the register number GN1, there is also the 12th register number.
As mentioned in the explanation of the figure, a signal V indicating whether the register number is valid is also included. These signals are in registers r410 and r413.
The resource type and number on the extension 429 are reset by the decoder b439. Register numbers GN1 in registers r410 to r413 correspond to decoders b440 to b4, respectively.
The V bit is input to one input terminal of the decoder valid terminal E with AND gate A of the decoders b440 to b443. The other input terminals of these terminals E receive data valid signals from memory requesters 0 and 1 and arithmetic units 0 and 1, respectively, through lines 46, 46', 29, and
29'. For example, under the condition that the output "1" of the V field in the register r410 is input to the AND gate of the decoder b440, when "1" is input from the line 46, the decoder b440 enters the decoding enabled state, and the GN of the register r410 The output of the field is decoded and any of the output terminals 0 to 7 of the decoder becomes "1", and the output line 420 of the OR gates g430 to g437 connected to each output terminal is output.
-427 becomes "1". These output lines 420-427 are vector registers 0-7
, and supply data valid signals to vector register control circuits 0 to 7, respectively. In this way, once registers r410 to r413
After the data is set to “1” on line 46,
The change of “0” is as it is, lines 420 to 427
can be communicated to either. What should be noted here is that as long as the register numbers in registers r410 to r413 are different, lines 46, 46', 29,
29' signals simultaneously on lines 420 to 420, respectively.
427 to the corresponding line. This simultaneous supply is possible for up to four register numbers. In this way, it becomes possible to operate four resources in parallel. The circuit portion of the SG conversion circuit b401 that supplies the final vector data signal supplied from each resource to the vector register control circuits 0 to 7 corresponding to the register number designated by the instruction control unit U3 is shown in FIG. lines 46, 46',
29 and 29' are connected to lines 44 and 44', respectively.
26,26', line 420~
It can be obtained by replacing 427 with lines 430-437. The SG conversion circuit b404 connects lines 52 from the operand control circuits 0 to 3 corresponding to each resource.
The vector data sending signal input via lines 0 to 523 is sent to the vector register of the register number specified by the instruction control unit U3 via line 540.
~ 543, and from the operand control circuits 0, 3 to lines 510 ~
513 to the vector register control circuits 0 and 7 for the resource number designated by the instruction control unit U3 via lines 530 and 537. In the former case, in FIG. 13, line 439 is replaced by line 449, lines 46, 46', 29, and 29' are respectively replaced by lines 520 to 523, and lines 420 to
427 by lines 540 to 547, respectively. The latter is similarly indicated by line 459 and lines 510 to 5 in FIG.
13 and 530-537. The SG conversion circuit b405 is also the circuit b
404, so the details are omitted.The signal line numbers after these replacements are
In Figure 3, signal line numbers 46, 46', 2
It is shown in the bracket after 9, 29', 420-427. () G-S conversion circuit Fig. 14 shows the G-S conversion circuit b402 (11th
Figure) shows the details. The resource type and number are input from the instruction activation control circuit b400 via line 429, the register number is input via line 449, and the set signal is input via line 419. The type and number of the resource on the line 429 are the register r corresponding to the vector register.
420 to r427, which corresponds to the register number on line 449. To specify the register to be set, the register number on the line 449 is input to the data terminal, and the set signal on the line 419 and the signal V indicating the validity of the register number on the line 449 are input to the AND gate A of the decoder b449.
It is controlled by a decoder b449 input to. The outputs of registers r420 to r427 are input to corresponding decoders b450 to b457, respectively. Decoders b450 to b457 are
When the vector register read permission signal input from the vector register control circuits 0 to 7 to the decode valid terminal E via the signal lines 480 to 487 becomes "1", the resource type and number input from the data input terminal are changed. Output "1" from any one of the corresponding output terminals. As a result,
OR gates g440~ connected to output terminals numbered 0~3 of decoders b450~b457, respectively
Lines 490-49 by any of g443
The line corresponding to the specified resource among 3 becomes "1". When any of the lines 480 to 487 becomes "0", the corresponding one of the decoders b450 to b457 is no longer valid for decoding, so the line 4
"1" and "0" of 80 to 487 are transmitted to corresponding signal lines 490 to 493 as "1" and "0". Note that once the resource number types set in the registers r420 to r427 are different from each other, the "1" signals on the lines 480 to 487 can be simultaneously supplied to the corresponding lines in the lines 490 to 493, respectively. Simultaneous provisioning can be performed for up to four resources. This allows parallel operation of four resources. Note that the G-S conversion circuit b403 in FIG.
Signal line 449 in FIG. 14 is replaced by line 459, and lines 490-497 are each replaced by line 50.
It can be obtained by substitution with 0 to 507. In addition,
In FIG. 14, the signal line numbers after the replacement are shown in brackets after the number of the signal line to be replaced. () Vector register control circuit Figure 15 shows the vector register control circuit b41.
This shows the details of 0. The other vector register control circuits 1 to 7 have exactly the same structure, and the lines 400, 410, 420, 430 in this figure,
460 and 480 can be obtained by replacing them with the line signals listed in brackets after these signal numbers. This control circuit performs three operations: a write or read only operation and a chaining operation (simultaneous write and read operations). (a) Write-only operation A write start instruction to vector register 0 is sent to line 4 by the instruction start control circuit b400 (Fig. 14).
10, flip-flop F420 indicating that writing is in progress is set, and up/down counter (hereinafter referred to as U/D counter) C400 is cleared. The U/D counter C400 has U,
The following output is supplied to the input of the D terminal. Input Output UD (Counter contents) 0 0 Unchanged 0 1 -1 1 0 +1 1 1 Unchanged When a data valid signal is input from the S-G conversion circuit b401 via the line 420 , this signal is
Through the AND gate g420 opened by the output “1” of the flip-flop f420, the U/D
It is input to the U terminal of the counter C400, increments the count by 1, and sends it as is to the vector register data unit U41 (FIG. 10). Line 430 from SG conversion circuit b401
When the final vector data signal is passed, this signal resets the flip-flop f420, halts the write operation, and sends it via direct line 430 to the instruction control unit U3 (first
RGSW, r306 (Figure 3)
The bit (Wj) corresponding to the write vector register number (for example, j) is reset.
Note that line 15 in FIG. 1 is obtained by bundling line 430 together with corresponding output lines 431 to 437 of other vector register control circuits 1 to 7. (b) Read-only operation When the write operation of vector register 0 has not been activated, a read activation instruction for this vector register is issued by the instruction activation control circuit b400 (11th
When the signal is transmitted through the twisted wire 400, the flip-flop f421 indicating that reading is in progress is set. Since flip-flop f420 is in a reset state, its output is connected to inverting gate g45.
1, is input via OR gate g452, and the output of flip-flop f421 is also input.
The output line 480 of AND gate g453 is “1”
becomes. Line 480 is a G
-S conversion circuit b402 (FIG. 11). Therefore, as explained with respect to the instruction control unit U3, when a vector register is used for reading in a certain instruction, a read-behind instruction that uses this vector register for writing is not activated until this reading is completed. Therefore, since flip-flop f420 is not set until this reading is completed, the read enable signal continues to be sent to line 480 until flip-flop f421 is reset. In this way, when all elements of veccle register 0 have been read out, S
A final vector data signal is input from the -G conversion circuit b404, and the flip-flop f421 is reset by this signal. Note that the line 460 is combined with the corresponding signal lines 461 to 467 in the other vector register control circuits b411 to b417 to form the line 16, which is connected to RGSW, r30 in the instruction control unit U3.
6 (FIG. 3) and is used to signal the completion of reading vector register 0 and to reset bit RO of this register. (c) Chaining Operation A chaining operation occurs when a write operation is first instructed to a certain vector register for a certain instruction, and then a read operation is instructed for another instruction before that operation is completed. Even if a write operation is instructed, the vector register will not actually be written unless a data valid signal and write data arrive from the resource. I don't care about the relationship. (c-1) For example, if a write operation is
0, the flip flop f4
20 is set, and the U/D counter C40
After zero is reset and before the arrival of the data valid signal from line 420, a read operation is indicated by line 400 and flip-flop 5
When 421 is set, U/D counter C
The output of the positive detection circuit b406, which detects that the content of the counter connected to the output of the AND gate g453 is 1 or more, is "0", and the output of the inverting gate g451 is also "0", so the output of the AND gate g453 is Output line 480 is also “0”
It remains as it is. Here, when a data valid signal comes to the line 420 in a certain machine cycle n, it passes through the ant gate g450 to the U/D
This signal is input to the counter C400, and the contents of the U/D counter C400 become +1 in this machine cycle n. Then, the output of the positive detection circuit b460 becomes "1", and a vector register read enable signal is outputted to the line 480 via the OR gate g452 and the AND gate g453. Line 480 is U/D
It is connected to the D terminal of the counter C400, and when no data is input from the next valid signal line 420 in the machine cycle (n+1), the value of the counter C400 returns to 0 after the machine cycle (n+1). Therefore, the read enable signal will be output on line 480 only once. Even after that, if the data valid signal is input intermittently,
Each time, it is output to the readable signal line 480. On the other hand, if the data valid signal is continuously input after machine cycle (n+1),
Since "1" is input to the U terminal and the D terminal, the value of the counter C400 does not change and remains "1", and "1" is continuously output to the line 480. (c-2) After a write operation is commanded by line 410, flip-flop f420 is set, and U/D counter C400 is reset, the data valid signal arrives over multiple machine cycles and each time U/D counter C400 is reset. Assume that the flip-flop f421 is set by read activation in machine cycle n while F421 is being counted up and displaying a non-zero value. U/
Since the output of the positive detection circuit b460 connected to the output of the D counter C400 is "1", a vector register read enable signal is outputted to the line 480. Since line 480 is input to the terminal of U/D counter C400, if the data valid signal from line 420 is not input in the next machine cycle (n+1), it will be -1, and if it is input, the value will not change. The above operation is repeated until the content of C/D counter C400 becomes 0. The number of read enable signals output on line 480 during a machine cycle after read activation is determined by the contents of U/D counter C400 before flip-flop f421 is set and the data valid signal input from 420 thereafter. It becomes the sum of numbers. In this way, (c-
In either case 1) or (c-2), it is guaranteed that the number of vector elements written in the vector register will not be read out. Note that the contents of the U/D counter C400 can be considered to represent the difference between the number of vector elements written into the vector register and the number of vector elements read from there. When writing is completed during chaining operation and flip-flop f420 is reset, U/
The contents of the D counter no longer have any meaning, and the operation is equivalent to the read-only operation in (b). () Operand control circuit Figure 16 shows operand control circuit 0, b420.
The details are shown below. The configurations of the other operand control circuits 1 to 3 are the same, and the signal line numbers in this diagram can be changed to the signal line numbers written in the brackets below. When the start signal is output from the instruction start control circuit b400 via the line 440, the processing vector length (VL) on the line 469 (assumed to be 1 or more) is selected by the selector S410, and the vector length counter (VLCTR) Set to C403. Also, this activation signal causes the U/D counter C to
The contents of 401 and C402 are cleared. Furthermore, flip-flop f431 is set,
It is stored that the processing of this operand control circuit 0 has become effective. If an instruction that requires memory requester 0, which corresponds to operand control circuit 0, only requires reading one vector register (assuming here that the instruction's R3 field does not specify a vector register read), then An instructing signal is transmitted from the instruction activation control circuit b400 via a line 450 to the flip-flop f.
Set 430. First, a case will be described in which both the R2 and R3 fields of an instruction requiring arithmetic unit 0 specify reading of a vector register. In this case, flip-flop f430 is "0". Lines 490 and 500 transmit vector register read permission signals from G-S conversion circuits b402 and b403 to counters C401 and C, respectively.
There are various ways in which this signal can be input using the signal line that is input to the U terminal of 402. Operations are performed in accordance with these cases for each machine cycle. Here, counter C401, C
402 is the same as the counter C400 (FIG. 15), and positive detection circuits b461 and b462 are the same as the positive detection circuit b460 (FIG. 15). (a) Case where both are not input This case has the following four cases. (a-1) U/D counter C401, C40
(a-2) When only U/D counter C401 is positive, (a-3) When only U/D counter C402 is positive, (a-4) When U/D counter C401, C40
When both of 2 are positive, cases (a-1) to (a-3) In these cases, andges g461 to
None of the outputs of G464 becomes "1" and no output is produced. Case (a-4) This case occurs already after the vector register read enable signal has been sent via lines 490, 500. At this time, the positive detection circuit b46
The outputs of 0 and b462 become "1", and the former is directly input, and the latter is input to AND gate g464 via OR gate g460. this and gate g4
The output “1” of 64 passes through OR gate g465,
It is input to AND gate g466. The output "1" of the flip-flop f431 is input to the AND gate g466. Furthermore, lines 630 and 631 are input to the AND gate g466, which will be described later. Here, it is assumed that both are "1". and gate g466
A vector data sending signal is output from the output line 520 of. Output line 520 is U/D counter C4
01, is input to the D terminal of C402, and the counter contents are decremented by 1. In addition, the output line 520 is VLCTR, C403
is input as a set signal and sets the counter value to 1.
only decreases. That is, the output of VLCTR,C403 is connected to the -1 subtraction circuit b463, and the -1 value is input to the selector S410. At this time, the control terminal of selector S410 no longer has line 4.
Since the command activation signal is not generated through 40, -
The output of the 1 subtraction circuit b463 is selected,
VLCTR, set in C403. This next circuit operation differs depending on the contents of U/D counters C401 and C402 and the input status of the vector register read enable signal from lines 490-500. Note that when the vector data sending signal is output to the line 520, the 1 detection circuit b464
When it is detected that the original content of VLCTR,C403 before being subtracted by 1 is "1", that signal is ANDed with the vector data sending signal in AND gate g467, and then is used as the final vector data signal. , is placed on line 510. The signal on line 510 also causes the flip-flop f
431 and f430. (b) A case in which only the line 490 is input; or (c) A case in which only the line 500 is input. Since the operation is the same in both cases, case (b) will be explained here. In this case, there are two further cases: (b-1) U/D counter C402 is “0”
When (b-2) U/D counter C402 is “positive”
Case (b-1) At this time, the output of the positive detection circuit b462 is "0", so the AND gates g461 to g4
64 does not become "1", therefore, the output of OR gate g465 and AND gate g466
If the output is also “0”, the U/D counter C401, C
The D terminal input of 402 remains at "0". No vector data send signal is output on line 520. Since the vector register read permission signal is input from the line 490 to the U terminal of the U/D counter C401, the U/D counter C401 is +
1 will be given. Case (b-1) At this time, since the output of the positive detection circuit b462 is "1", the output of the AND gate g462 becomes "1", and the vector data sending signal is transmitted via the OR gate g465 and the AND gate g466. 520. Since the operations such as resetting VLCTR, C403 and flip-flops f430 and f431 are the same as in case (a-4),
It is omitted here. Since the line 520 becomes "1", both the D terminals of the U/D counters C401 and C402 become "1". U/D counter C40
Since "1" is input to the U terminal of 1, the contents of the counter do not change. U/D counter C40
Since "0" is input to the U terminal of 2,
The contents of the counter are decremented by 1. (d) Case where both lines 490 and 500 are input at the same time This case can be further divided into the following four cases. (d-1) When both U/D counters C401 and C402 are 0, (d-2) When only U/D counter C401 is positive, (d-3) When only U/D counter C402 is positive, ( d-4) Case (d-1) when both U/D counters C401 and C402 are positive In this case, the output signal of AND gate g461 is set to “1” by the vector register read permission signals on lines 490 and 500. ”, and as a result, a vector data sending signal is output on line 520. The U terminals of the U/D counters C401 and C402 are "1", and the D terminal also receives "1" on the line 520, so the contents of the counters do not change. Operations such as control of VLCTR and C403 are (a
This is the same as the explanation for case -4). Cases (d-2) and (d-3) The operations in both cases are similar, so (d-2) and (d-3) are the same.
Let us discuss case 2). In case (d-2), U/D counter C4
Since the content of only 01 is positive, the positive detector path b46
Since the content of only 01 is positive, the positive detector path b46
The output of 1 becomes “1” and the AND gate g461
And the output of g463 becomes "1". A vector data sending signal is sent to line 520 via OR gate g465 and AND gate g466. The control of VLCTR, C403, etc. is the same as in case (a-4), so the explanation will be omitted. The contents of the U/D counters C401 and C402 do not change because they operate the same as in case (d-1). Case (d-4) In this case, U/D counters C401, C
Since the content of 402 is positive, the positive detection circuit b46
1, the output of b462 becomes "1", and all the outputs of AND gates g461 to g464 become "1". The following operation is similar to case (d-2), and a vector data sending signal is sent out on line 520. Similarly, the contents of U/D counters C401 and C402 do not change. As can be seen from the above description of the operation, the U/D counters C401 and C402 play a role in synchronizing the sending of two operands (vector data). When only one vector register read permission signal comes, it is stored in a counter (the counter is incremented by +1), and when it is taken out, the counter is incremented by -1. When the vector register read permission signals arrive at the same time, the contents of the counter do not change. Next, a case where only one operand is used will be explained. In this case, when the operand control circuit is activated, a flip-flop f430 is set to indicate that only one of the operands is used. This output is input to the other input terminal of OR gate g460 connected to the output of positive detection circuit b462, and the output of OR gate g460 is set to "1" regardless of the contents of U/D counter C402. In this way, line 490
As before, a vector data sending signal is generated only by the vector register read permission signal inputted from the vector register read permission signal. Note that a line 630 shown in FIG. 16 is a vector that permits transmission of a vector data transmission signal. This is used, for example, when it is desired to send vector data (therefore, a data valid signal) to the arithmetic unit at intervals longer than a certain interval (for example, when the arithmetic unit cannot receive data continuously). In this case, this enable signal is created within the operand control circuit. For example, the enable signal may be the output of a flip-flop that is reset by the data valid signal and set a certain time after the data valid signal. It is also used when temporarily stopping vector data sent to a memory requester (when storing data in the main memory again). In this case, this permission signal is generated by the main memory control unit U1 (see FIG. 5) or the memory requester. At line 630, when vector data transmission is not permitted, line 4
The vector register read permission signal input from 90,500 is sent to U/D counters C401, C4.
02 and the counter is updated. line 6
When a permission signal is input from line 30, line 490,
Even if there is no signal input from 500, the contents of U/D counters C401 and C402 are positive, so
The output of AND gate g464 becomes “1”,
A vector data send signal will be placed on line 520. At the same time, U/D counter C401,
C402 is set to -1. Further, the timing control circuit b465 is a circuit that controls the sending timing of the vector data sending signal. As will be explained in detail in the explanation of FIG. 18, each vector register is configured with two memory elements in order to perform reading and writing to the vector registers at the same time, and reading and writing to each memory element are alternately performed. Let's do it. That is, when writing to one memory element, the other memory element is controlled to read, and vice versa in the next cycle. Therefore, it is not possible to simultaneously read from a memory element that is being written to, so it is necessary to make the reading wait for that cycle and control the reading in the next cycle. For this purpose, control is performed so that the transmission of the vector data transmission signal is temporarily stopped. The timing control circuit b46 corresponds to this role.
In step 5, when it is determined that the vector data sending signal should not be sent in the next cycle, the timing control circuit b465 sets the output line 631 to "0" and suppresses the output of the AND gate g466. Specifically, the timing control circuit b465
It works like this: That is, when a vector data sending signal is input in a certain machine cycle, "1" is output in the next machine cycle, the second cycle, the fourth cycle, and so on. 1st cycle, 3rd cycle... Outputs "0" in the subsequent machine cycles. This timing is shown in FIG. When the vector data sending signal is input continuously, “1” is output in the next machine cycle, so the timing control circuit b46
Note that "1" is output continuously from 5 onwards. In this embodiment, the operand control circuit is
Although a case has been described in which read enable signals of two vector registers are input, it is also easily possible to create a vector data sending signal by inputting read enable signals of three or more vector registers. () Vector register data unit In FIG. 18, each of the eight vector registers is connected to a vector register circuit b470 to
Each vector register in b477 is configured with a memory element because of its large capacity.
A memory element can be given an address to write data to that location or read data from that location, but at the same time read data at different addresses.
Writing is not possible. To achieve chaining operation, write a certain vector element,
Since it is necessary to read other vector data at the same time, in this embodiment, two vector registers are configured with two memory elements m400 and m401 for one vector register, and reading and writing are performed alternately to these registers. Do this. This allows simultaneous reading and writing to different addresses. The numbering of vector elements is assumed to be such that even-numbered vector elements and odd-numbered vector elements are arranged in the same memory element. The details of the operation will be explained below. Writing and reading to vector register 0 will be described here, but operations to other vector registers are exactly the same. When the instruction is activated, the instruction activation control circuit b400 (FIG. 12) in the vector register control unit U40 causes the S-G conversion circuit b480, the G-S
The resource type and number are sent to conversion circuits b481 and b482 via line 439, the write vector register number is sent via line 439, and the write vector register number (both numbers since there are two operands) is sent via lines 449 and 459. Then, the above set signal is sent via line 419, and S
-G conversion circuit b480, G-S conversion circuit b48
1, set in b482. S-G/G-S
Conversion circuits b480, b481, b482 are the 13th
This is the same as that explained with reference to FIGS. Writing to vector register 0 operates as follows. First, a signal instructing to start writing to vector register 0 is sent from instruction activation control circuit b400 via line 410. This signal clears the write address counter C411 to 0. Write address counter C41
The output of 1 is input to selectors S420 and s421. The other inputs of the selectors S420 and s421 are the outputs of the read address counter C410, and the output of the timing control circuit b482 and the output obtained by inverting the same with the inverting gate g480 are input to the control terminals of these selectors, respectively.
The timing control circuit b482 is configured to receive a clock output every machine cycle using a trigger type flip-flop (not shown), and outputs "0" and "1" every machine cycle. Output alternately. Therefore, the timing control circuit b482 selects these selectors from the read address counter C41 at the selector s420.
When selecting an output of 0, selector s421
In this case, the output of the write address counter c411 is selected, and the opposite is selected in the next machine cycle. The output of selector s420 is given as the address of memory element m400, and the output of selector s421 is given as the address of memory element m401. Now, lines 45, 45' from arithmetic units 0, 1 or memory requesters 0, 1,
The write data is sent to S-G via 29, 29'.
Upon arrival at conversion circuit b480, this data is input from the resource specified on line 429 to one of vector register circuits b470 to b477 corresponding to the vector register specified on line 439. Here, since it is written to vector register 0, it is input to circuit b470.
The write data is stored in registers VRIRE, r430, VRIRO, r44 provided at the entrance of circuit b470.
0 according to instructions from VRIR input control circuit b484.
are set alternately. VRIR input control circuit b48
4, a data valid signal 420 is inputted, and VRIRE and VRIRE are input for each even and odd data valid signal.
Control is performed to set data in r430, VRIRO, and r440, respectively. There are two memory elements m400 and m40 in which cycles to write.
1 (details will be described later), it is not possible to write to any vector element in any cycle, and one cycle may be required. At this time, the same vector register circuit b4
Since it is convenient that the next write data arrives at 70, two registers VRIRE and VRIRO are provided, and different memory elements m4 are used for two successive write data.
It is now possible to write to 00, m401. The write instruction is given to vector register control circuit 0, (14th
This is done by a data valid signal input via line 420 from FIG. This signal is input to the write timing control circuit b483. circuit 48
3 is 2 according to even/odd write instructions
Two signals held during the machine cycle are output at the timing shown in FIG. 19, and these outputs are input to AND gates g481 and g482, respectively. On the other hand, the output of the timing control circuit b482 and the output obtained by inverting it by the inverting gate g480 are input to these ungates, and the outputs become write enable signals for the memory elements m400 and m401, respectively. Write address counter c
411 indicates the next address +1 circuit b4
+1 after 81. This control is performed by the output obtained by ORing the outputs of AND gates g481 and g482 with OR gate g48. Note that since writing is performed alternately to memory elements m400 and m401, the write address counter c411 only needs to be incremented by 1 after writing to both memory elements m400 and m401. Selector s420, s4 uses the value ignoring the lower 1 bit as the write address.
21. The same applies to the read address counter c410. As mentioned above, vector elements are memory elements m400, m
401 alternately. A time chart of the above operation is shown in FIG. Reading from vector register 0 operates as follows. First, a signal instructing to start reading from vector register 0 is sent from instruction activation control circuit b400 via line 400. This signal clears the read address counter c410. Initially, the read address counter c410 is cleared to 0, so
The address is given to memory elements m400 and m401 via selectors s420 and s421, and data at address 0 is read out and input to selector s422. The output of the timing control circuit b482 is connected to the control terminal of the selector s422 by an inverting gate g.
The inverted output is input at 480, which instructs which memory element to select the data read out from, and the output of memory m400 is used in the reading cycle of memory m400, and the output of memory m401 is used in the next cycle. Controlled to select alternately. The data selected by this is once set in the register (VROR) r450, and then
-S conversion circuits b481 and b482 convert the data into data corresponding to the resource. For example, if the data is the operand to the arithmetic unit 0, the data is
It is sent to arithmetic unit 0. Since only one data is required to be sent to the memory requester (data stored in the main memory), it is sufficient to use one G-S conversion circuit. Here, the circuit b481 performs G-S conversion. Every time one vector element of the vector data is sent out, the vector register control unit U40 sends out an update signal for the vector register read address counter c410 via the line 470. As a result, the read address counter c410 is updated by one. The update is performed by adding 1 to the output of the counter c410 by adding circuit b4.
This is done by returning it to the input of the counter c410 via the counter c410. As described above, the vector register unit reads vector data supplied to the resource and stores vector data sent from the resource. Here, the data to be supplied to the resource is 2 because two are required for the operation.
The two vector data must be aligned before being sent. Moreover, due to chaining action,
It is necessary to read vector elements on any two vector registers that are stored at unequal intervals in each vector register after confirming that the data for both are complete. To this end, we provide a circuit that detects whether each vector register can be read or not, and a circuit that detects whether the two data can be read for each resource. Data is read from the vector register only when it is readable. (Actually, the data has already been read, and the read address counter is updated for the read.) Memory Requester The circuit details of memory requester 0 are shown in FIG. The operations of the memory requester are divided into three: initialization operation at the time of instruction activation, read operation from main memory, and storage operation to main memory. () Initialization operation at the time of command activation In FIG.
The resource type and number are sent through line 11, the instruction code is sent through line 12, the register number is sent through line 12, and the processing vector length is sent through line 14. The resource type and number on line 13 are
When the decoder b100 decodes and specifies that it is the own memory requester, the decoder b100 outputs "1" and inputs it together with the instruction start signal on the line 10 to the AND gate g100, and the output line 100 “1” is output. Line 100 is input to flip-flop f100 to set the flip-flop and registers MIR, r100, MGR, r101.
The instruction code and register number are input to MIR and MGR, respectively. Line 100 is also input to the control terminal of selector s103, which selects the processing vector length on line 14, and sets the processing vector length counter (MVLCTR), c100, to the processing vector length. A line 100 is also connected to the set terminal of MVLCTR, c100. This completes the initialization operation. () Read operation from main memory It is known that the read operation is from the main memory by decoding the output of MIR, r100, in which the instruction code is set, by decoder b101. The output line 20 of the decoder b101 is sent to the main memory control unit U1 (see FIG. 1) to designate read or store operations, and is also input to the control terminals of selectors s104, s105, s106, and s107. Select the side marked “F” of each selector. Note that if storage in the main memory is specified by MIR, r100, the side of the selector marked with "S" is selected. The outputs of vector address register U5 and vector address increment register U6 (see FIG. 1) are input to selectors s100 and s101 via lines 18 and 19, respectively, and register numbers are set to MGR and r101.
the vector address register U5 specified by the output of the vector address register U5, and the vector address increment register U
6 is selected, and the vector address is passed through the selector s102 to the working vector address register (WVAR) r100 and the working vector address increment register (WVAIR) r1.
It is set to 11. Setting both registers is
It is controlled by an output line 101 to flip-flop f100. The line 101 is also connected to the control terminal of the selector s102, and the selector s100
control to select the output of When set to vector address WVAR, r110, line 21 connects main memory control unit U1 (FIG. 1).
The first vector element address is sent to At the same time, "1" is output from the non-zero detection circuit b104 connected to the output of MVLCTR, c100 (assuming that MVLCTR is set to 1 or more as the processing vector length), and via the selector s107,
It is sent by the main memory control unit U1 as an address valid signal on line 23. Line 23 is also input to the control terminal of MVLCTR,c100, causing the contents of MVLCTR,c100 to be -1. 1
The subtracted value is created by a 1 subtraction circuit b103 connected to the output of MVLCTR, c100, and is input to MVLCTR, r100 via selector s103. Furthermore, line 23 is WVAR,r11
It is also input to the control terminal of 0, WVAR, r110
and the contents of WVAIR, r111 are added to adder b102.
The result added in is passed through selector s102 again.
Control is performed to set WVAIR, r110. This makes the next vector element address
This means that WVAR, r110 is set.
By repeating this one after another, the vector address is determined and sent to the main memory control unit U1 via the line 21 together with the address valid signal (line 23), thereby performing the main memory read operation. When the read operation in the main memory is completed, the read data is returned via the line 24 and the data valid signal is returned via the line 25 from the main memory control unit U1. The read data on line 24 is sent to selector s
105, it is input to the data register DR, r120, and the line 25 passes through the selector s104,
Read data is input to the set terminal of DR,r 120 and is set in DR,r 120, the output of which is sent via line 29 to vector register data unit U41 (FIG. 10). Also,
The data valid signal on line 25 is once set in flip-flop f102 and sent via line 30 to vector register control unit U40. When MVLCTR,c100 is subtracted and the content becomes "1", the 1 detection circuit b105
is detected to be the final vector element, line 3
2, the final register data signal is sent to the main memory control unit U1 at the vector address (line 2
1), sent out with the address valid signal (line 23) and returned by line 33 synchronously with the read data. The final vector data signal on line 33 is once set in flip-flop f103, passes through selector s106, and is sent to vector register control unit U4 (10th
(Figure), but when the contents of MVLCTR,c100 become “0” after passing through the 1 subtraction circuit b103,
The non-zero detection circuit b104 outputs "0" and the sending of the address valid signal is stopped. This completes the vector data read operation. () Vector data storage operation In storing vector data, first, a signal specifying that storage is possible is sent to the main memory control unit U1 via line 20. This signal is
It is created by decoding the contents of MIR, r100 with a decoder b101. Sending out the main memory address of the data to be stored is exactly the same as the read operation. That is, a designated one of the vector address register and vector address increment register is selected by selectors s100 and s101.
selected by WVAR, r110, respectively.
WVAIR, set to r120. WVAR,
Similarly to the read operation, the vector address is sent to the main memory control unit U1 via the output line 21 of r110. The data to be stored comes from the vector register unit U4 on line 27 together with the data valid signal (on line 28). The vector data passes through the selector s105 and is sent to DR, r120.
is set to DR, r120 is controlled by connecting the data valid signal on line 28 to selector s.
This is done by inputting it to the set terminal of DR, r120 via 105. The data valid signal on line 28 is also input to a flip-flop, f101, whose output, once set, passes through selector s107 to DR, r1 on line 23.
It is sent to main memory control unit U1 together with the vector data to be stored on 20. As a result, the main memory control unit performs a write operation to the main memory. The address valid signal on line 23 is
WVAR, input to the set terminal of r110,
The use for updating WVAR,r110 is similar to the read operation. As described above, each time data to be stored and a data valid signal are sent from the vector register unit, the address is attached and sent to the main memory control unit, and at the same time, WVAR, r110 is updated and the next Provides storage of vector data. This is repeated as long as data is sent from the vector register unit. In addition, in the storage operation, MVLCTR,c1
00 operates similarly to a read operation, but has no meaning. The final vector data signal is line 32
Even if the data is sent to the main memory control unit due to the data processing, it is ignored during the storage operation. Arithmetic unit FIG. 21 shows an outline of the arithmetic unit 0. Arithmetic unit 1 also has the same structure. In this embodiment, the arithmetic circuits b210 to b213 perform partial arithmetic operations on inputs to each one under the control of arithmetic control circuits b201 to b204, as is already known. Here, we assume that the pipeline operation is executed in four stages.
There is no particular limit to the number of stages. Further, it is assumed that arithmetic units 0 and 1 can perform various operations specified by instructions. In this embodiment, when vector data and its data valid signal are input as input operands, they are operated on by the pipeline stage, and the resulting vector data and data valid signal are output in synchronization. , when the final vector data signal is input, this signal is also output in synchronization with the data valid signal. An outline of the operation will be explained below. An instruction start signal is input to the AND gate g200 via the line 10 from the instruction control unit U3,
The resource type and number are input to the decoder b200 via the line 13, and the instruction code is input to the register r200 via the line 11. decoder b
The output of 200 becomes "1" when the input thereto is for the own processor, and instructs register AIR, r200 to set the instruction code on line 11 via AND gate g200.
The output of AIR, r200 is the arithmetic control circuit b201
~b204 to control the operation of arithmetic circuits b210 to b213 in each stage. On the other hand, when vector data to be operated on is sent from the vector register unit via line 43, the vector data is transferred to registers r210 and r210.
At 220, the data valid signal is applied to the flip-flop f.
Set to 200. Data valid signal (4
3) is also used as a set signal to registers r210 and r220. Register r210, r2
The contents on 20 are calculated in the calculation circuit b210, and in the next cycle, the contents are stored in registers r211 and r22.
The intermediate result is set to 1. The output of flip-flop f200 is used to set the register, and this output is also transmitted to flip-flop f210. Similarly, registers r211, r21
The output of 2 is input to the arithmetic circuit b211 to perform arithmetic operations, and in the next cycle, the output is input to the register r21.
2, the intermediate result is set in r222. In synchronization with this, the output of flip-flop f201 is
It is transferred to flip-flop f202. Hereafter, by repeating this, the arithmetic circuit b212 and the register r2
13. As the data moves to the arithmetic circuit b213, the arithmetic operation progresses, and the final result is sent to the register r214.
is set to The data valid signal is also transferred from flip-flop f202 to flip-flop f203 to flip-flop f204. The result of the operation and a data valid signal indicating that the data is valid are returned to the vector register unit by lines 45 and 46, respectively. The data to be calculated is in registers r210 and r22
0 to registers r211 and r221, the next data to be operated on is transferred to registers r210 and r221.
The setting to r220 is the same as in a general pipeline arithmetic unit. When input to the flip-flop f210 by the final vector data signal line 40, the data is input to the flip-flop f210 in the same way as setting in the register.
Set to 10. Synchronous with the data valid signal moving through flip-flops f200-f204, the final vector data signal moves through flip-flops f210-f214 and is output on line 44 and returned to vector register unit U4. As described above, in the arithmetic unit of the present invention, vector data and a data valid signal are input synchronously, the data is operated in synchronization with the movement of the data valid signal through the pipeline stage, and the result is transferred to the data valid signal. Its feature is that it is output in synchronization with the valid signal. The same applies to the final vector data signal. As described above, according to the present invention, reading at irregular intervals and writing of results in synchronization with the reading at irregular intervals can be performed while the arithmetic unit is kept operating.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a vector processor according to the present invention, FIG. 2 is a diagram showing the formats of various registers used in the present invention, FIG. 3 is a diagram showing details of the instruction control unit, and FIG. 4 shows the details of the instruction queue, FIG. 5 shows the details of the resource usage check circuit, FIG. 6a shows the details of the register usage check circuit, and FIG. 6b shows the check conditions. , FIG. 7 is a diagram showing details of the register conflict check circuit, FIG. 8 is a diagram showing a modification of the instruction control unit, FIG. 9 is a detailed block diagram of b394 in FIG. 8, and FIG. 10 is a diagram showing a modification of the instruction control unit. , FIG. 11 is a detailed diagram of the vector register control unit, FIG. 12 is a diagram showing details of the instruction activation control circuit, and FIG. 13 is a diagram showing the configuration of the vector register control unit.
FIG. 14 is a diagram showing details of the G-G conversion circuit.
FIG. 15 is a diagram showing details of the S conversion circuit, FIG. 15 is a diagram showing details of the vector register control circuit, FIG. 16 is a diagram showing details of the operand control circuit, and FIG. 17 is a diagram showing details of the operand control circuit.
The figure is a time chart of the operation of the timing control circuit of FIG. 16, FIG. 18 is a diagram showing details of the vector register data unit, FIG. 19 is a time chart of the circuit of FIG. 18, and FIG. 20 is a diagram showing the details of the vector register data unit.
FIG. 21 is a diagram showing details of the requester, and FIG. 21 is a diagram showing details of the arithmetic unit.

Claims (1)

[Claims] 1. A main storage device, a plurality of vector registers, a plurality of arithmetic means each of which performs an operation in a pipeline manner, and a first
Reads the operand vector elements to be operated on from the vector register of the computer, supplies them to one of the plurality of operation means that executes the vector operation, and receives the operation results for those operand vector elements from the one operation means. a control circuit for writing a plurality of result vector elements outputted as a second vector register into a second vector register; means for reading an operand vector element from a vector register, and operating the one calculation means to read a certain operand vector element regardless of whether or not the reading means reads the vector element from the first vector register. and means for writing a result vector element outputted from the one calculation means into the second vector register in synchronization with a timing at which a certain period of time determined depending on the calculation time by the one calculation means has elapsed. Data processing equipment. 2. The reading means includes means for outputting a read valid signal in synchronization with reading of a vector element from the first vector register, and the writing means outputs a read valid signal output for a certain operand vector element. means for delaying a signal for a fixed time depending on the calculation time by the one calculation means; and the one calculation means for the operand vector element in response to a read valid signal output from the delay means. and means for writing result vector elements supplied from the second vector register into the second vector register. 3. The data processing device according to item 2, wherein the delay means is a plurality of storage means connected in cascade.