JPH0470657B2 - - Google Patents

Description

[Detailed description of the invention]

Field of use This invention applies to memory systems, especially those that cannot be corrected.
Restarting the memory system as a result of detecting errors
Regarding the constituent devices. Description of prior art Generally, the memory system is
to reconfigure memory system modules.
It has a device for Such a system was published on April 9, 1974.
Natsutata David Day Devoy and Jiyoji
J. Barrow U.S. Patent No. 3,803,560
has been disclosed. Other devices include mappiping, replacement algorithms and
important physical buffers such as
By changing memory parameters, buffer memory can be
It reduces storage capacity. This type of system has no.
It is disclosed in the specification of No. 3820078. Disclosed in British Patent No. 1411290
Other systems such as
In the event of a failure during rebanking, memory placement may be
optional to be able to change at will
Interleave corresponding to the number of addresses that can be changed to
It has a number of tabs. The prior art systems described above are automatic memory reconfiguration
However, such systems are subject to failure and
Removing these modules detected by
of a single controller or control device depending on
Reconfigures the memory module to operate under your control.
Ru. Additionally, such prior art systems are
If an error that cannot be edited is detected within that range, the
Keep the created memory area at the specified address arrangement
It is not possible. For example, this memory area is the basic
Operating system software is stored
corresponds to the area to be used. purpose of invention Therefore, the main purpose of this invention is to
can be automatically reconfigured to provide memory space
A memory system that includes one or more controllers
It is about providing. Furthermore, it is an object of the present invention to
Automatically restart to save memory space system
By providing a configurable memory controller
be. The above and other objects of the invention are
This is accomplished with a preferred embodiment of a moly system. Summary of the invention A memory system has many memory controllers.
and each of the controllers is a data processing device.
A common bus for receiving instructions and data from
Connect to. Memory failure caused by data processing equipment
is detected, the memory controller attempts reconfiguration.
reconstructed by a given type of instruction to identify
Ru. During such reconfiguration, the memory system is
The architecture or organization will turn on the failed controller.
to save adjacent memory space.
Install the other remaining good controller in its place.
changed by changing. Moreover, in the memory system of this invention,
A portion of the controller memory designated as failed.
is switched offline and communication continues as above.
Controller to operate remaining normal memory
It will continue to be continued. In a preferred embodiment of the memory system, each
The controller receives reconfiguration commands from
Configuration Controller Address and Control Information Bits
It has a reconfiguration mode control register to store the
It has a reconstruction device. Note the control bits.
code to identify the operating state of the recontroller.
be converted into The reconfiguration device is the controller that reconfigures the
Mode to indicate when to operate in operating mode
It has a control device. Mode controller reconfigured
When set to a predetermined state by an instruction,
The corresponding controller will reconfigure the address bits.
specified accordingly. i.e. that controller
Only the method that specifies the reconfiguration controller address
Responds to Mori commands. At least one pair of control information bits are
used to specify the offline state of the controller.
Meanwhile, other bits are reconfigured by the controller.
Instruct how. To explain in more detail, each controller
The controller is a controller that contains the controller's control logic.
includes a motherboard and multiple daughterboard pairs.
It is configured so that Each of the daughter boards
Total memory capacity that a controller can have
including a predetermined capacity of In a preferred embodiment, 2
There are paired daughter boards, each daughter board is
Contains 1/4 of total memory. Offline Bit is a device that is connected offline.
encoded to indicate the number of computer boards.
Ru. In other words, this bit applies to all daughterboards.
Is everything offline or online?
and a pair of daughterboards.
the daughter is connected offline or
1/2 of the board pair is connected offline
Instruct. The signal representing the offline bit is input as input.
controller bus response circuit. bus response
The circuit determines whether the board is installed inside the controller or not.
receives a signal from each of the daughter boards that tells
connected to believe. In a preferred embodiment
, each controller has two pairs of daughter boards
or a pair of daughter boards
Either. Bus response during normal operation
The circuit includes a controller with two pairs of daughter boards.
or a pair of daughter boards.
Includes or does not include features and options.
Responds to bus commands as fly bit state
occurs. For maintenance or diagnostic operations, the bus response circuit
Does the controller include two pairs of daughter boards?
or includes a pair of daughter boards.
whether the command is in online memory or not.
or offline memory.
as a function of whether you want to set or specify
generates a response. Indicates how the controller was reconfigured.
The control bits have at least one pair of bits.
Ru. The first bit is exchanged by both daughterboard pairs.
(i.e. replacing 1/2 board) What has been done
is encoded to specify. second bit
The section in the daughter board is replaced (i.e.
1/4 board replacement).
encoded to determine the In addition, the reconfigurator sets the reconfiguration register in mode
Has an identification register that connects to the control device and bus.
are doing. That register contains one of the control information bits.
corresponding to the predetermined bits and state of the mode control device.
Stores error status signals, including signals that Both the reconfiguration register and the identification register
The memory system controller is interleaved
operating in operation mode or bank operation mode.
Contains instructions specifying what to do. The memory system of this invention has interleaved operation.
operation and/or bank operation mode.
can work with. Multiple bank systems
independently accessible memory units are temporarily
In a system where one memory is accessed every
Ru. Memory units in the bank system can be accessed independently.
Only one address at a time can be accessed in the bank.
It is considered to be the smallest unit that can be accessed. An interleaved system has many addresses in parallel.
Multiple memory units to access columns
It is interleaved through. In accordance with the principles of this invention, a memory controller
System architecture changes can lead to memory failure.
Location and memory system reconfiguration mode
type (i.e. bank mode or interface)
This is done as a function of leave mode). for example,
The controller is fully populated (i.e.
(including two pairs of daughter boards), the failure is addressed
If it happens at a location with 0, the control
The reconfigurator is a failure at the top of the controller memory.
Replaced 1/2 board and 1/4 board to move to 1/4.
Conditions are set such that the Does this memory system have multiple controller pairs?
and each controller is in interleaved mode
and one controller is completely failed.
the remainder allocated to the topmost memory space when
One of the normal controller pairs of is then off-line.
A failed controller that is turned on can be replaced.
I can do it. In such an arrangement, the controller pair
The remaining good controllers then operate in bank mode.
can be made. As mentioned above, depending on the type of system reconfiguration,
However, this invention provides contiguous memory space.
and system behavior (i.e., operating
required for system software memory area)
memory control to save some memory space.
It can be seen that automatic reconfiguration of the rollers is possible. Schematic description of the system in Figure 1 Figure 1 shows a data processing system including the device of this invention.
Indicates the time. Referring to Figure 1, the system has many subsystems.
Stems 20-1 to 20-n and central processing unit
(CPU) Contains a multi-line bus connected to 40
I understand that. Only the memory controller is shown, but the
The system in Figure 1 was usually published on December 28, 1976.
Disclosed in U.S. Pat. No. 4,000,485
It turns out that it is equipped with other equipment like this.
Ru. Each memory subsystem is labeled A through D.
2 pairs, i.e. 4 memory modules
memory controller that addresses up to the unit
(i.e., 200-1 to 200-n)
There is. As mentioned above, each memory module unit
The circuit is the motherboard containing the controller control circuit
located on the daughter board that connects to the In a preferred embodiment, a memory controller
is fully populated (i.e. daughter board
containing two pairs of ) or semi-populated
(i.e. includes one pair of daughter boards)
It is. For purposes of this invention, CPU 40 is conventionally known as
The microprogrammed processing used
It is a mechanical device. Richard A. Leemey and Jiyoung Ae
Invented by Le Carley, January 5, 1978
No. 867,266 filed in U.S. Patent Application No.
In addition to "a system that provides information requests"
The co-pending application cited above provides further details.
It can be used as a reference. In addition, the Jiyoji G.E.B.
- Related application of Lowe et al. “Main data processing system device
and to control the transfer of information between central subsystems
'Interface' can also be used as a reference.
Wear. CPU40 and each controller and each
The Mori subsystem is described in U.S. Patent No. 4000485.
via bus 10 in a predetermined manner disclosed in
connect. Simply put, the device you want to communicate with is a bus cycle.
request a bus cycle, and once the bus cycle is granted.
That device becomes the “master” and the rest of the system
A device can be addressed as a “slave”.
Wear. Requires a response (e.g. memory read operation)
For these bus exchanges, the requesting device is
Identify yourself as “master” and slave
Indicates that a response is required from the device. When the slave is ready to respond (e.g.
For example, obtaining requested information)
Reve assumes the role of “master” and requests
starts transferring information to the target device. Therefore, the number of bus cycles is the number of operations performed.
Varies depending on type. to the control line as described with respect to Figure 2.
By changing the state of the applied signal,
One device is initiated into another device
or specify the type of operating cycle to be performed.
be able to. A distributed tie-breaking network is
Allow bus cycles and synchronize for use of bus 10.
When resolving requests. Priority is based on physical location on bus 10
the highest rank is the first on the bus.
given to the device. In a typical system, the memory subsystem
is allowed the highest rank, and the CPU is
with other devices positioned by
Allowed. Memory subsystem interface Before explaining the controller in Figure 1, each component
From the interface between controller and bus 10
It can be seen that there are a number of lines constructed. As shown, there are many interface lines.
address lines (BSAD00−23, BSAP00),
Two sets of data lines (BSDT00-15, BSDP00,
BSDP08) and (BSDT16−31, BSDP16,
BSDP24), numerous control lines (BSMREF−
BSMCLR), numerous timing lines
(BSREQT−BSNAKR) and numerous tiebreakers.
-King Network Line (BSAUOK-
BSIUOK, BSMYOK). The explanation of the above interface line is below.
Explained in detail. Memory subsystem interface lineName explanation address line BSAD00−BSAD23 The bus address lines are
Transfer the 24-bit address to the controller 200.
or from the controller 200 to the bus
16 bits (to be received by the rave device)
A bus memory reference label is used to transfer the
24-bit wide aisle used in connection with inn
Consists of. Signal applied to lines BSAD00−BSAD03
is used for memory addressing.
Therefore, if you select a specific 512K word module,
Lines BSAD04−BSAD22 are in the module
Select one of the 512K words. On the other hand, the line
The signal applied to BSAD23 is the selected word (i.e.
BSAD23=1=right side byte; BSAD23=1
= left side byte). Line BSAD00 is used for identification
-BSAD07 is not used. Lines BSAD08-BSAD23 read the previous memory
is transmitted to the controller 200 during the request.
The receiving device's identification signal is transmitted so that the receiving device BSAP00 Bus address parity line is
Address signal applied to BSAD00−BSAD07
Bidirectional LA providing odd parity signals for
It's in. data line BSDT00−BSDT15, BSDT16−BSDT31 bus
The set of data lines corresponds to the operating cycle being performed.
The function is to transfer data between the controller 200 and the bus.
32 bits to transfer data or identification information.
In other words, it constitutes a two-word wide bidirectional passage. During the write operation cycle, the bus data line is
Addresses applied to lines BSAD00−BSAD23
memory location identified by the source signal
Transfer information so that it is written to. During the first half cycle of a read operation, the data
In BSDT00-BSDT15 is controller 200
Readout to transfer identification information (channel number) to
During the second half cycle of operation, the data line
Transfer the information read from the memory. BSDP00, BSDP08, BSDP16, BSDP24 bus
The data parity line is encoded as below.
Two sets of bidirectional signals providing odd parity signals
It's a line. BSDP00 = line BSDT00 - BSDT07 (left side bar
odd number for the signal to be applied to
parity BSDP08 = line BSDT08 - BSDT15 (right side bar
odd parity for a signal applied to
stomach BSDP16 = applied to lines BSDT16 – BSDT23
odd parity for signals BSDP24 = applied to lines BSDT24 – BSDT31
odd parity signal control line BSMREF The bus memory reference line is
Extends to the memory controller 200. When set to true, this line is lit.
BSAD00−BSAD23 are complete memory controllers.
address, and can be written at a specific location.
command to perform a write or read operation.
A signal is sent to the controller 200. When reset to false state, the line becomes
BSAD00−BSAD23 are directed to other devices and
Contains information that cannot be directed to the controller 200.
A signal is sent to the sea urchin controller 200. BSWRIT Bus write line is the bus-to-memory
Extends to the controller 200. This line is true when set to the true state.
The write operation size is related to line BSMREF.
controller 200 to execute the program.
issue a number. When reset to false state, this lamp
read in relation to line BSMREF which is true.
control to perform the eject motion cycle.
Signal to LA 200. BSBYTE The bus byte line is controlled from the bus.
It extends onto the roller 200. This line, when set to the true state,
should perform byte operations rather than read operations.
A certain signal is sent to the controller 200. BSLOCK The bus lock line is controlled from the bus.
It extends onto the roller 200. When set to true, this line is tested.
Execution of a program or
The state of the memory lock flip-flop that is
Controller request signal to change
Put it out at 200. BSSHBC bus second bus cycle half cycle
The cruise line is connected to the bus by the controller 200.
The current information applied to the previous read request
The information requested by
Used to send signals to equipment. In this case, the controller 200 and information
The controller 200 of both receiving devices
Initiation cycle until transfer completes
busy for all devices from the start of the file.
It is. This line is the memory lock flip-flop
to set or reset the
Used with BSLOCK line. The device requests a read or write.
and line BSLOCK is true, line
BSSHBC is true and its lockflipf
controller 20 to reset the
Give a signal to 0. When in false state, it is the lock flip
To test or reset the flop
A signal is issued to the controller 200. Is BSMCLR Bus Master Clear Line a bus?
and extends to the controller 200. When this line is set to true, this
The controller 200 is a controller
A certain bus circuit in 200 is cleared to zero. BSDBWD 2x word line is controller 2
It is a unidirectional line that extends from 00 to bus 10.
Ru. This line along with the BSDBPL line is read
How many words of data is being requested?Memory
Format provided by controller 200
Indicate what kind of format Matsuto is.
used for Read response from memory controller 200
During the cycle, the state of line BSDBWD is 1 work.
or two words of data are printed on bus 10.
Indicates whether or not to be added. Line BSDSWD is set to binary “1” state
, which indicates that two words have been transferred.
Ru. If only one word is transferred, the line
BSDBWD is set to binary "0". BSDBPL 2x pull line is controller 2
It is a bidirectional line that extends between 00 and bus 10.
Ru. This line along with line BSDBWB is
The first device (last
device) or is the last device
Instruct the fish. Bass handshake/timing line BSREQT The bus request line connects the bus
It is a bidirectional line extending between 200 trollers.
Ru. When set to true, other devices can
signal that it is requesting an cycle.
Send it to Troller 200. When reset to false state, bus request
There is no bus pending.
A signal is sent to the controller 200. This line is used for the second bus cycle for reading.
control to request a half cycle.
is set to the true state by the controller 200. The BSDCNN data cycle line connects to the bus.
It is a bidirectional line extending between 200 trollers.
Ru. When set to true state, the device is requested
Bus cycles are allowed for other devices on the bus.
A signal to be placed on the information is sent to the controller 200.
put out. Controller 200 receives the requested data.
signal to send the data back to the device.
Sets in to true state. Prior to this, the controller 200
bus cycle is allowed. BSACKR The bus acknowledge line is the bus and control
This is a bidirectional line extending between rollers 200. Set to binary “1” by controller 200.
When the line is connected to the first bus service for reading
During half cycle or write cycle
Signals that bus transfers are accepted.
vinegar. Half cycle of second bus cycle for read
Inside, this line is the outfit that is making the request.
When set to binary “1” by the
An attach signal is sent to the controller 200. BSWAIT The bus waiting line is connected to the bus and controller.
This is a bidirectional line extending between the lines 200 and 200. The binary “1” state is set by the controller 200.
When set to state, the controller will
Receive a signal that the transfer cannot be accepted.
Send it to the quest device. Thereafter, the device is rotated by the controller 200.
begins successive retries until the request is acknowledged.
Ru. The controller 200 operates under the following conditions.
Set the BSWAIT line to true. 1 All queue registers are full
is busy when . 2 Busy when in initial mode.
The BSWAIT line is a binary “1” depending on the device.
When set to , this means that the data is
The current
The signal that should terminate the bus operation cycle of
Output to the controller. BSNAKR The bus negative acknowledge line is in contact with the bus.
This is a bidirectional line extending between rollers 200. This line is set to 2 by the controller 200.
When set to the forward “1” state, the specified transition
sends a signal indicating that transmission is being refused. The controller 200 has a line as shown below.
Set BSNAKR to true state. 1 Memory lock flip-flop is binary
Set to “1”. 2 Request is locked flip-flop
(BSLOCK is true and BSSHBC is false) In all other cases, the memory lock
Once the lipflop is set, the control
La 200 is BSACKR line or BSWAIT line.
generate a response via
No response occurs. BSNAKR line is made true by the device
and this means that the data is not accepted by the device.
It is said that the operating cycle should be terminated.
A signal is sent to the controller 200. tie-breaking control line BSAUOK-BSIUK tie-breaking network
- line from the bus to the controller 200
Bil. These lines indicate that higher priority devices are
whether you are requesting a
A signal is issued to the controller 200. All signals on these lines are binary
When “1”, this causes BSDCNN
At what time can the line become a binary “1”?
Bus cycle permission signal to controller 200
put out. Any one of the signals on the line is a binary “0”
, this allows bus cycles
line BSDCNN becomes binary “1”.
The controller 20 sends a signal that prohibits
Put it out on 0. BSMYOK tie-breaking network cry
The line extends from the controller 200 to the bus. The controller 200 is a low level bus request
This line is used to signal other devices in the
to binary “0”. BSYELO The bus yellow line is a bidirectional line.
It is. The second bus server responds to the read command.
When set to true state during half cycle of cycle
and that the accompanying transfer information is successful.
be corrected. Set to true state during memory read request.
This line indicates that the read request is
that it should be translated as a command
Instruct. Schematic description of the memory subsystem in Figure 1 Figure 3 is constructed using the principles of this invention.
Memory subsystem including controller 200-1
This is a preferred embodiment of the program 20-1. To explain FIG. 1, the controller 200-1
are two 256K word memory modules in the memory section 210.
control device 210-2 and 210-4
I understand that. Modules of blocks 210-2 and 210-4
The roll equipment includes blocks 210-20 and 210-20.
High-speed MOS random access memory compatible with 40
Integrated circuits and blocks 210-22-210
-26 and 210-42 to 210-46 compatible
It includes an address buffer circuit. Each 256K memory device is illustrated in detail in Figure 4c.
1-bit dynamic MOSRAM as shown
It consists of 64K words written on a chip. In more detail, FIG. 4c will be described. 22 bit
Each 256K by memory module is 1 bit
Contains 88, 65, 534 (64K) words by Each chip contains a 256 row by 256 column map of memory cells.
There are many memory arrays made up of
I understand that. Controller 200-1 receives memory timing signals.
Refresh operation, control operation
operation, data transfer operation, address distribution and decoding operation
and bus interface operations.
Contains these circuits required for. Such a circuit
Included as part of the different sections of FIG. The section is timing section 204, ref.
Tsushiyu control unit 205, data control unit 206, ad
response unit 207, read/write control unit 208,
Data 209 in the cushion, bus control circuit section
211, memory initialization circuit section 212, buffer
driver/receiving circuit section 213 and reconfiguration control
216. The bus control unit 211 operates for one word and two words.
Generates and accepts bus cycle requests.
It includes a logic circuit that generates signals for. As can be seen from Figure 3, these circuits and
The circuits of other sections are conventionally well known.
via section 213 driver/receiver circuit.
connected to the bus. Section 211 describes the physical location of devices on the bus.
Type to resolve request priority based on
Contains raking network circuitry. The first memory module located on the leftmost side of bus 10
Controller 200-1 is assigned the highest rank.
On the other hand, the central processing unit located at the top of the bus
CPU 40 is assigned the lowest rank. For more detailed information on bus operation
is a U.S. Patent issued December 28, 1976.
It is disclosed in specification No. 4000485. As shown in detail in Figure 4a, the tie
The processing unit 204 performs memory read and write operations.
Timing signal sequence required from cycle
includes a circuit that generates energy. As can be seen from Figure 3, this section
Cushion 205, 206, 207, 208, 21
1,213 and 215, section 205,
206, 207, 208, 211, 213 and
215, transmitting and receiving signals and transmitting or receiving signals.
Ru. As illustrated in detail in Figure 4b,
The response section 207 performs refresh operations, initial settings, and
address signals required for read/write operations.
Contains circuitry to decode, generate, and distribute signals. Section 207 is the main line from the BSMREF line.
line BSAD00− in addition to the reference control signal
Receives address signals from BSAD23 and BSAP00.
believe Furthermore, section 207 is section 20
Control and control from 4,205,212 and 215
and timing signals. The memory initial setting section 212 controls the controller circuit.
To clear the initial state, that is, the predetermined state,
Including the circuit of knowledge. The read/write control unit 208 is conventionally often used.
Contains registered registers and control logic. The register circuits are BSWRIT, BSBYTE,
Corresponding to the state of the BSDBWD and BSAD23 lines.
receive and store signals. The control circuit decodes the register circuit signal,
The controller performs read and write operation cycles.
followed by a kuru (i.e. for a byte command)
Whether a write or read should be performed
Sections 204, 207 and
and 210. The refresh unit 205 periodically refreshes the contents of the memory.
Contains a circuit for refreshing. Section 205 is a tag from section 204.
receive timing and control signals, section 2
Refreshed on 04, 207, 208 and 212
Provides command control signals. For more information, see the refresh command
The circuit for generating the (REFCOM) signal is described.
Disclosed in U.S. Pat. No. 4,185,323
It is. Day in section of block 209-4
The 209 circuit consists of a pair of multiplexer circuits and
Connected to receive signals from section 206
Contains address registers that are Conventionally, the well-known multiplexer circuit is
Two sets of bus lines BSDT00−15 and BSDT16−
Receive data word from 31 and write operation cycle
Medium, output lines MDIE000−015 and MDIO000−015
a specific word into a normal memory module through a pair of
Apply. That is, the initialization signal from 212
INITTM310 is a binary “0” (i.e., initial
(not rise mode), the multiplex
The circuit is generated by AND gate 209-10.
selectively activated by signal MOWTES000
be done. AND gate 209-10 is the bus address bit
22 (i.e., signal BSAD22).
When the controller performs a write operation (i.e., the signal
BSWRIT)
Generates MOWTES000. During a write operation, the signal MOWTES000 is
Normal data words (all
That is, bus line BSDT00−15 or
(word applied to BSDT16-31). This allows write operations to start on word boundaries.
You can During a read operation, the multiplexer circuit
Modules received from bus lines BSDT00−15
address bus line BSAD08-23.
The condition is such that it is applied again. This is the even data register in section 206.
A signal applied to line BSDT00-15 at 206-8.
This is done by loading the number. This then causes block 209-4 to
Dress register latch is on bus line BSDT00-15
Transmits module identification information via. This is not about understanding this invention.
It will not be discussed further here. The data control unit 206 has two sets of three-state operating data.
data registers 206-8 and 206-10,
even and odd memory units in section 210.
written in locations 210-20 and 210-40,
related to control circuits that can be read from or
Associated multiplexer circuits 206-16 and 2
Including 06-18. For example, during a double-width read operation, the operand
Alternatively, the command signal is the device 210-20 and
Read from 210-40 to even and odd registers
be done. During the write operation cycle, signals MDIE000−15 and
and MDIO000-15 via section 209-4.
register pairs 206-8 and 206 from the bus
- loaded to the leftmost side of 10, section 2
Written to 10 odd or even devices. In accordance with the teachings of this invention, section 206
Additionally, status registers 206-20 and identification registers
registers 206-22. status register 206
-20 is used to isolate memory anomalies
Connected to store memory error information. For example, registers from section 207
Address bit and single bit error correctable
In order to isolate the abnormality to the RAM chip in the case of
EDAC circuits 206-12 and 20 required for
Union of EDAC syndrome bits from 6-14
Store the details. Status register 206-20 is
Contains status information about new single bit errors.
double bit error that cannot be corrected.
remains fixed in the case of Identification register 206-22 identifies the type of reconfiguration and
and the reconfiguration control unit 216 that identifies the operation mode.
connected to store signals received from the receiver. Additionally, section 206 is connected to block 206.
-24 red and yellow generators included. These circuits ensure that the information transferred to bus 10 is
error, and whether the error can be corrected.
signal indicating whether or not it can be corrected.
The yellow generator circuit that generates the
The information transmitted together with the received signal is normal.
normal operation is performed (i.e., hard
A binary “1” indicating that the
Make it. The error generation circuit is configured to handle the information transferred together with an error.
– (i.e., an uncorrectable error condition)
Other signals are set to binary "1" to indicate that. These signals are connected to other bus lines (not shown).
(not included). A more detailed explanation of the occurrence of these signals
is disclosed in US Pat. No. 4,072,853. Controller 200-1 performs error detection and correction.
(EDAC) equipment included. Each word of that device is
16 data bits and a single bit in a data word
Detection and correction of test errors and data language
Signaling without detection and correction of double bit errors
Contains 6 check bits used to
nothing. The EDAC device has two sets of EDAC encoder/decoder
and circuits 206-12 and 206-14. These circuits are covered by a US patent issued February 7, 1978.
The form of the circuit disclosed in specification No. 4072853
Take. On top of that, section 206 is a data line
Received from BSDT00 and address line BSAD08
-23 to register 209-4.
Enables return of separate information. The queue control unit 215 further includes the controller 20
Included as part of 0-1. This section handles many memory requests simultaneously.
Stores address and control signals for processing at
Contains circuitry for storage. As can be seen from Figure 3, section 215 is
Sections 204, 205, 207, 211 and
and 212. that sexy
section 204, as shown.
206, 207 and 208.
Ru. The operation of this section is related to this invention.
Since I don't have one, I won't go into details here. In accordance with the teachings of this invention, the reconfiguration control unit 2
16 is a circuit for enabling controller reconfiguration.
including roads. As can be seen from Figure 3, section 216 is
Sections 207, 208, 211 and 212
Receives address and control signals from. Section 216 is section 206, 207
and provides control and status signals to 211. Relevant parts of the above sections are shown in Figures 4a--
This will be discussed in detail in connection with FIG. 4c. Detailed explanation of the controller section These sections are necessary to understand this invention.
Only Kushion is mentioned here. Get more information about its remaining sections
Please refer to the related application or U.S. No. 4,185,323.
Please refer to the book. Section 204 and Section 206 FIG. 4a shows the timing circuit for section 204.
FIG. The circuit is traditionally constructed using the well-known delay line type
input timing from a timing generation circuit (not shown).
Timing pulse signal DLYINN010, TTAP01010
and receive TTAP02010. Such a circuit is described in U.S. Pat. No. 4,185,323.
It takes the form of the timing generation circuit disclosed in
Ru. The timing generation circuit is switched to binary “1”.
Series connection 200ns in response to signal MYACKR010
Generates a series of timing pulses through a pair of delay lines
do. These pulses associated with the circuitry of block 204
for the remainder of the memory operation cycle.
Confirm the timing. Additionally, the circuitry of block 204 provides a boundary signal.
Access from MYBNDY010 and section 207
Receives address signals LSAD22200 and LSAD22210
do. Furthermore, section 212 is similar to section 204.
Apply initialization signal INITMM100 to. When signal MYBNDY010 is set to binary “1”,
NOR gate that sets signal RASINH010 to binary “0”
204-5. The series-connected AND gate 204-7 is a signal
Initialize signal to generate RASINH000
INITMM100, section 205 (not shown)
generated by circuits in
The command signals REFCOM100 are logically combined. NAND gate 204-8 is an even row strobe
signal to generate inhibit signal ERASIH000
RASINH000 and address signal LSAD22210
Join. The signal is sent through AND gate 204-1.
Timing signal obtained from No.DLYINN010
AND gate to be combined with MRASTT010
204-10. The resulting output signal MRASTE010
is printed on the RAS timing input of even stack devices.
added. NAND gate 204-14 inhibits odd rows
signal to produce the default signal ORASIH000.
Combine RASINH010 and LSAD22200. This signal synchronizes the row timing signal MRAST0010.
Tie with AND gate 204-17 to occur
combined with the timing signal MRASTT010. This signal is connected to odd stack units 210-40.
Applied to RAS timing input. As can be seen from Figure 4a, and204-1
1 is a refresh command (i.e., a signal
REFCOM000=1), even data record
G input terminal of the middle section of register 206-8
Apply the timing signal MDOECT000 to the child. Similarly, AND gate 204-15 is an odd number
Middle section of data register 206-10
The timing signal MDOOCT000 is input to the G input terminal of
Apply. AND gate 204-3 is a timing signal
Signal to generate MCASTT010
MRASTT010, REFCOM100 and
Combine TTAP01010. Signal MCASTS010 is AND gate 204-1
8 through even and odd stack devices 210-
20 and 210-40 CAS timing inputs
added to. In a similar manner, AND gate 204-19
Generate timing address signal MCASAD010. The signal MCASAD110 is the AND gate 204
-20 to section 207 address circuit
added to. Even and odd data registers 206-8 and
and 206-10 are of the three-state operating type. more details
According to the explanation, the register is SN74S373 manufactured by TI
From a D-type transparent latch circuit like
configured. The register circuit receives the signal applied to the G input terminal.
is binary “1”, the signal at the Q output terminal is the D input
Trigger in the sense that it follows the signal applied to the power terminal.
It is transparent. In other words, the signal applied to the G input terminal is low level.
When the signal reaches the bell, the signal at the Q output terminal latches. Outputs of registers 206-8 and 206-10
Terminal allows multiplexing of data word signal pairs
Commonly connected to the wired OR device. Such multiplexing can be achieved by using the register shown in Figure 3.
Different sectors of stars 206-8 and 206-10
signal applied to the output control (OC) input of the system
MQ2ELB000, MQ1ELB000, MDOTSC000 and
This is done in conjunction with the state control of MDRELB000 and MDRELB000.
This operation is in response to a signal applied to the G input terminal.
Is the register flip-flop latch operation caused by
It is independent from Series connection of gates 204-22 to 204-26
The group is the state of signals MDOTSC100 and MDOTSC010.
control the situation. AND gate 204-22 receives identification information from the bus.
Read or write support to enable storage of information.
At the beginning of the cycle, the timing signal DLY1NN010 is
and receive DLY020100. This is the invention
Signal PULS20210 is binary as it is not relevant to understanding
It is considered to be in the "0" state. During read operation, read command signal READCM000
is set to binary "0". Depending on that binary “0”
And gates 204-26 are the signal
Set MDOTSC100 to binary “0”. Signal MDOTSC100 is a register when it is binary “0”.
The middle section of registers 206-8 and 206-10
When you enable a section, its contents are
Apply force to the terminal. During a write cycle, read command signal
When READCM000 is set to binary “1”, the AND
Gates 204-26 convert signal MDOTSC100 into binary
Set it to “1”. This produces the opposite result. That is, signal MDOTSC100 is input to register 20.
The middle section of 6-8 and 206-10
prohibits its contents from being applied to its output terminal.
Ru. Most of registers 206-8 and 206-10
In the left section, the signal MDRELB000 is binary.
When “0”, add its contents to its output terminal
be able to. For the purpose of this invention, signal MDRELB000 is
It is considered to be a binary "1" state. Therefore, the rightmost section of the register
can add its contents to its output terminal by
It is forbidden. Most of registers 206-8 and 206-10
The two sections on the left are connected to section 215.
The signals MQ1ELB000 and
Controlled by the state of MQ2ELB000. When binary “0”, signal MDOTSC000 is
Signal Q1TRST010 from section 215 and
Register 206 as a function of the state of Q2TRST000
The leftmost side of either -8 or 206-10
enable one of the two sections of
Ru. When signal Q1TRST010 is binary “1”, the
No. Q2TRST000 is binary “0” and section 21
5 sets the signal MQ1ELB000 to binary "0". this
registers 206-8 and 206-1 by
The Q1 part of 0 can add its contents to its output terminal.
and make it possible. Conversely, if signal Q1TRST010 is binary “0”
signal Q2TRST000 is binary “1” and the
The pin 215 sets the signal MQ1ELB000 to binary “0”.
Ru. This causes registers 206-8 and 2
The Q2 part of 06-10 sends its contents to its output terminal.
Allows you to add. Finally, the circuit of block 204 is described here.
The clock supplied to the circuit of block 216
Generates lock signal CLOCK1010. See Figure 4.
The AND gate 204-33
signal in response to timing signal PULSCK010.
Generates CLKCK1010. Signal PULSCK010 is 20
positive timing with a range between 50 nanoseconds and 50 nanoseconds
pulses and irregular memory cycles (e.g.
During the refresh cycle, etc.), the signal
To eliminate the occurrence of CLCK1010, the signal
Gated by PARTWT000 and CYCINH000. The timing signal PULSCK010 is the inverter rotation
After being reversed by path 204-31, the timer
Timing signal DLY3Y0010
By combining with TTAP06010, Android game
generated within port 204-32. signal
CYCINH00 is the section of signal PARTWT000.
While being generated by the circuit of 208, the
Signal REFCOM110 from section 205 and
Noah Gate 204-30 in response to STOPCY010
generated by. Section 207 FIG. 4b shows different sections of the address field 207.
Indicates the Section 2 as shown
07 is input address section 207-1, address deco
code section 207-2 and address register section 20
7-4 included. Sections 207-1 and 207-2 The input address section 207-1 is the input address from the circuit 213.
Least Significant Bus Address Bit 22 and Section
High chip select address bits from 216
Store signals BSADX3110 and BSADX4110
207-12. Address strobe signal ADDSTR000 is binary
When set to “0”, the three signals are transferred to the register 207.
-12. This occurs when memory becomes busy. (vinegar
In other words, bus cycle/memory request reception
hair) For brevity, register 207-12
is the queue for section 207 (not shown).
It can be considered as part of Further information regarding such queuing devices can be found at
Robert B. Johnson and Chester
Co-pending U.S. patent issued by M. Nibiy General
Application, filed on October 31, 1980, application number 202821 “I
Memory processor with interleaved queuing device
``Ntrolola'', and Jiyoji G.A.B.A.R.O.
-, Chester M. Nibby and Robert
Co-pending U.S. Patent Application of B. Jiyeon-Sung, 1981
Filed on December 17th, Application No. 331933 “Inter
memory controller with a spaced queuing device.
``Pasing Device for La''. Furthermore, section 207-1 is block 20
7-15 boundary detection circuits are included. That circuit is
D type flip-flop via gate 207-18
Nando connected to the D input terminal of Tsupu 207-19
Includes gate 207-16. Nand Gate 207-16 is a memo from bus 10
Receives rerequest address bits 22-19.
Ru. Address bits 22-19 are all binary
When it is “1”, the gate 207-16 is a boundary signal.
The output detected by the number DBSA16000 is set to binary “0”.
do. In all other cases, the signal
DBSA16000 is a binary "1". 2 word transfer is real
When executed, the signal BSDBWD110 is a binary “1”.
be. When it is a binary “1”, the flip-flop
207-19 to a binary “1”.
By No. DBSA16000, ANDGATE 207-
18 sets the signal BOUNDY110 to binary "1". This allows signal MYBNDY010 to
It becomes a binary “1” indicating that there is no boundary condition.
Ru. When signal DBSA16000 switches to binary “0”,
As a result, the signal BOUNDY110 becomes binary “0”
, flip-flop 207-19 becomes binary
Switch from “1” to binary “0”. The signal NYBNDY010 is connected to the timing section 204.
is applied as an input. As shown, the high order address bit signal
LSAD05210 and LSAD04210 are binary decoder circuits
207-20. lowest
Bit address signal LSAD22210 and inverter
its complement generated by the data circuit 207-22.
Signal LSAD22200 is connected to sections 204 and 20
Added to 6. The binary decoder 207-20 connects the gate (G) terminal.
It is activated by grounding. 4 decode outputs DECOD0000～
Each of DECOD3000 is Nand Gate 207-24
~207-30 different pairs of ground. 0 decode signal DECOD0000 is 0 row address
NAND game that generates the probe signal DRAST0010
Connect to the input of ports 207-24. Similarly, 1 decode signal DECD1000 is 1 row address.
Nan that generates the rest strobe signal DRAST1010
connected to the input of gate 207-26. next screen
- The sequential decode signal DECOD2000 is
– Kensial row address strobe signal
NAND gate 207-2 that generates DRAST2010
Connect to 8. Finally, the last decoded signal DECOD3000 is
Generates 3-row address strobe signal DRAST3010
Connect to NAND gate 207-30. Furthermore, these gates are AND gate 207
-32 receives signal OVERDEC000. When signal OVRDEC000 is binary “0”, this
This is the REFCOM100 or INITMM100
When either is in “0” state, the signal
Each of DRAST0010 to DRAST3010 is binary “1”
state. Even and odd row add as shown
The rest strobe signal can be used for even and odd stack configurations.
RAM chips for 210-20 and 210-40
applied to the loop. Section 207-4 Address register as shown in Figure 4b.
The data section 207-4 is the queue register of the section 207.
of the row address register 207-40 through the register.
Different stages, column address registers 207-42 and
and the bus added to the input of the adder circuit 207-54.
Receives address signals BSADX5210~BSAD22210
do. Registers 207-40 and 207-42
The gate input terminal that enables operation is the register input
is held at a binary “1” which allows the signal to accumulate.
Ru. OC input terminal of row address register 207-40
The children are signals INITMM000, REFCOM000 and
ANDGATE 207 in response to MCASAD110
-44 inverter circuit 207-46 and NAND
Timing generated by gate 207-47
connected to receive the programming signal MRASCT000.
Ru. OC input of column address register 207-42
The terminals respond to signals INTREF000 and MCASAD110.
In response, it was generated by NAND Gate 207-50.
To receive the timing signal MCASCT000
connected to the Signal INTREF000 is a signal
The address that receives INITMM000 and REFCOM000
is generated by the second gate 207-44. Address registers 207-40 and 207-
Each of 42 is a D-type truck like the SN74S373 mentioned above.
It consists of a transparent latch circuit. As can be seen from Figure 4b, each set of registers
Different address output terminals output these address signals.
A common wired OR device for multiplexing
Connected. As mentioned above, such multiplexing is done in register 2
Output control (OC) for 07-40 and 207-42
by controlling the state of the signal applied to the input.
will be achieved. In more detail, the output control (OC) end
The children are controlled by circuits 207-44 to 207-50.
This allows so-called 3-state operation to be controlled. Each of the signals MRASCT000 and MCAST000
When in binary “1” state, this is any address.
The signal is also added to the output terminal of the register associated with it.
It is prohibited to be As mentioned above, this operation is a register flip-flop.
It is independent of the latching action of the lock. Additionally, in a preferred embodiment of the invention,
Section 207-4 is address register 2.
Connect in parallel to 07-40 and 207-42
Conventionally well-known 3-bit binary full adder circuit
including. The adder circuit 207-54 has a lower address bit.
Connected to increment bits 19-21 by one. Furthermore, to explain in detail, input terminal A1-A
4 is the queue address register in section 207
Bus address signal from BSAD21210,
Receive BSAD20210 and BSAD19210. binary
“0” signal is applied to input terminals A8 and B1-B8.
available. The lowest address signal BSAD22210 is shown in Figure
Adder terminal C as shown₀carry signal to
added as. As mentioned above, the source of the bus address signal is
from the queue address register of section 207.
be. The incremental output signal produced at the sum terminals S1-S4 of the adder
No. MADD00111 to MADD02111 are multiplexers
In addition to one set of input terminals of circuit 207-56,
It will be done. Input terminal of multiplexer circuit 207-56
The second set of children is the queue address of section 207.
address signal from the register BSAD11210,
To receive BSAD12210 and BSAD13210
Connected. This eliminates register delays.
It will be done. Multiplexer circuit 207-56 enables
is activated by grounding the power supply (EN) terminal.
Ru. Sex applied to gate (G0/G1) terminal
The signal MCASAD110 from John 204 is multiplexed.
added to the output terminal of the lexer circuit 207-56
Controls address signal source selection. i.e. the signal
When MCASAD110 is binary “0”, the address
signal BSAD11210, BSAD12210 and
BSAD13210 is signal MADD00211~MADD02211
It is the source of When signal MCASAD110 is binary “1”,
Adder signals MADD00111 to MADD02111 are signals
This is the source of MADD00211~MADD02211. The RAM chips in the odd stack in Figure 4c are
address via the response buffer circuit 210-46.
To receive signals MADD0010~MADD07010
connected to. The even stack RAM chips in Figure 4c are
When the number MCASAD110 is binary “0”, the address
Address signal via response buffer circuit
Connect to receive MADD0010~MADD07010.
Continued. When signal MCASAD110 is binary “1”,
Incremental output signal MADD00111~MADD02111 is the signal
MADD00010 to MADD02010 and signals
Even stats instead of MADD03010~MADD07010
It is added to the RAM chip of the block. Memory devices 210-20 and 210-40-th
Figure 4c As previously discussed, blocks 210-20 and 2
10-40 even and odd word stacks
The stack is shown in detail in Figure 4c. These stacks are shown as
4 rows for 22 64k x 1-bit RAM chips
It becomes more. Each 46k chip has two 32,768 bits
Contains memory array. Each array is a 128 row by 256 column matrix.
Organized into a matrix with 256 sense amplifiers
Connecting. Other 64k chip configurations are also used.
Ru. The chip and its associated gate circuitry are
mounted on the controller board. Each daughter board is read from section 208
Receives the corresponding signal among the write/write command signals.
Two inverters (as shown) are connected to
) and the matrix from section 204
Timing signals and lines from section 207
4 connected to receive the decoded signal
2-input NAND gate (e.g. 210-200~
210-206 and 210-400 to 210-
406). These tips are relevant to understanding this invention.
Only the steps are shown. Remaining terminals (not shown)
(not connected) are connected in the normal way. As a reference for further information, 1978
Application No. 921292 filed on July 3rd “Rotating Chip”
There are ``Tip Selection Techniques and Devices''. Section 216 FIG. 4d is a reconstruction of a preferred embodiment of the invention.
FIG. 3 is a detailed diagram of the control circuit. These circuits are
in response to diagnostic commands received from the management device 40.
to reconfigure the controller daughter board
generates a signal. As shown, section 216 has three
Input 8 output binary decoder circuit 216-2, EDAC
Mode flip-flop 216-4, a set of controllers
controller address switch 216-6, reconfiguration level
register 216-8, reconfiguration mode flip-flop
216-10, controller address multiple
Lexer circuit 216-12, address mode multi
Plexer circuit 216-14 and block 216
-16 controller address circuits. Signal LSYEL0010 is set to binary “1” and the signal
When LSWRIT010 is set to binary “0”, the decoder
Circuit 216-2 becomes operational. Circuit 216-2 is a queue for section 207.
Supplied from the register and connected to terminals A, B and the circuit.
and a binary encoded signal supplied to C.
BSAD21210, BSAD20210 and BSAD19210
Pairs of the terminals of that circuit according to their specific sign
Set the corresponding terminal to binary “0”. For example, bits 19, 20 and 21 are “000”
, the signal READID000 is set to binary “0”.
It will be done. Similarly, binary, “001”, “010”, “011” and
“100” is the signal READST000,
SETEDA000, RESEDA000 and RECONF000
Set to binary “0”. As shown, signal SETEDA000 is
is inverted by the inverter circuit 216-19, and the
D-type flip-flop via the gate 216-18.
Preset (PR) input terminal of loop 216-4
added to. On the other hand, the signal RESEDA000 is the inverter circuit 21
Inverted by 6-21 and NAND gate 216
Clearing the same flip-flop through -20
(CLR) terminal. nand gate 216
-18 and 216-20 both section
Receive timing signal PULS20010 from 204
do. Flip-flop 216-4 further
Section 211 added to the Tsuk(C) input terminal
The signal BSMCLR310 is received. On the other hand, the data
The data input terminal (D) is grounded. flip flop
The binary “1” and “0” output terminals of 216-4 are
identification register 206-22 and block, respectively.
EDAC times of Tsuku 216-12 and 206-14
added as input to the path. If the signal EDACMM000 is binary “0”, then
signal is a set of check bit signals (i.e.,
MDIECO-5) to circuits 216-12 and 2
16-14 to be set to binary “0”
Ru. Signal READID000 is the identification register 206-22
is applied to the OC terminal of On the other hand, its complement signal
READID110 is connected via inverter circuit 216-22.
to the gate (G) input terminal of register 206-24.
Added. Similarly, signal READST000 is a status register.
applied to the OC terminals of registers 206-20. generated by the inverter circuit 216-23.
Signal READID110 and signal READST110 are
data multiplexer circuits 206-16 and 20
6-18 is added as an input. Signal READID110 or signal READST110
When either is a binary “1”, it is a multi
The plexer circuit adds the data signal to the bus.
prohibit. This allows registers 206-20 or
The contents of 206-22 are replaced in place of that signal.
It will be done. Status registers 206-20 include a pair of serially connected
contains registers, each containing odd and even sectors.
It has a long history. The first register is a standard integrated latch circuit.
(74LS273). latch or button
Each section of the buffer register is block 206.
- upon detection of a read error by the 24 circuit.
Timing signal from section 6
Has a clock input that receives MYDCNN210
Ru. Uncorrectable errors occur in even or odd numbers.
circuits 206-24.
The signal MYDCNN210 is connected to the latch register.
It is prohibited to be added to Yong (S). this is
Register contents to facilitate diagnostic testing
Make it fixed. The latch register section is a bus clear signal
Readings from section 216 in addition to BSMCLR110
Output status signal READST000 or reset date
0 depending on either signal of data signal RESEDA000.
cleared or reset. The output signal from the latch register section is data output.
A second tri-state output level connects to lines MUXD00-15.
added to the register section. This register is also register 207 in Figure 4b.
- Bus 10 in the same way as 40 and 207-42
To control reading of the contents of the latch register to
Receives the signal READST000 used for condition
The status register device clears and clears the status as described above.
Allows updating of read error status conditions in addition to fixing
vinegar. The last decoder output signal RECNF000 is waiting
With signal BSAD07210 from column register 207
is provided as one input to the NOR gate 216-24.
be provided. The Noah Gate 216-24 is an
supplied as one input to gate 216-26.
Generates signal RECONF110. and gate 2
16-26 is a binary "1" during normal operation.
Battery mode signal from section 212
Receive BATTMM000. Section 204?
The timing signal CLOCK1010 is a normal memo
During recycling, AND gate 2 as third input
16-26. output signal
MCONCK010 is a different register 216-8
Supplied to the clock input terminal (CLK) and (C) of the stage
be done. The signal RECONF110 is sent to the decoder circuit 216
−2 forced to binary “1” and signal
When BSAD07210 is binary “0”, the timing
The clock signal CLOCK1010 is connected to the AND gate 216-26.
makes the signal MCONCK010 binary "1". For signal BSAO7210, the bus address bit
7 is system-wide for all memory controllers.
In response to a command specifying a general reset, the binary
It is set to “1”. This address bit is an instruction bit.
The addressed memory command is reset along with the
stored in the queue section of the controller.
However, the signal from queue register 207
Since the number BSADO7210 is a binary “1”, it is not accumulated.
The reconfiguration signal generated by the reconfiguration command
In response to signal RECONF000, signal RECONF110 is activated.
Noah Gate 216-24 sets it to binary “1”
prohibit. This means that the reconfiguration mode flip
Loop 216-10 performs a general system reset operation.
to prevent it from being set again. Transition of clock signal MCONCK010 to positive polarity
section 20 in register 216-8 by
Address of bus memory request received from 7
The status of the bit signals BSAD08210 to BSAD17210
enable loading. Furthermore, the signal MCONCK010 is connected to the inverter circuit.
216-28, flip-flop
A signal to the preset (PR) terminal of pull-up 216-10.
Added as No. MCONST100. When signal MCONST100 switches to binary “0”,
The flip-flop switches to a binary "1". pretend
The data (D) terminal of flip-flop 216-10 is
No. BATTMM00, RCFGU010, BSAD07110,
BSMREF110, BSAD19110, BSAD20110,
In response to BSAD21110, and BSYEL0110,
NOR gates 216-29, inverter circuit 216
-33, and Nand Gate 216-30, 21
Signals generated by 6-31, 216-32
Receive RCONCT110. timing signal
DCNR60110 is a flip from section 211
Supplied to the clock (C) input terminal of flop 216-10.
be provided. Signal BATMM000 is out of controller
It is a binary “1” indicating that it is not in operation mode.
signal BSYEL0110, BSMREF110,
BSAD19110 and BSAD07110 are binary “1”
and the signals BSAD20110 and BSAD21110
When it is binary “0”, NAND gate 216-3
0 makes the signal RCOUCT110 a binary "0". child
This means that the timing signal DCNR60110 is binary
When switching from “0” to binary “1”, the reconstruction mode
flip-flop 216-10 is binary “0”
Allows the device to be reset to Reconfiguration mode
Flip-flop 216-20 resets to binary “0”.
The reconfiguration code address bits are
bits 19, 20, 21 and bus address bit 7
is determined. This allows non-reconfiguration diagnostic mode.
of one of the memory controllers when the
Reconfiguration mode flip-flop accidentally cleared
Prevent from being exposed. As shown, register 216-8
One stage indicates that system power is established (i.e.
(enabled), then switch from binary “0” to binary “1”
The system generated by the section 211
Cleared in response to system power-on signal PWONLL010.
It will be done. When the signal PWONLL010 is binary “0”, the register
Clear the star stage to 0. Signal INTERL000
The interleaved mode flip-flop to be stored is
Signal applied to the PR input terminal of that stage
Power is turned off in binary “1” state by PWONLL010.
be turned off. That is, signal PWONLL010 is 2
When the binary value is 0, the interleave mode stage is binary.
Switch to “1”. Its binary is the signal INTERL000
Set to binary “0”. Reconfiguration mode flip-flop 216-10
The binary “1” output is an enabled multiplexer.
for selecting the control input terminal of the circuit 216-12.
register 206-22 and NAND gate 2
16-30. As can be seen from Figure 4d, the multiplexer circuit
Route 216-12 is a manual switch as shown.
Controller address signals from S1 to S4
When receiving the first set of BSSW00010 to BSSW03010
Ru. Some of those switches are closed.
This is the address signal BSSW00010~
Set the corresponding signal of BSSW03010 to binary “0”
Make it. When the same switch is opened, this corresponds to
Set the address signal to binary “1”. Binary “1” belief
The number is the pull-up resistor 216- connected to the voltage +V.
34-216-42.
Ru. added to multiplexer circuit 216-12
The second address signal RCONF0010 to RCONF3010
The set of is bus address bit BSAD08210 ~
Register 21 that stores the status of BSAD11210
Obtained from stages 6-8. When signal RCFIGU010 is binary “0”, the master
The multiplexer circuit 216-12 is a signal
Sweets as a source for BSSW00110~BSSW03110
Select S1 to S4. When signal RCFIGU010 is binary “1”, the master
The multiplexer circuit 216-12 is a signal
Regis as a source for BSSW00100~BSSW03110
selects the designated stage of data 216-8. The signals from the remaining switches S5 and S6 are
comparison circuit 216-16 and multiplexer circuit 2
16-14. Sunawa
The signal INTESW000 is a series connected inverter circuit.
via 216-44 and Noah Gate 216-46
to control the selection of multiplexer circuit 216-14.
added to the input terminal. The status of switch 85 is
Controller operates in interleaved operating mode
bank operation mode is activated.
Ru. If switch S5 is open, the signal
INTESW000 is binary “1” and controller address
The address specification mode is set to binary “1” while the power is on.
Interleaved mode flip-flop
specified by the state of the step. this is a signal
Set INTERL000 to binary “0”. This is Noage
signal INTERL110 by gate 216-46.
Set to binary 1. Signal INTERL110 is binary “1”
When , the multiplexer circuit 216-14 is
Signal BSADX3010, BSADX4010 and
Address bit signal as source for BSADX5010
BSAD03110, BSAD04110 and BSAD05110
select. During controller reconfiguration, the bank operation mode is
The address bit signal BSAD17 is binary “0”.
At some point, close switch S5 or turn on
Turn the flip-flop stage into binary in terleave mode.
specified by either switching to “0”.
Ru. As a result, the signal INTERL110 becomes binary “0”.
do. The binary “0” signal is sent to the multiplexer circuit 21
Signal BSADX3010 by 6-14,
As a source for BSADX4010 and BSADX5010
Address bit signals BSAD04110, BSAD05110 and
and BSAD18110. Signal BSADX5010 is the queue for section 207
Row address register 207-4 via register
Added to 0. The queue register is for every memory operation cycle.
Performs the necessary storage of the memory request address of
cormorant. Signals BSADX3010 and BSADX4110 are shown
A pair of exclusive OR circuits 216-5 as shown in FIG.
Configuration signal HALFBS010 within 0 and 216-52
and is logically combined with QARTBS010. The resulting signal BSADX3110 and
BSADX4110 has section 2 to decode
Added as input to 07. Furthermore, the signal
HALFBS010 and QARTBS010 are Noah Gate 2
Interleave module generated by 16-46
identification register 206 along with code signal INTERL110.
-22 is added as an input. inverter times
The last sweet added via route 216-54
The touch signal MODINH000 is connected to block 216-16.
Used to enable/disable the comparator circuit.
used. When switch S6 is open, the signal
MODINH000 is binary “1”. Comparison circuit 2
16-160 and 216-162 each
When it is in the state, it is enabled. When switch S6 is in the closed state, the signal
MODINH000 is binary “0” and circuit 216-1
60 and 216-162 are rendered inoperable. Next, consider the circuit of block 216-16.
Ru. Comparison circuits 216-160 indicate that the controller
When operating in interleaved operating mode,
These controls used for memory communication
address input signal. Comparison circuit 21
6-162 is in bank operation mode for memory communication.
This controller address input signal used for
receive the signal. Either circuit 216-160 or 216-162
detects a true comparison, it is a signal
Compatible with MYADG0100 and MYADG0200
change the signal from binary “1” to binary “0”. Then this is the signal MYADG100 and
AND gate 216- that receives MYADG0200
164 to output the output signal MYADG0001 to 2
Converts a binary “1” to a binary “0”. Section 21
Signal applied as input to bus response circuit 1
MYADG0001 generates the appropriate response. Section 211 FIG. 4e shows the bus response of the preferred embodiment of the invention.
FIG. 3 is a detailed diagram of the response circuit. These circuits are addressed to the controller
Operates to respond appropriately to memory instructions
do. The response circuit includes a data selection circuit 211-2 and a multiplex data selection circuit 211-2.
Number of inverter circuits 211-4 to 211-10
and associated pull-up resistors 211-14 to 21
1-20, multiple NAND gates 211-22~2
11-28, AND gate 211-30, a pair of
Exclusive OR circuits 211-32 and 211-34
and Noah connected as shown
Includes gates 211-36. The circuit 211-2 consists of four daughter boards or
The data generated by the corresponding board in
Receive data signals MDBP1L110 to MDBP4L110
connected like this. To explain in more detail, the four daughter boards
Once each is connected to the memory subsystem, the
The numbers MDBP1L000 to MDBP4L000 are binary “0”.
Ru. That is, inverter circuits 211-4 to 211
The input to each of -10 is grounded. Next, this converts MDBP1L110 to MDBP4L110 into 2
Set to decimal “1”. However, some daughter boards
This is the signal MDBP1L000~
Set the corresponding signal of MDBP4L000 to binary “1”
Make it. That is, the input from the daughterboard is
floating or floating
Either you haven't done it, or you haven't. That input is a pull
Inverter circuit 211-4 through up resistor
Apply voltage +V to one input of 211-10.
I can do it. The address that identifies the daughter board being addressed.
The response signals BSAD22110 and BSADX3110 are
is added to the selection input terminal of the data selection circuit 211-2.
Ru. Circuit 211-2 is the source of the output daughter board
By the signal BSAD22110 and BSADX3110 as
Daughter board signal DBNOTH000 generated by
Apply. The daughter board being addressed is the controller
When connected to DBNOTH000, the signal DBNOTH000 becomes binary “1”
be made into However, the addressed daughterboard
does not exist (e.g., a pair of daughterboards
), the signal DBNOTH000 is binary “0”
be put into a state. Signal DBNOTH000 is Nando game
added as one input to port 211-28.
Ru. Three other input signals to the NAND gate
OFFL1N000, HOFL1N000, QOFL1N000 are
operating controller memory offline
(i.e. all controller memory
Offline, 1/2 controller memory offline
and 1/4 controller memory offline) Signal OFFL1N000 is gate 211-22, 21
Generated by 1-30 and 211-34
Ru. Signal OFFLIN000 is set to 2 depending on the diagnostic command
When set to 0, this is shown in Figure 1.
All controller memory is offline so that
It indicates that Signal OFFLIN000 connects gates 211-30 and
and signals generated by 211-22.
Exclusive or of MODOFL010 and BSYEL6000
Generated by operations. Signal MODOFL010
Signal received from section 216
Combine OFFLN0010 and signal OFFLN1010
Generated by AND gate 211-30.
Signal BSYEL6000 is received from section 213.
bus signals BSYEL0110 and BSAD06010
and signals received from section 216
NAND gate 211-22 combining BS2021110
generated by. Therefore, gate 211
-34 signal MODOFL010 and
Exclusive or of BSYEL6000 is MEADID and
Diagnostic cycles started in response to configuration commands
Enables offline communication with the middle controller.
This allows you to go offline during other diagnostic cycles.
This prevents incorrect addressing of modules.
Ru. Signals HOFLIN000 and QOFLIN000 are
and the controller is in 1/2 offline operating mode.
and 1/4 off-in operating mode.
It shows. Some of the signals DBNOTH000~QOFLIN000
When set to binary “0”, NAND gate 211-2
8 sets the response signal RESPIN110 to binary "1".
This is an acknowledgment signal from Noah gate 211-36.
Prohibits setting ACKGEN010 to binary “1”.
Ru. Therefore, the controller is
Offline operation mode, 1/2 offline operation mode
mode and 1/4 offline operating mode (i.e.
Controller's entire memory section, 1/2 memory section, or
1/4 of the memory section is placed offline).
respond to memory requests while running
do not. Description of operation With respect to FIGS. 1 to 4e, the memory of the present invention
The system operation is shown in the blocks shown in Figures 7a to 10b.
are mentioned in specific relation to the diagram. Before explaining the operation example, please refer to Figure 5a and Figure 5a for reference.
and FIG. 5b. Figure 5a shows that the system of Figure 1 is in bank mode.
When activated, each memory read request
control as part of the write request.
Indicates the memory address format added to the
are doing. The four high order/most significant bit positions 0-3 are
Which of the memory controllers is being
to identify which quest should be processed
encoded. Address bit 4 is controller
Which half of the 256k of memory, i.e. the top half,
Which of the bottom half is being accessed?
used to select. Furthermore, address 4 and address bit 5 are
Which row of the RAM chip was addressed
is encoded to select. As mentioned above,
These bits are decoded and stored in a pair of memory
8 bits to the desired row of RAM chips in the tack
Row address strobe to latch row address
(RAS) signal. These address bits are
processed by the RAM chip and not supplied to the RAM chip.
stomach. Address bits 6-21 are addressed
22-bit memory location within the RAM chip
Specify the address of. As detailed above, these
16 address bits are multiplexed into 8 address inputs
Ads for blocks 210-26 and 210-46
The RAM chip in Figure 4c is transmitted via the response buffer circuit.
is applied to address input terminals A0-A7 of the The lowest address bits 22 and 23 are
Select whether the codes and bytes are addressed.
used to select. Figure 5b shows that the system of Figure 1 is interleaved.
Memory address when operating in bu mode
It shows the format. As you can see from the figure, the difference is in the most significant bit.
Places 0-2 and bit 18 should process the request.
The objective is to identify the controller. Address bit 3 is the controller memory
Select which half of 256k is being accessed
used to. Bits 3 and 4 are the RAM chips being addressed.
Select the row of the address and enter the address bits excluding bit 18.
Point 5-21 points to the addressed location.
Set. Figure 6d shows the part of the instruction that specifies the reconfiguration operation.
Addressed controller added as
Memo loaded into reconfiguration register 216-8 of
The rear format is shown. Address bits 19, 20 and 21 are executed.
Specify the type of operation to be performed. As can be seen from Figure 6d, the diagnosis code “100”
puts the addressed controller into reconfiguration mode.
Set to C. Before explaining this mode as above,
Other codes like “010” will cause the controller to
Set to EDAC test mode. its test mode
, the controller is the location being addressed.
Reads the contents of Yon and transfers the contents to bus 10.
do. On the other hand, in this mode, the controller is reading
The voltage generated by circuits 206-24 of FIG.
The generation of the bus error indication signal is prohibited, and the write operation is disabled.
Set the check bit signal to 0 during the cycle. A diagnosis code of “011” indicates that the controller
resets the EDAC mode. Depending on this code, the controller changes state and
and EDAC check bit indicators, and add
Reads the contents of the specified location and executes it.
The contents of the data are transferred to the bus 10. A diagnostic code of “000” is read identification register operation.
This code specifies the controller
is address bit 3-22 or address bit 4
−22 as specified by either
Read the contents of the addressed location
Do it like this. However, the controller is
in the identification register 206-22 instead of the contents in the identification register 206-22.
The contents are transferred to the bus 10 using the contents. In the same way, use the code “001” to control
Laura is the content of the addressed location
The contents of status register 206-20 instead of
Transfer to 10. Now, if we consider Figure 6d in detail, the bus address
The res bit is the response of the controller during reconfiguration mode.
coded to specify the address to be answered.
You can see that Bus address bits 12 and 13 are control
controller (i.e. all controllers, controllers)
half of the controller or 1/4 of the controller)
is offline.
will be coded. Bus address bits 15 and 1
6 to specify the type of controller reconfiguration
is encoded in As can be seen from Figure 6d, bit 15 is binary.
When “1”, this means that the controller
– Specifies that both boards in a pair should be replaced.
do. When bit 16 is a binary “1”, this means that
controller is connected to a sector in a pair of daughter boards.
section (i.e. from section 207-2)
the line specified by the decode signal).
Specify that the Finally, bit 17 indicates that the controller is installed.
When it should operate in taleave mode of operation,
Coded to specify. Figures 6a and 6c show the state according to the invention.
status register 206-20 and identification register 20
6-22 shows the format of the contents. As can be seen in Figure 6a, the 16-bit register
is the decoding from register 207-12 in Figure 4b.
Door address bit (i.e. LSADX3010
and LSADX4010) and single bit error isolation
Syndrome bit S0~ that allows RAM chips to
Store the combination of S5. Errors and errors using syndrome bits
Reference for more information about detection
Documents include US Pat. No. 4,072,853. As mentioned above, status register 206-20 is
A syndrome signal representing a new single bit error.
Store the number. Uncorrectable errors (i.e. double bit errors)
error) occurs, the level of block 206-24 is
The output generation circuit uses the contents of the status register 206-20.
Generates a signal to fix the As can be seen in FIG. 6c, the identification register 20
6-22 is the controller's information in addition to other status information.
Stores indications of reconfiguration mode and addressing mode.
pay. This will be explained in more detail. Bit position 8 is EDAC
Stores the state of mode flip-flop 216-4.
Ru. Bit positions 9 and 10 are for soft errors and bugs.
Stores an indication of a sparsity error. Soft error conditions occur at normal memory speed or higher.
Directs the results of performing memory rewrite operations at high speeds
do. For the purposes of this invention, such an indicia
Additionally specifies memory readiness. Filed and filed on July 25, 1980 as a co-pending application.
Application No. 172486 ``Effects included in the memory system''
methods and methods for testing and verifying the operation of controller controllers.
There is a device for Bit position 11 is in section 211 of Figure 4e.
Status of the signal MDBP4L110 generated by the circuit
Store. Bit position 12 is the reconfiguration mode flip-flop.
Stores the state of 216-10. Bit positions 13 to 15 are 1/4 board replacement, 1/2 board
Like exchange and interleave mode stage status
A certain stage of the stages of the reconfiguration register 216-6
Store the sign. In accordance with the teachings of this invention, the memory system of FIG.
The system has addressing mode of operation and error time.
Adjacent apps as a function of the drop and its location.
to provide addressable address space
Can be reconfigured. In each example, each memory controller in FIG.
is 2 pairs with 64KRAM chip as shown in Figure 6b.
daughter board. That is, each controller is addressable
512K words of memory (i.e. 524, 288 words)
have The memory system is in interleaved address mode.
When operated in the sixth mode, each pair of controllers
b The addresses arranged as shown in figure
have Now, the memo shown in Figures 7a and 7b
Types of reconfiguration are considered. For this reconfiguration, the system
It is operated in the mode. Before issuing the reconfiguration command, the central processing unit 40
is the first to report the detection of an uncorrectable error condition.
Executes various diagnostic operations in the controller shown in the figure.
do. Such an operation is performed by the normal state register 206-2.
Includes generation of a diagnostic command that specifies a read of 0.
nothing. Controller according to controller decode
The decoder circuit 216-2 receives the signal READST000 as 2
Set the binary value to “0” and set the signal READST010 to binary “1”.
do. These are condition registers 206-20 and lines
Read status information to bus 10 via MUXD00-15.
Data output multiplexer 206-1 for outputting
6 and 206-18. From the status information in Figure 6a, the defective memory
The position of the case can be determined. After this is done, this is the defective note
Verify that it is the only location in
It is desirable to perform further test operations to
stomach. Such tests for the purposes of this invention are
and which form part of this invention.
not present. Additionally, as a reference for memory testing,
Filed on July 25, 1980, Application No. 172486 “Memory
Test the operation of error control devices included in the system.
"Methods and equipment for testing and verifying"
Ru. Following such a test, the central processing unit 40
Word location 000000 in Figure 6b is defective.
As shown in Figure 7a,
Make sure that the memory system part in Figure 1 is not used.
I will do it. The reconstruction device of the invention is shown in FIG. 7b.
Locate the defect at the top of the controller memory.
You can put Shion on it. This means that the controller memory is reconfigured that way.
A diagnostic memory read command that specifies what is to be done.
By having a processing device 40 that generates a
can be achieved. Frame loaded into reconfiguration register 216-8
The command address bits are coded as follows:
Ru. Bit 8-11=0000 Bits 12-13=00 Bit 15=1 Bit 16=1 Bit 17 = 0 Bit 19-21=100 The controller operates in bank address mode.
address bits 0-3 indicate the defective location.
Specify the address of the controller that has the
coded for. All 0 addresses (i.e., the control in Figure 1)
controller to which the roller 200-1) is assigned
If the controller has defective memory, other address bits may
All (i.e. 0-7) are binary “0”
It is. Processor 40 sends a diagnostic memory command to bus 10.
When applying, it also connects the lines BSYELO and
Set BSMREF to binary “1”. Additionally, the lines BSWRIT and BSDBPL are
The controller 200-1 is the defective module shown in FIG.
Read operation cycle to read 1 word from file A
remains as binary “0” indicating that it should be executed.
It is. The comparator circuit 216-162 in FIG. 4d is the address
Specified by bits 0-3 and switches S1-S4
Detects true comparisons between controller addresses
Then, the signal MYADG0200 is set to binary "0". This causes the signal MYADG0001 to become a binary "0". This binary “0” causes section 211 to
The bus response circuit is a result of the generation of signal MYACKR010
generate an appropriate bus response to the resulting processing device 40;
be able to. Signal MYACKR010 has the timing shown in Figure 4a.
Circuit 204 connects address bits 4-22 of Figure 6a.
from the memory location specified by
A memory operation that generates a series of signals to read the code.
Start the production cycle. Simply put, a memory operation cycle consists of the following
Including Kens. The signal MYACKR010 causes circuit 204 to
Controller Mori busy signal MEMBUZ010
#0 means to start a memory operation cycle
Set to binary “1” to indicate. Next, the bus address signal BSAD06210~
BSAD21210 is the row address from bus 10 to Figure 4b.
address registers 207-40 and column address registers
data 207-42. Signal MEMBUZ010 is the signal in Figure 4b
Switch ADDSTR000 to binary “0”. this is
Most Significant Address Bit BSAD22110 and Chip
Select address signal BSADX3110 and
Load BSADX4110 into register 207-12
Ru. One cycle is determined by the timing signal from circuit 204.
Cushion 204 controls line BSREQT.
controller #0 accepts memory reconfiguration commands.
Switch to binary “0” as shown. Controller #0 has the highest priority
section 211 is the signal
Switch MYDCNN010 to binary “1”. This belief
The signal is inverted by circuit 213 and connected to the bus line
Added to BSDCNN. As can be seen from Figure 4d, the signal CLOCK1010
is set to binary “1”, the reconfiguration register 216
–8 is loaded with command address bits 8-17.
This signal allows the reconfiguration
Mode flip-flop 216-10 is binary
Switched to “1”. As mentioned above, to explain in more detail, the line
BSYELO is a menu added to line BSAD00−23.
The Mori address is said to include a diagnostic command code.
A signal is sent to controller 200-1. sexy
Binary “1” signal stored in pin 208
BSYELO10 sets signal LSYELO010 to binary “1”
do. This signal along with signal LSWRIT010 is shown in Figure 4d.
Enable decoder circuit 216-2. In response to the code “100”, the decoder circuit 216
-2 sets the signal RECONF000 to binary "0". child
As a result, the timing signal CLOCK1010 is binary
When switched to “1”, the reconfiguration mode flip-flop
Push 216-10 is switched to a binary "1". During the memory operation cycle, the stored chip select
The address signal is sent to the decoder circuit 207-20.
It is then decoded. As a result, the decoding circuit
207-20 converts one of the decoded signals to binary “0”
Make it. RAS time (i.e. signal MCASAD110 is 2
(when the digit is “0”), row address register 2
The row address signal from 07-40 is connected to device 210-
Loaded into rows of RAM chips 20 and 210-40.
is coded. Therefore, column address register 207-42
and column address from multiplexer circuit 207-56.
The address signal is CAS (i.e. signal MCASAD010
210-2 switches to binary “1”)
Loaded into 0 and 210-40 RAM chips
It will be done. Memory specified by row and column address
The contents of the location are accessed and register 2
06-8 and 206-10. The single word requested is
When the cycle is completed, it is added to the bus 10. Reconfiguration register by signal MCONCK010
Stage 216-8 is address bit BSADS-17.
loaded. However, flip-flop 216-10
Reconfiguration is not performed until the
It won't happen. Next, by such switching, multi-
Plexer circuit 216-12 is the controller address
i.e. signals RCONF0010 to RCONF3010
Conditions are attached for use as such. At this time, the signals HALFBS010 and
Both QARTBS010 are binary "1". death
Therefore, exclusive OR circuits 216-50 and 2
Address bit signals generated by 16-52
The signs of numbers BSADX3110 and BSADX4110 are reversed.
be done. That is, each memory request
The states of select bits 4 and 5 are automatically complemented.
It will be done. What is the complementation of address decoding circuit 20?
The output signal when decoded by 7-20
Logical output that generates DRAST0010 to DRAST3010
It is to invert the dar. This is the daughter board pair (A/C) (,)
and B/C(,) respond to signal HALFBS010.
This means that it will be exchanged as soon as possible. Furthermore, as can be seen from Figure 7b, each daughter
– The upper and lower halves of the board pair are signal
exchanged according to QARTS010 (i.e.
and daughter in A/C vs. board
board vs. in B/D) Figures 8a to 8e are the memory system of Figure 1.
How to reinstall in case of defective controller
Here are some other examples showing what can be configured:
There is. As mentioned above, the system of Figure 1 is shown in Figure 8a.
Interleave module vs. as shown
Contains 16 memory subsystems located in Each pair is organized as shown in Figure 6b.
Contains 2MB. All controllers assigned address 0010
Defective software that disables controller memory
Including Mori location. If it remains in this state, the control
controller operates in interleaved address mode
Therefore, the central processing unit 40 has address 0010 (#2)
and the controller assigned 0011 (#3)
around the address space provided by
You have to make a pool. Through the use of a series of reconfiguration commands, Fig.
memory system provides contiguous address space
To do this, as shown in Figures 8b-8d.
The sea urchin is reconstructed. By the first reconfiguration command, the binary address
The controller assigned 0010 (#2) is the same
taken offline at the same address. The reconfiguration command address bits are coded as follows:
will be coded. Bit 8-11=0010 Bit 12-13=11 Bit 15 = 0 Bit 16 = 0 Bit 17=1 Bit 19-21=100 where address bits 0-2 and 18 are address bits 0-2 and 18
Coded to specify response 0010 (#2)
Ru. Additionally, BSYELO, BSMREF and
The BSWRIT line is conditioned in the same way as above.
It will be done. Controller #2 reconfigures in response to the reconfiguration command.
Configuration mode flip-flop 216-10 binary
Switch to “1” and register address bits 8-21.
216-8. Offline signal OFFLN0010 and
Since both OFFLN1010 are binary “1”,
This is because the bus response circuit in Figure 4e is shown in Figure 8b.
towards controller address #2 as shown.
prevent responding to memory requests that are
Ru. That is, the AND gate 211-30 receives the signal
Set MODOFL010 to binary “1” state. Signal BSYEL6000 corresponds to regular memory commands.
Since it is usually binary “0”, exclusive or game
The output sets the signal OFFLIN000 to binary “0”. Next
As a result, Nand Gate 211-28
Since the signal RESPIN110 is set to binary “1”, Noah
Gate 211-36 sends an acknowledgment ACKGEN010.
Prohibits setting to binary “1”. Next, the processing device 40 replaces controller #2.
The controller with address 1110 (#14)
generates a second reconfiguration command to reconfigure the
Ru. The reconfiguration command address bits are as follows:
coded. Bit 8-11=0010 Bits 12-13=00 Bit 15 = 0 Bit 16 = 0 Bit 17=1 Bit 19-21=100 In this example, address bits 0-2 and
18 specifies address 1110 (#14)
is encoded in Again, BSYELO, BSMREF
and BSWRIT line conditioned in the same way as above.
can be added. When decoding a reconfiguration command, the control
Controller #14 is its reconfiguration mode flip-flop 2
Switch 16-10 to binary “1” and set the address bit.
8-21 into register 216-8.
Therefore, controller 14 then registers register 2
Controller address value of 16-8 followed by reception
The condition is set to compare the memory requests made
Can be attached. Therefore, next controller #14
functions as controller #2. Additionally, controller #14 is shown in Figure 8c.
interleave with controller #3 so that
conditioned to operate in address mode.
Ru. Also provided by controller #14
Figure 8c shows that the memory is currently not operating.
I understand. Therefore, in order to select the controller 15,
Furthermore, as shown in Figure 8d, the control
Memory provided by rollers #12 and #13
controller to provide contiguous memory across
A reconfiguration command is generated to reconfigure La #15.
Ru. The reconfiguration command address bits are as follows:
Become. Bit 8-11=1110 Bits 12-13=00 Bit 15 = 0 Bit 16 = 0 Bit 17 = 0 Bit 19-21=100 Address bits 0-2 and 18 are controller
Code to specify address 1111 (#15)
Controller #15 depending on the command being coded
is its reconfiguration mode flip-flop 216-1
Switch 0 to binary “1” and set the command address bit.
load into reconfiguration register 216-8. figure
Once reconfigured as shown, the
Controller #15 has controller address value 1110
(#14) and the memory request received subsequently.
and operates in bank address mode. i.e. controller #15 is making memory requests
Controller address bits 0-3 and controller address
Compare the value 1110 (#4), thereby determining the 8th d
Provided by controllers #12 and #13 in the diagram
address with a value 1 greater than the maximum address value
Provide contiguous memory starting with address. From the above, we can see how the defective controller
Addresses that are taken “offline” and have no neighboring failures
to provide addressable memory space.
Is it possible to replace the controller with another controller?
Ru. From the above example, the failure occurring in controller #2
cannot use the lower two daughterboard pairs.
Do it like this. Therefore, the memory system is
Reconfigured as shown in Figure 8c. From this point on, the system is shown in Figure 8e.
be reconfigured so that This was previously occupied by controller #14
Offline controller #2 to the position where it was
Including moving and 1/2 board replacement. Therefore, the processing device 40 issues the reconfiguration command.
put out. Command address bits for reconfiguration commands
is coded as follows. Bit 8-11=1110 Bit 12-13=10 Bit 15=1 Bit 16 = 0 Bit 17=1 Bit 19-21=100 The command is directed to controller #2. Therefore, command address bits 0-2 and
and 18 have the value 0010. the remaining address space
t is a binary "0". Controller #2 is
Since it is “offline”, the line BSYELO is offline.
Set to binary “1” along with the address bit BSAD06.
It will be done. At the same time, bus address bit BSAD26 and
BSAD21 is set to binary "0". Again, the line
BSMREF is set to binary "1". As can be seen from Figure 4e, controller #2
is in an “offline” state (i.e., the signal
OFFLN0010 and OFFLN010 are binary “1”.
), so the AND gate 211-30 is reliable.
Set the number MODOFL010 to binary “1”. By signal BSYEL0110 and signal BSAD06010
Therefore, NAND gate 211-22 is a signal
Set BSYEL6000 to binary “0”. Therefore, exclusive or gate 211-34 is
Set the signal OFFLIN000 to binary “1”. Both signals BSAD03110 and BSAD04110
Since it is binary “0”, NAND gate 211-2
4 and 211-26 are signals HOFLIN000 and
Set QOFLIN000 to binary “1”. At this time, the signal DBNOTH000 is binary “1”.
(i.e. all daughter boards are
attached) Therefore, the NAND gates 211-28 are
RESPIN110 is set to binary “0”. Circuit 216 of FIG. 4d in response to a reconfiguration command.
-160 sets the signal MYADG0100 to binary “0”
Ru. With this, the AND gate 216-164 becomes
Set signal MYADG0001 to binary “0”. signal
Noage according to RESPIN110 and MYADG0001
Other inputs to ports 211-36 are acknowledge signals.
Set ACKGEN010 to binary “1”. signal
ACKGEN010 responds to memory reconfiguration commands
Generates memory acknowledge signal MYACKR010.
Conditions for the bus response unit 211 are set. This means that the timing circuit 204 of FIG.
address bits 3-22 of Figure 5b in the manner described above.
The memory location of controller #2 specified by
sequence of instructions to read a single word from the
During the memory operation cycle that generates the
Start cycle. New Reconfiguration Stored in Register 216-8
The information was originally provided by controller #14.
Interleaved addresses operating in the address space
Set controller #2 to response specification mode, and
- Replace the board pair and set the offline command bits.
Reset 1. That is, register 216-
Reconfiguration signal RCONF0010~ stored in 8
RCONF3010 now has controller #2 as 8th e
For controller #15 as shown in the figure
Ru. The signal HALFBS101 in register 216-8
The replacement of the daughter board pair as specified in
The memory function is shown on the bottom as shown in Figure 8e.
Place half. Reset signal OFFLN1010 to binary “0”
by bringing the top half of memory online,
Make it operational. The signal OFFLN0010 is still binary “1”.
leaves the top half of memory offline and works
make it impossible. From the above, the system in Figure 1 uses the reconfiguration command
can be reconfigured again by the processing device 40 that emits
I understand. All controllers must be original
If it is desired to return to the initial state, this
has a processing unit 40 that issues default instructions.
It is done by. In the default command, the bus address
7 plus lines BSYELO and BSMREF
are all set to binary “1”, and the bus address
Bits 20 and 21 are set to binary "0". As can be seen from Figure 4d, the signal BSAD07110
is binary “1”, then NAND gate 216-
30 sets the signal RCONCT110 to binary "0".
This allows reconfiguration mode within each controller.
The flip-flop is set to 2 according to the signal DCNR60110.
Switched to binary "0" state. This is switch 216-6 in each controller.
Control is returned to the pair. Therefore, each controller then switches S
1-controller address specified by S4
respond to messages. Furthermore, the power on signal PWONLL010 is binary
When it is “0”, the control is
Return to Group Chi. Figures 9a to 9c show two pairs of daughter boards.
Different controller options for controllers including
The fly memory configuration is shown. As shown in Figure 9a, all controls
RAM memory board is taken offline. On the other hand,
In this state, the controller is connected to the processing device 40.
and respond to offline commands. Figures 9b and 9c are controller memory
half of the board and controller memory board
Indicates that 1/4 is taken offline. However, the controller
Offline from the processing device 40 commanded to the input section
does not respond to commands. In other words, the memory frame
command is commanded to half of offline memory,
The NAND gates 211-24 in FIG. 4e are signal
Set HOFLIN000 to binary “0”. This causes the NOR gate 211-36 to signal
By setting ACKGEN010 to binary “0”
Prevent responding to memory requests. In the same way, the memory command
When commanded to 1/4 of Li, NAND gate 211-
26 disables signal QOFLIN000 from controller response.
Set to binary “0” to stop. Figures 10a and 10b show a pair of daughters
Different controls for controllers including boards
The roller offline memory configuration is shown. As you can see from the drawing, a pair of daughter boards
The controller including the entire memory section and 1/4
only responds to commands that reconfigure it. That is, the offline bit is connected to a pair of dows.
half of the controller's memory, including the
Ignore commands that specify to go offline
be done. To explain in more detail, Nand Gate 211
-26 uses signal HOFLIN000 as bus response signal
Set to binary “0” to prohibit generation of ACKGEN010.
Ru. From the above, it is clear how the device of this invention can be used offline.
Communication with the controller memory section is reconfigured to the state
I understand that you allow faith. Memory systems that include many memory controllers
The method by which the system is reconfigured by the device of this invention is as follows.
As mentioned above. Controller specified by invention of reconfigurable device
Operates in all modes less than
It is clear to those skilled in the art that it can be reconfigured to
That's it. For example, in some memory systems, this
The need to have a reconfiguration device that provides for
offline communication is not required by excluding
stomach. In accordance with the provisions, the best mode of the invention has been described.
However, some changes are listed in the appendix.
departing from the spirit of this invention as stated in the
In many cases, this invention was made without
Some features are useful without corresponding use of other features.
Used to stand.

[Brief explanation of the drawing]

FIG. 1 is a block diagram from a system including the memory system of the present invention. FIG. 2 is a detailed diagram of the lines of system bus 10 connecting each of the memory subsystems of FIG. FIG. 3 is a block diagram of memory subsystem 20-1 of FIG. 4a-4e are detailed views of different portions of the memory subsystem 20-1 of FIG. 3. FIG. FIG. 5a is a diagram of the address format applied to the controller of FIG. 1 when the system is operated in banked mode. FIG. 5b is a diagram of the address format applied to the controller of FIG. 1 when the system is operated in interleaved mode. FIG. 6a is a format diagram of the status word register contents applied by the controller to bus 10 in response to a read status word diagnostic command.
FIG. 6b is a memory organization diagram of the controller pair of FIG. 1. FIG. 6c shows the identification register 20 of FIG.
6-20 format diagram. FIG. 6d is a format diagram of a reconfiguration register included in the reconfiguration section of FIG. Figures 7a and 7b are diagrams showing reconfiguration of the controller memory;
The figure shows the defect location in the controller memory, and FIG. 7b shows the defect location at the top of the controller memory. Figure 8a~
FIG. 8e shows another example of how the memory system of FIG. 1 can be reconfigured in the case of a defective controller. 9th
Figures 9a-9c illustrate different controller offline memory configurations for a controller including two pairs of daughter boards, with Figure 9a showing all controller memory boards taken offline; Figure 9b shows half of the controller memory board being taken offline;
FIG. 9c shows that 1/4 of the controller memory board is taken offline. Chapter 10a
Figures 10b and 10b illustrate different controller offline memory configurations for a controller that includes a pair of daughter boards, with Figure 10a being responsive only to commands that reconfigure all of the memory sections; Figure 10b shows 1/1 of the memory section.
FIG. 10...Bus, 20-1 to 20-n...Memory subsystem, 40...Central processing unit, 200-
1-200-n...Memory controller, 211
...Memory initialization section, 211...Bus control circuit section, 215...Queue control section, 216...
Reconfiguration control unit.

Claims (1)

[Scope of Claims] 1. A data processing system comprising a data processing device and a memory system including a plurality of addressable memory controllers, wherein each controller for controlling the operation of the memory has a corresponding number of addressable memory controllers in response to a memory command. a plurality of memory modules provided on a daughter board, the controller being commonly connected to a bus to receive the memory commands and data from the processing unit, each memory command being In a data processing system, each memory controller includes an address portion consisting of a plurality of address bits coded to specify which of the controllers is to perform the operation specified by the command; a reconfiguration control section connected to reconfigure the controller in the system in response to memory commands, the section comprising: an instruction signal defining a type of controller memory reconfiguration in addition to a controller address signal; register means for storing an address of the controller within the memory system; selectable switch means coupled to the register means and the switch means for representing the address of the controller during a reconfiguration mode of operation; output selection means for generating a signal, responsive to a predetermined type of memory command coupled to said bus and said output selection means, specifying a reconfiguration mode of operation for a controller specified by an address portion of said command; is switched to a predetermined state, and when in the predetermined state, the output selection means causes the controller to receive an address signal from the register means as the signal representing the address of the controller instead of the address from the switch means. mode control means for adjusting the memory controller to add contiguous addressable memory spaces to enable reconfiguration of each of the plurality of memory controllers in the memory system to create contiguous addressable memory spaces; Characteristic data processing system. 2. The system of claim 1, wherein each predetermined type of memory command includes a diagnostic code defining a reconfiguration bit pattern coded to include the reconfiguration mode of operation and the instruction; The reconfiguration section: has decoder circuit means coupled to said bus, said mode control means and said register means;
The decoder circuit means outputs an output for switching the mode control means to the predetermined state and for enabling the register means of the controller specified by the address field loaded with the reconfiguration bit pattern. A data processing system operative in response to said diagnostic code to generate a signal. 3. The system of claim 2, wherein each said controller further: is coupled to said output selection means and said bus;
When the mode control means is in the predetermined state, detecting a comparison match between the signal representing the address from the register means and the plurality of address bits of the memory command applied to the bus, and generating an output comparison signal. and address comparison means coupled to said address comparison means and said bus such that said command is received from said register means by said predetermined type of command previously applied to said bus. bus response means conditioned by said output comparison signal to generate an acknowledge signal on said bus indicating acceptance by said controller reconfigured to be responsive to said address; A data processing system comprising; 4. The system of claim 3, wherein each of said controllers is coupled to said plurality of memory module units for generating signals for accessing different sections of said set of memory daughter boards. address means, said register means comprising a plurality of register stages, a plurality of register stages storing predetermined bits of said reconfiguration bit pattern coded to specify a type of daughter board reconfiguration; The reconfiguration section is: coupled to the plurality of stages, the addressing means and the bus for receiving predetermined address bits of the address portion of each memory command coded to specify access of the different sections; and logic means for transmitting a signal to the addressing means for accessing every other section of the set of memory daughter boards not specified by the encoding of the predetermined address bits. A data processing system characterized in that the data processing system is conditioned by a predetermined state of the predetermined address bits to change the encoding of the predetermined address bits for generation. 5. The system of claim 4, wherein a first stage of the plurality of stages stores a first predetermined bit of the reconstructed bit pattern, and the first predetermined bit is connected to the daughter board pair. the daughter board pair specified by the state of the first bit of the first predetermined address bit; the first predetermined bits to complement the state of the first one of the predetermined address bits for conditioning the addressing means to generate a signal for accessing a different pair of daughter boards; A data processing system characterized in that the data processing system is conditioned by a first state of. 6 The first state of the first predetermined bit is 2.
corresponding to a binary "1" state, said logic means select a first one for complementing said state of said first one of said predetermined address bits in response to said binary "1" state.
6. The data processing system according to claim 5, further comprising an exclusive OR circuit. 7. a second stage of said plurality of stages stores a second predetermined bit of said reconstructed bit pattern;
The second predetermined bit is coded to specify whether half of the daughter board pair is to be replaced or not, and the logic means is configured to determine the second of the predetermined address bits. of said second of said predetermined address bits for conditioning said addressing means to generate a signal for accessing said half of said daughter board pair different from the half designated by said state; 6. A data processing system as claimed in claim 5, characterized in that the second predetermined bit is conditioned by the first state to take the complement of the state. 8 The first state of the second predetermined bit is 2.
Corresponding to the binary "1" state, said logic means operate a second exclusive-OR circuit for complementing said state of said second bit of said predetermined address bit in response to said binary "1" state. 8. A data processing system according to claim 7, characterized in that: 9. The system of claim 3, wherein said register means has a plurality of stages, each stage having said register means coded to specify the mode of operation of a different section of said memory daughter board. comprising a plurality of stages for storing a plurality of bits of a configuration bit pattern, said bus responsive means: coupled to said plurality of stages and said bus for receiving therefrom certain bits of said address bits of said address portion; input logic means for combining said plurality of bits of said reconfiguration bit pattern to generate a signal indicating that a certain bit of an address bit and a section of said memory daughter board are offline; and and output gating means coupled to the input logic means and the bus for generating the acknowledge signal in accordance with a condition. 10. The system of claim 9, wherein the input logic means: is coupled to the multiple stages to generate a first output signal indicating when all of the controller daughter board memories are offline. first gating means coupled to said bus for receiving a signal corresponding to a first predetermined bit of said certain address bit specified by a diagnostic type of a memory command; The second to indicate that it is for communication.
second gating means for generating an output signal; and said acknowledgment coupled to said first and said second gating means and said output gating means to permit offline communication with said offline controller during a diagnostic operating cycle. a third gating means for logically combining said first and said second output signals to generate a third signal for enabling generation of a signal; . 11. The system of claim 10, wherein the input logic means further includes fourth gate means coupled to the output gate means;
The fourth gating means has a pair of input terminals, a first input terminal of which is connected to one of the plurality of stages for receiving a first signal indicating when at least half of the controller memory is offline. 1
and a second input terminal thereof for receiving a second signal corresponding to a second predetermined bit of the address bits of the address portion indicating that the half of the controller memory is to be addressed. logic first and second signals coupled to said bus to generate an output signal for inhibiting said output gating means from generating said acknowledge signal preventing offline communication with said offline controller half; A data processing system characterized by a combination of 12. The system according to claim 9, wherein the input logic means further includes: a pair of input terminals and an output terminal, and a first terminal of the pair of input terminals is connected to the predetermined board of the daughter board. is coupled to a predetermined board of the daughter board for receiving a third signal indicating when one half of the controller memory is being addressed; The third address bit of the address portion indicates that
fifth gating means coupled to said bus for receiving a fourth signal corresponding to a predetermined bit of the output gating means; and a plurality of input terminals and an output terminal connected to said output gating means. , a first terminal of the input terminals is connected to the output terminal of the fifth gating means, and a second terminal receives a fifth signal indicating that one quarter of the controller memory is offline. a third of said input terminals is coupled to another stage of said plurality of stages for receiving a third of said certain address bits for indicating that one quarter of said controller memory is being addressed; said output gate means is coupled to said bus for receiving a predetermined bit and said output gate means for generating an output signal for inhibiting generation of said acknowledge signal preventing off-line communication with said one quarter of said controller memory; A data processing system comprising: sixth gate means for logically combining signals applied to the input terminals. 13. The data according to claim 10, wherein the first gate means includes an AND gate, the second gate means includes a NAND gate, and the third gate means includes an exclusive OR gate. processing system. 14. The data processing system according to claim 11, wherein the fourth gate means includes a NAND gate. 15. The data processing system according to claim 12, wherein the fifth gate means includes an exclusive-OR gate, and the sixth gate means includes a NAND gate. 16. The system of claim 9, wherein the input logic means includes a pair of selection input means, a plurality of data input terminals whose number corresponds to the maximum number of daughter boards that can be attached to each memory controller, and the a multiplexer circuit having one output terminal coupled to output gating means, said pair of select input terminals for selecting a predetermined bit of said address bits of said address portion specifying that one of said daughter boards is being addressed; each of the data input terminals is coupled to a different one of the maximum number of daughterboards to receive a signal indicating whether a different daughterboard is installed; The multiplexer circuit connects the daughter board selected by the address bits to inhibit generation of a positive confirmation signal indicating that the controller is not fully populated when the daughter board is not installed. to supply the signal from to the output terminal;
A data processing system that operates in response to said predetermined bit of said address bit. 17. The system of claim 4, wherein the register means comprises a storage device for storing one of the instruction signals received from the bus and applied as an input to the storage device. the instruction signal is for defining an addressing mode of operation for the controller;
Furthermore, the storage device is connected to receive a power-on signal for switching the storage device to a first state corresponding to a first addressing mode when the controller is powered on for operation. a plurality of output terminals coupled to the logic means and the address selection means; and a plurality of sets of input terminals, a first set of which includes: a plurality of output terminals coupled to the logic means and the address selection means; coupled to the bus for receiving a first plurality of address bits coded to specify a controller address when the system is operated in the first addressing mode of operation; , and the second
the set of address bits for receiving a second plurality of address bits coded to specify the controller address when the system is operated in the second addressing mode of operation; where it is connected to the bus,
a selection circuit having: a plurality of sets of input terminals; and a control input coupled to the storage device for receiving a signal representative of a state of the storage device; conditions the selection means to apply the first plurality of address bits to the output terminal, which, when in the first state, conditions the addressing means to operate in the first addressing mode; said second plurality of signals on said output terminals for conditioning said addressing means to operate in said second addressing mode when switching to said second state in response to said predetermined type of memory instruction; A data processing system characterized in that said selection circuit is conditioned to apply address bits of. 18. the first state corresponds to a binary "1" state, the first addressing mode corresponds to an interleaved mode of operation, and the second state corresponds to a binary "0"state; 18. The data processing system of claim 17, wherein the second addressing mode corresponds to a bank operation mode. 19. The system according to claim 17, wherein the address comparison means includes a plurality of comparison circuits corresponding in number to the addressing operation modes, and each of the comparison circuits corresponds to the first and second input terminals. a first set of input terminals of a first comparator circuit having a plurality of said address bits used to specify a controller address when said system is operated in said first mode of operation; coupled to the bus for receiving the signal from the storage device, a second set of input terminals of the first comparator circuit being coupled to the output selection means and a voltage representing a binary "1"; the first comparator circuit detects a comparison match between the plurality of address bits and the controller address signal from the output selection means when the controller is operated in the first addressing mode of operation; A data processing system operable to generate the output comparison signal. 20. The system of claim 19, wherein the first set of input terminals of a second comparator circuit are used to specify a controller address when the system is operated in the second mode of operation. a second set of input terminals of the second comparator circuit are coupled to the bus for receiving a plurality of the address bits and a signal from the storage device; data, characterized in that when operated in an operational mode, the data is operated to generate the output comparison signal upon detecting a comparison match between the plurality of address bits and the controller address signal from the output selection means. processing system. 21 said mode control means includes bistable storage means including a first input terminal coupled to receive said output signal from said decoding circuit means, said bistable storage means causing said controller to be in a reconfiguration mode; to condition it to operate in
3. The data processing system of claim 2, wherein said data processing system is operated in response to said output signal for switching to a binary "1" state. 22. The system of claim 21, wherein the reconfiguration section of each controller further includes logic circuit means for generating a reconfiguration reset signal, and wherein the logic circuit means is configured such that each of the plurality of controllers coupled to said bus for receiving a diagnostic command for specifying when to be reset and a signal representing a predetermined bit of said address bits to reset said binary from said binary "1" state to a binary "0" state. operated in response to a predetermined state of said predetermined bits of said address bits of a diagnostic memory command to switch the stable storage means;
A data processing system, wherein each controller is thereby brought back under control of said manually selectable switch means. 23. The system of claim 17, wherein the addressing means is coupled to the plurality of memory module units and to the logic means, and wherein a predetermined one of the output terminals of the selection circuit is coupled to each of the plurality of memory module units and to the logic means. coupled to apply predetermined address bits of said first and second plurality of address bits to said logic means during first and second addressing modes, said logic means for accessing during said reconfiguration mode of operation. applying said predetermined address bits to said decoder circuit means which are changed in accordance with said state of said predetermined bits to condition said decoder circuit means to generate a signal to select a designated section of said memory module unit; A data processing system characterized by: 24 In a memory system having multiple addressable memory controllers, each controller includes a plurality of memory modules contained in a corresponding number of daughter boards for controlling memory operations, and a bus for receiving memory commands and data. each memory command includes a multi-bit address portion having a plurality of address bits encoded to specify which of the controllers is to perform the operation specified by the command; and said address portion of each given type of command includes a reconfiguration bit coded to specify a number of different reconfiguration operating modes, and each memory controller: reconfiguration control means including register storage means for; manual selection switch means for generating a first set of signals specifying the address of said controller within said memory system during normal operation; said selection switch means, said coupled to a reconfiguration register storage means and a bus for generating an output comparison signal upon detecting a comparison match between the first set of signals and the plurality of address bits of the predetermined type of memory command during the normal operation; and response means coupled to said address comparison means, said reconstruction means and said bus, said response means operable to register said reconstructed bit pattern to said reconstructed storage means. said output comparison signal for generating an acknowledge signal for causing the output to be stored;
in response to a subsequently received memory command, the output comparison signal and the acknowledgment signal for operating the controller in accordance with the encoding of the different bits to be reconfigured according to a predetermined type of the command; 2. A memory system according to claim 1, further comprising response means conditioned by different bits in said bit pattern for conditioning said address comparison means and response means to occur. 25. The memory system of claim 24, wherein the reconfiguration control means further comprises: a plurality of the reconfiguration bit patterns representing addresses of the controller to be reconfigured by a predetermined type of the command; output selection means coupled to said register storage means for receiving a signal corresponding to said first set of signals and said output signal; said output selection means coupled to said switch means for receiving said first set of signals and said output signal; said output selection means, said address comparison means, said reconfiguration means and said bus, said response means being operated to provide said reconfiguration means stored in said reconfiguration storage means; a configuration bit pattern and said address comparison means to be conditioned by said output comparison signal to generate an acknowledge signal for enabling different bits in said bit pattern; The output comparison and the A system comprising: generating an acknowledgment signal; and; and bistable mode control means coupled to said bus and said output selection means, said bistable mode control means responsive to said predetermined type of memory command specifying a reconfiguration mode of operation for said controller. is switched to a first state in response to said first state.
the address comparing means for comparing with the plurality of address bits of each successively received memory command configuring the memory controller in the memory system for providing contiguous addressable memory spaces; and said bistable mode control means for conditioning said output selection means to apply an address. 26. The memory system of claim 25, wherein each predetermined type of memory command includes a diagnostic code specifying the reconfiguration mode of operation, and the reconfiguration control means further also: the bus, the bistable mode. decoding circuit means coupled to the control means and the register storage means, the decoding circuit means for switching the mode control means to the first state and for decoding the memory command loaded with the reconfigured bit pattern; A memory system operable in response to said diagnostic code to generate an output signal for activating said register storage means of a controller addressed by said respective predetermined type. 27. The memory system of claim 26, wherein each of the controllers is further coupled to the plurality of memory modules for generating signals for accessing different sections of the pair of memory daughter boards. and wherein the register storage means includes a plurality of register stages for storing predetermined bits of the reconfiguration bit pattern coded to specify a type of daughterboard reconfiguration; The means further further include: a predetermined address bit of the address portion of each memory command coded to specify access to a different stage of the plurality of stages, the addressing means, and a different section of the plurality of stages. a corresponding number of logic gate means coupled to said bus for receiving, said logic gate means being connected to every other pair of said memory daughter boards designated by said encoding of said predetermined address bits; A memory system characterized in that the memory system is conditioned by the state of the predetermined address bits to change the encoding of the predetermined address bits to condition the addressing means to generate a signal for accessing a section of the memory system. . 28. The memory system of claim 27, wherein a first stage of the plurality of stages stores a first predetermined bit of the reconfigured bit pattern, and the first predetermined bit is connected to the daughter board pair. a first of said plurality of logic gate means is coded to specify whether said first bit of said predetermined address bit is to be exchanged or not translated; said first address bits to complement the state of said first one of said predetermined address bits; the first of a given bit of
A memory system characterized by being conditioned by the state of. 29. The memory system of claim 28, wherein the first state of the first predetermined bit corresponds to a binary "1" state, and the first of the logic gate means A memory system comprising a first exclusive-OR circuit for complementing said state of a first bit of a given address bit in response to a binary "1" state. 30. The memory system of claim 28, wherein a second stage of the plurality of stages stores a second predetermined bit of the reconstructed bit pattern;
a predetermined bit of the predetermined address bit is coded to specify whether half of the daughterboard pair is to be replaced or not; a second of the plurality of logic gate means a second state of said predetermined address bit for conditioning said addressing means to generate a signal for accessing said half of said daughterboard pair different from the half specified by the first state of said second bit; A memory system characterized in that the memory system is conditioned by the first state of said second predetermined bit to complement the state of the bit. 31. The memory system of claim 30, wherein the first state of the second predetermined bit corresponds to a binary "1" state, and the logic means responds to the binary "1" state. to obtain the complement of the state of the second bit of the predetermined address bit.
A memory system comprising an exclusive-OR circuit. 32. The memory system of claim 26, wherein said register storage means stores a plurality of bits of said reconstructed bit pattern coded to specify operating states of different sections of said memory. the bus response means: comprising a plurality of stages for receiving from the plurality of stages and a bus certain bits of the address bits of the address portion; input logic means for combining said plurality of bits of the reconstructed bit pattern to generate a bit and a signal indicating which section of said memory is offline; and said acknowledge signal according to the state of said signal. A memory system comprising output gate means coupled to said input logic means and said bus for generating. 33. The memory system of claim 32, wherein the input logic means: is coupled to a number of stages for generating a first output signal indicating when all controller daughter board memories are offline. first gating means coupled to said bus for receiving a signal corresponding to a first predetermined bit of said certain address bit specified by a diagnostic type of a memory command, said diagnostic command being an off-line controller communication; second gating means for generating a second output signal for indicating that the output is for; and coupled to said first gating means, said second gating means and said output gating means, and logically combining the first and second output signals to generate a third signal to enable generation of the acknowledge signal to permit offline communication with the offline controller during a diagnostic operating cycle; A memory system comprising third gate means. 34. The memory system of claim 33, wherein the input logic means further comprises fourth gate means coupled to the output gate means, and wherein the fourth gate means has a pair of input terminals. a first input terminal coupled to one of the plurality of stages for receiving a first signal indicating when at least half of the controller memory is in an offline state; said input logic means being coupled to said bus for receiving a second signal corresponding to a second predetermined bit of said address bits of said address portion indicating which half of said controller memory is to be addressed; , the output gating means is logically configured to generate an output signal for inhibiting the output gating means from generating the acknowledge signal that stops offline communication with the semi-offline controller.
and the second signal. 35. The memory system of claim 34, wherein the input logic means further comprises: a pair of input terminals and an output terminal, the first terminal of the pair of input terminals being connected to a predetermined board of the daughter board. is coupled to the predetermined board of the daughter board for receiving a third signal indicating when the controller is attached to the controller, and a second terminal of the terminal pair is coupled to the predetermined board of the daughter board to receive a third signal indicating when the controller memory is to be addressed. a fifth gate means coupled to said bus for receiving a fourth signal corresponding to a third predetermined bit of said address bits of said address portion indicating a plurality of input terminals and said output gate means; a first terminal of said input terminal is connected to said output terminal of said fifth gating means, and a second terminal of said input terminal is coupled to said fifth gating means; 5th to indicate the time
a third of said input terminals is coupled to another stage of said plurality of stages for receiving a signal of said certain address bit for indicating which quarter of said controller memory is being addressed. an output signal coupled to said bus for receiving a third predetermined bit and for inhibiting said output gating means from generating said acknowledge signal to stop offline communication with said one quarter of said controller memory; a sixth gating means for logically combining signals applied to the input terminals to generate a memory system. 36. The system of claim 35, wherein the first gate means includes an AND gate, the second gate means includes a NAND gate, the third gate means includes an exclusive-OR gate, and the third gate means includes an exclusive-OR gate. A memory system characterized in that the fourth gate means includes a NAND gate, the fifth gate means includes an exclusive-OR gate, and the sixth gate means includes a NAND gate. 37. The system according to claim 32, wherein the input logic means includes a pair of selection input terminals;
a multiplexer circuit comprising a plurality of data input terminals, the number of which corresponds to the maximum number of daughter boards that can be attached to each memory controller, and an output terminal coupled to the output gate means; are applied to the bus for receiving predetermined bits of the address bits of the address portion indicating which of the daughter boards is being addressed, each of the data input terminals being connected to said multiplexer circuit is coupled to a respective different one of said maximum number of daughter boards to receive a signal indicating whether said controller is front-populated when said daughter board is not installed; supplying said signal to said output terminal from the daughter board selected by said address bit to inhibit generation of a positive confirmation signal indicating that said address bit is not present;
A system operable in response to said predetermined bits of said address bits. 38 In a memory system having n addressable memory controllers, each controller for controlling memory operations includes a plurality of memory modules contained in a corresponding number of daughter boards, and wherein said controller memory commands, each memory command having a plurality of address bits encoded to specify which of said controllers is to perform the operation specified by said command. a bit address portion, said address portion of each predetermined type of command including a reconfiguration bit pattern coded to specify a plurality of different reconfiguration operating modes, and each of said memory controllers: a set of manual selection switches for generating a first set of signals specifying the address of the controller within the memory system during operation of the controller; and a register for storing the reconfigured bit pattern including the controller address signal. reconfiguration control section means comprising; output selection means coupled to said register and said set of switches for providing a signal representative of said address; coupled to said bus and said output selection means;
bistable mode control means switched to a first state in response to a predetermined type of coded memory command to specify a reconfiguration mode of operation of the associated controller; said switch, said reconfiguration register and said bus; comparator circuit means coupled to said mode control means for indicating said normal operation when detecting a comparison match between said first set of signals and said plurality of address bits of said respective predetermined types of memory commands; address comparison circuit means operative to generate an output comparison signal when in a second state; and bus response means coupled to said address comparison circuit means, said reconfiguration register and said bus; , said output comparison to generate an acknowledgment signal for enabling said reconstructed bit pattern to be stored in said reconstructed storage means and different bits within said bit pattern for conditioning said address comparison circuit means. conditioned by a signal, and said bistable mode control means is conditioned by said second
is operable to detect a comparison match between the controller address signal and the plurality of address bits of each successive command to generate the comparison and acknowledge signals, thereby controlling memory system operation. A memory system characterized in that it comprises: bus responsive means adapted to reconfigure different controllers of said n controllers to provide the necessary addressable memory. 39. The memory system of claim 38, wherein each predetermined type of memory command includes a diagnostic code, and wherein the reconfiguration section further includes: a decoder circuit coupled to the bus, the mode control means, and the register. the decoder circuit having an output signal for switching the mode control means to the first state and for being able to load the register of the addressed controller with the reconfiguration bit pattern. A memory system operated in response to said diagnostic code specifying said reconfiguration mode of operation to occur. 40. The memory system of claim 39, wherein each of the controllers further comprises an address controller coupled to the plurality of memory modules for generating signals for accessing different sections of the pair of memory daughter boards. and wherein the registers include a plurality of register stages for storing predetermined bits of the reconfiguration bit pattern that are coded to specify the type of daughterboard reconfiguration, and the reconfiguration section further comprises: said plurality of stages for receiving predetermined address bits of said address portion of each memory command coded to specify access of different sections;
a plurality of logic gates coupled to said addressing means and a bus, each of said plurality of logic gates said addressing of said memory daughter board pair not being specified by said encoding of said one predetermined address bit; A memory system characterized in that the memory system is conditioned by the states of different bits of said predetermined address bits to change the encoding of one of said predetermined address bits to condition a section. 41. The memory system of claim 40, wherein a first stage of the plurality of stages stores a first predetermined bit of the reconfigured bit pattern, the first predetermined bit being stored in the daughter board pair. a first gate of said logic gate is different from the pair specified by said state of said first bit of said predetermined address bits. a first of said first predetermined bits to complement the state of a first of said predetermined address bits for conditioning said addressing means to generate a signal for accessing said pair of said daughter boards; A memory system characterized by being conditioned by state. 42. The memory system of claim 40, wherein a second stage of the plurality of stages stores a second predetermined bit of the reconstructed bit pattern, the second predetermined bit being stored in the daughter board pair. a second gate of said logic gates is specified by said state of said second bit of said predetermined address bits; said second bit to complement the state of said second bit of said predetermined address bits for conditioning said addressing device to generate a signal for accessing said half of said daughter board pair different from said half; A memory system characterized in that it is conditioned by a first state of a predetermined bit. 43. The memory system of claim 40, wherein said register stores a plurality of bits of said reconfigurable bit pattern coded to specify offline operating modes of different sections of said memory daughter board. and the bus responsive means is: coupled to the bus for receiving from the plurality of stages and a bus certain bits of the address bits of the address portion; input logic means for combining the plurality of bits of the reconfigured bit pattern to generate a signal indicating which section of the controller memory is offline; according to the state of the input logic means and the signal; and output gating means coupled to the bus for generating an acknowledge signal. 44. The system according to claim 43, wherein the input logic means includes a pair of selection input terminals;
a multiplexer circuit comprising a plurality of data input terminals, the number of which corresponds to the maximum number that can be attached to each memory controller, and an output terminal coupled to the gate means, the input terminal pairs being addressed; each of said data input terminals is coupled to said bus for receiving a predetermined terminal of said maximum number of boards for receiving a signal indicating whether said different daughter board is installed or uninstalled; a different one of the multiplexer circuits coupled to the address bits to inhibit generation of a positive acknowledge signal indicating that the controller is not front-populated when the daughter board is not installed. The system is operative in response to said predetermined bit of said address bits to provide said signal to said output terminal from a daughter board selected by said address bit. 45. The system of claim 42, wherein a third stage of the plurality of stages stores a third predetermined bit of the reconstructed bit pattern, the third predetermined bit being an address for the controller. specifying an operating mode, the third stage of the stage receiving a power-on signal for switching the stage to a first state corresponding to a first address mode when the controller is powered on for operation; a plurality of output terminals coupled to a different one of the plurality of logic gates and the addressing means; and a plurality of input terminals. a first set of terminals, the first set of input terminals having a first plurality of said address bits encoded to specify a controller address when said system is operated in a first addressing mode of operation; a second plurality of address bits, the second set being encoded to specify the controller address when the system is operated in a second addressing mode of operation. a set of said plurality of input terminals coupled to said bus for receiving said address bits; and a control input terminal coupled to said third stage of said stages for receiving a signal representative of a state of said stage; a selection circuit having a selection circuit configured to condition the addressing means to operate the first plurality of address bits in the first addressing mode when in the first state; conditioning the selection circuit to apply the first plurality of address bits to an output terminal, and when a third of the stages is switched to the second state in response to a predetermined type of the memory command; , conditioning the selection circuit to apply the second plurality of address bits to the output terminal conditioning the addressing means to operate in the second addressing mode. 46. The memory system of claim 45, wherein the first state corresponds to a binary "1" state, the first addressing mode corresponds to an interleaved mode of operation, and the second A memory system characterized in that the state corresponds to a binary "0" state and the second addressing mode corresponds to a bank operation mode. 47 A reconfigurable memory controller for changing the addressing of a plurality of storage modules connected to and controlled for reading and writing by the controller, the controller operating within a system including a plurality of said memory controllers, each of which The controllers are identified within the system by a unique identification code, and the system includes a data processing device for sending instructions to one of the controllers to control the operation of the controller, the instructions being configured to address a set of signals operable in a plurality of states and operable to generate a first set of signals representative of the initial identification code of the controller; a switch 216-6; a second group of signals retaining information representative of reconfigured attributes of the controller and representing an identification code different from that represented by the group of switches and other reconfigured attributes of the controller; a register 216-8 for generating another signal representing an attribute; and circuitry for loading a portion of the instruction representing the attribute into the register in response to an instruction addressed to the controller specifying a reconfiguration operation. 2
16-2, capable of operating in two states, initially operating in the first state, but shifting to operating in the second state in response to reception of the reconfiguration prescription command by the controller. a mode control element 216-10 connected to receive the first and second signal groups and transmit a signal group representative of one of the received signal groups; A first state of the element is controlled to transmit a group of signals representing the first group of signals, and a second state of the element is controlled to transmit a group of signals representing the second group of signals. Selection switch 216-12
, whereby the output signals sent by the selection switch are representative of the current identification code of the controller receiving instructions from the data processing device, and the output signals sent by the register are representative of the current identification code of the controller receiving instructions from the data processing device; is adapted to control reconfiguration addressing of storage modules of said controller.