JPH0470824B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an erasing device for erasing image information recorded on a recording medium.

[Conventional technology]

2. Description of the Related Art Recording and reproducing apparatuses for recording and reproducing, for example, still image information on recording bodies such as disks, for example, have been developed in recent years.

As such a device, for example, a device that uses a recording/reproducing head to record, reproduce, and erase data one block at a time on a recording medium is considered.

[Problems to be Solved by the Invention] In a conventional recording/reproducing apparatus having the function of recording, reproducing, and erasing data block by block on a recording medium, the unit of erasing is block by block. Therefore, for example, a frame image recorded on a magnetic disk in which one field of video signal is recorded in one block, and two field video signals constituting one frame of video signal are recorded in two adjacent blocks, respectively. When erasing a signal, it is necessary to manually erase each block twice, which poses a problem in that the operability is not necessarily good.

This problem occurs not only in the device that erases a recording medium on which a video signal is recorded as described above, but also in a device that erases one block at a time.

[Means for solving problems]

In order to solve the above-mentioned problems, the erasing device of the present invention includes a reproducing means (corresponding to 3-1, 3-2, and 6 in FIG. 1 in the embodiment) for reproducing information recorded on a recording medium, The image information recorded in the first
Is the image information recorded in the first recording mode (field recording mode), or is the image information recorded in a high-quality second recording mode (frame recording mode) that has a larger amount of information than the first recording mode? a discriminating means (also shown in FIG. 1, 12) for discriminating from the playback output of the playback means, an erasing means (also shown in FIG. 1, 85) for erasing the image information recorded on the recording medium;
An operation member (also the numeric keypad in FIG. 4), a first erasing mode (also the 27th erasing mode) in which the erasing range of the recording body by the erasing means is automatically controlled according to the discrimination result of the discrimination means in response to a given erasing instruction. #V-7, #V-8 in the figure) and image information in the specified range is erased by manual operation of the operating member in response to the given erasure instruction regardless of the discrimination result of the discrimination means. and a second erasing mode for controlling the erasing range of the recording medium by the erasing means (#V- in FIG.
5, #V-5-1, #V-8, #V-10), a second control means (also the 27th #V-1) in the figure.

<Example> The present invention will be described in detail below with reference to the drawings. In the example of the present invention described below, a still image video signal is recorded on a disk-shaped recording medium, specifically, a disk-shaped magnetic sheet. A recording and reproducing apparatus that records or reproduces a recorded still image video signal will be described.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a magnetic sheet on which a recording/reproducing track of a video signal, a track pitch, and a position of the track are predetermined. In the case of a recorded frame video signal, one field of the video signal is recorded on each of two adjacent tracks to form a frame video signal. The magnetic sheet 1 is placed in a jacket (not shown) in advance, and the jacket is provided with a claw to prevent accidental erasure, and by breaking this claw in advance, the erasing operation is prohibited in the same way as with an audio cassette. . 2 is a DC motor for rotating the magnetic sheet 1 at a constant speed; 3-1 and 3-2 are in-line heads that access two adjacent tracks; 3-1 is the outer peripheral side and 3-2 is the inner head. Access the peripheral side. 4 is a magnetic head 3-1, 3-2
A magnetic head moving mechanism 5 moves the magnetic head 3-1 so as to access the track formed on the magnetic sheet 1, and a magnetic head moving mechanism 5 moves the magnetic head 3-1 to access the innermost track on the magnetic sheet 1. The state switches from off to on, and the microcomputer (hereinafter referred to as CPU) 40, which will be described later,
6 is a reproducing amplifier for amplifying the signals detected by the magnetic heads 3-1 and 3-2, and 7 is the average value of the output signal from the reproducing amplifier 6. 8 is a comparator that detects whether the output of level detector 7 is higher than a threshold value set by a reference voltage source (not shown); 9 demodulates the output signal of reproduction amplifier 6; A demodulation circuit; 10 is a 1/2H delay circuit that delays the output of the demodulation circuit 9 by 1/2 horizontal scanning period (hereinafter referred to as 1/2H); 11 is a demodulation circuit 9;
Horizontal synchronization signal Hsync, vertical synchronization signal from the output of
A synchronization signal separation circuit 12 separates a synchronization signal such as Vsync, and detects a predetermined data signal from the output of the reproduction amplifier 6 according to the timing of the synchronization signal separated from the synchronization signal separation circuit 11, and demodulates the data signal. It is a data demodulator. The data signal is a signal for determining what kind of information is recorded on the track, for example, whether it is a field video signal or a frame video signal, and a signal for the date set by the user. is a signal indicating an 11-digit number freely set by the user, and is recorded in a frequency band lower than the video signal at a position that has a predetermined relationship with the part where the track synchronization signal is recorded. . The reason why the demodulation circuit 9 and the data demodulation circuit 12 are provided separately here is as follows. That is, the video signal recorded on the magnetic sheet 1 is FM modulated, but the data signals other than the video signal use a DPSK modulation method (Differential Phase Shift Keying) that is different from FM modulation. Therefore, the demodulation circuit 9 described above is an FM
The data demodulation circuit 12, which is a demodulation circuit, is a DPSK demodulation circuit.

Reference numeral 13 denotes a monitor for reproducing and observing video signals, and reference numeral 13' denotes a printer connected to print the video signals. Furthermore, the printer 13'
starts operating when the signal at the start signal input terminal becomes H level, and sets the busy signal output terminal to L level during operation. 14 is a data demodulator 12
On the contrary, it is a modulator that performs DPSK modulation on data output from the CPU 40, which will be described later, and is modulated at a timing corresponding to Hsyn and Vsync separated by the synchronization signal separation circuit 17 from the video signal input from the video input terminal 18. The recorded data is output to the recording amplifier 16.

A recording amplifier 15 performs processing necessary for recording, such as FM modulation, on the video signal input from the video signal input terminal 18 and outputs it to the recording amplifier 16. 19 is a reference signal generator, which generates accurate reference pulses (60
Hz) and generates an alternating signal for cancellation.

Reference numeral 20 denotes a magnetic piece provided on the magnetic sheet 1 described above, and as described later, the magnetic piece 2
The rotation of the DC motor 2 is controlled in synchronization with the reference signal generated by the reference signal generator 19 using the signal from 0. 21 is a PG coil for detecting a signal from the magnetic piece 20 when the magnetic sheet 1 is rotated by the DC motor 2.

22 is a waveform shaping circuit that shapes the waveform of the signal output from the PG coil 21, and the output of the waveform shaping circuit 22 is input to a CPU 40 and a motor control circuit 23, which will be described later.

23 is a control circuit for controlling the rotation of the DC motor 2, and is a control circuit for controlling the rotation of the DC motor 2;
Vsync or the output signal of the reference signal generator 19 and the output of the waveform shaping circuit 22, that is, the magnetic sheet 1
The rotation of the DC motor 2 is controlled so that the phase relationship with the signal from the magnetic piece provided above is in a predetermined relationship, for example, so that the two are always out of phase by 7H. Here, when a recording operation is performed by the magnetic heads 3-1 and 3-2, SW1 is the synchronizing signal separation circuit 1.
The rotation of the DC motor 2 is controlled based on Vsync and the signal input from the waveform shaping circuit 22, that is, the signal from the magnetic piece 20 provided on the magnetic sheet 1. When the heads 3-1 and 3-2 perform a reproduction operation, SW1 is switched to the reference signal generator 19 side, and the reference signal from the reference signal generator 19,
The rotation of the DC motor 2 is controlled based on a signal input from the waveform shaping circuit 22, that is, a signal from the magnetic piece 20 provided on the magnetic sheet 1.

23' is a driver that drives a step motor 24 for controlling the positions of the heads 3-1 and 3-2 based on a signal from the CPU 40, which will be described later.
The heads 3-1 and 3-2 are moved via the.

25' is a display circuit driven by a signal from the CPU 40, and the display element is a third one, which will be described later.
As shown in the figure, the NO of the track being accessed by heads 3-1 and 3-2,
A 7-segment display element that displays the feed speed of the PB.2 digits indicates the playback mode.
LED, REC.LED to indicate recording mode
It consists of FRAME.LED that displays frame mode and FIELD.LED that displays field mode.

26 stores programs for CPU 40
ROM 27 is a RAM in which data of the CPU 40 is temporarily stored. 28 is a timer driven by the CPU 40, and 29 is a crystal oscillator that generates a reference clock for the CPU 40. Note that 80 is a photocoupler 81, which constitutes a detection switch for detecting whether or not the magnetic sheet 1 is inserted.
Detection circuit connected to 82.

83, 84 and SW6 are circuits for displaying data signals (hereinafter referred to as ID) such as year, month, day, etc. signals and signals freely set by the user on the monitor 13 and printer 13'. 83 is the Vsync and Vsync of the video signal input through SW5 to adjust the timing of the data characters generated.
This is a sync separation circuit that separates Hsync, and has the same configuration as the sync separation circuit shown as 17. 8
4 is separated by the synchronous separation circuit 83
This is a character generator that generates characters corresponding to data signals in synchronization with Vsync and Hsync. When displaying the ID signal superimposed on the video signal on the monitor 13 and printer 13', a control signal is given from the CPU 40, SW6 is turned on, and the synchronization signal and data signal are added by the adder shown in FIG. monitor 13 or printer 13'
displayed in a specific position. The details will be described later.

Reference numeral 85 denotes an erase signal generator for erasing signals on arbitrary tracks of the magnetic sheet 1. Note that the AC signal for erasing is provided from the reference signal generator 19.

Here, the erasure signal generator 85 is, for example, a second
A decay signal formed by a constant amplitude period T ₁ and a subsequent decay period T ₂ as shown in FIG. 9 is generated and connected to the recording amplifier 16.

SW1 is a switch whose state is changed by a signal from the control circuit 30 that is driven based on a signal from the CPU 40, and a video signal is input from the video signal input terminal 18, and the synchronization signal separation circuit 1
When Hsync is output from 7 and when a signal indicating recording mode is input from the CPU, the synchronous signal separation circuit 17 and the motor control circuit 23 are connected, and the synchronous signal separation circuit 17 Hsync is not output from the CPU 40, or a signal indicating that the CPU 40 is in the playback mode is input, or the reference signal generator 1 is in the erase mode.
9 and the motor control circuit 23 are connected.

SW2 is a switch whose state changes based on a signal from the CPU 40, and it connects the head 3-1 to the recording amplifier 16, connects it to the playback amplifier 6, and connects it to either the recording amplifier 16 or the playback amplifier 6. Switch between an intermediate state in which no connections are made.

Like SW2, SW3 is a switch whose state changes based on a signal from the CPU 40, and there are two states: connecting the head 3-2 to the recording amplifier 16, connecting the head 3-2 to the playback amplifier 6, and connecting the head 3-2 to the recording amplifier 16.
It switches between an intermediate state in which it is not connected to any of the reproduction amplifiers 6.

When reproducing a video signal from the magnetic sheet 1, when reproducing a frame video signal using both heads 3-1 and 3-2, SW4 is switched to the upper side in FIG. It is now connected and head 3-1
In the case of reproducing a field video signal using only the 1/2H delay circuit, there are two states in which it is switched to the upper side in FIG. This is a switch that is driven by the CPU 40 so that the state in which the data is displayed is alternately switched for each field.

SW5 connects the monitor 13 to the video signal input terminal 18 during recording, and connects the monitor 13 to the SW during playback.
This is a switch driven by the CPU 40 so as to connect to the CPU 40.

By the way, as mentioned above, the video signal recorded on or reproduced from the magnetic sheet 1 can be a field video signal consisting of only one field, or a frame video signal consisting of two fields in pairs. However, SW2 in such a case,
Switching of the states of SW3, SW4, and SW5 will be explained using FIG. 2.

FIG. 2 is a diagram showing combinations of switching states of SW2, SW3, SW4, and SW5.

During field playback, SW2 is head 3-
1 is connected to the playback amplifier 6, SW3 is in the intermediate state,
That is, the head 3-2 is not connected to the reproduction amplifier 6 or the recording amplifier 16, and the SW 4 outputs the signal directly from the demodulation circuit 9 to the monitor 13 in odd fields, and outputs the signal directly to the monitor 13 in the even fields. The signal is alternately switched for each field so that the signal is outputted to the monitor 13 through the input signal, thereby preventing the occurrence of skew distortion.

Next, during frame playback, SW2 connects the head 3-1 to the playback amplifier 6 in odd-numbered fields, and is in an intermediate state in even-numbered fields;
is in an intermediate state in odd fields, and connects the head 3-2 to the reproduction amplifier 6 in even fields. Therefore, during frame playback, head 3-
Either signal 1 or 3-2 is alternately output to the reproduction amplifier 6 for each field.

In this case, SW4 is switched to the upper side in FIG. 1, and the signal from demodulation circuit 9 is directly output to monitor 13.

In any of the above-mentioned field playback and frame playback states, SW5 is driven so that the monitor 13 is connected to SW4.

Next, in field recording, SW2 connects the head 3-1 to the recording apparatus 16, and SW3 is in an intermediate state.

Therefore, when recording the field, the head is 3-1.
Recording is performed by

In addition, in frame recording, SW2 connects the head 3-1 to the recording amplifier 16 in odd-numbered fields, and is in an intermediate state in even-numbered fields;
is in an intermediate state for odd fields, and connects the head 3-2 to the recording amplifier 16 for even fields. In addition, in frame recording, head 3-1,
You can also reverse the 3-2 combination.

Further, in both field recording and frame recording, during recording, the SW 5 is switched so that the monitor 13 is connected to the video signal input terminal 18 so that the video signal to be recorded can be observed on the monitor 13. Further, in such a case, SW4 may be in any state.

Next, the erase mode will be explained. In the erase standby state, which will be described later, SW1 is connected to the reference signal generator side, and SW5 is connected to the upper side in FIG. 1, which is exactly the same state as in the reproduction mode. At this time, a case will be described in which field erasing is performed, for example, erasing only the track being reproduced by the magnetic head 3-1. In this case, at the same time as erasing starts, a control signal is sent from the CPU 40 so that SW2 is placed on the recording amplifier side and SW3 is placed in an intermediate state.Furthermore, an erase signal trigger pulse is sent from the CPU 40 to the erase signal generator 85, and the erase signal trigger pulse is sent to the head 3-1. The erase signal is sent only when the

Next, a description will be given of frame erasing in which tracks being accessed by heads 3-1 and 3-2 are simultaneously erased. When erasing a frame, SW2 and
Both SW3 are CPU40 on the recording amplifier side.
send control signals. Then, an erase signal is generated by a trigger pulse from the CPU 40, and the erase signal flows to both heads via the recording amplifier.

Furthermore, in the embodiment, when field erasing is performed, the erasure is performed using head 3-1, but when field erasing is performed using head 3-2,
It is sufficient to control so that SW2 is in the intermediate state and SW3 is on the recording amplifier side.

Next, the switches 51 to 78 shown in FIG. 1 will be explained.

In giving this explanation, the external appearance of the apparatus of this embodiment shown in FIGS. 3 and 4 will also be explained.

FIG. 3 is a front view of the apparatus of this embodiment, and FIG. 4 is a front view of a remote control device used in the apparatus of this embodiment.

The switches 51 to 79 and 72 shown in FIG. 1 are the switch group provided in the device shown in FIG. 3, the switch group provided in the remote control device shown in FIG. The switches are divided into groups of switches provided in both the remote control device shown in FIG. 4 and the remote control device shown in FIG. still,
The switch provided in the device shown in FIG. 3, which in FIG. 1 is only provided in the remote control device shown in FIG. 4, is connected to the CPU 40 via a line. Although shown for convenience, the signal generated by operating the switch provided only with the remote control device shown in FIG.
The remote control device converts the light into infrared light, and the remote control light receiving section 4 provided in the device shown in FIG.
5 to the CPU 40 of such a device.

It should be noted that the method of arranging the switches 51 to 79 can be considered in various other variations of this embodiment, and is not limited to this embodiment.

1 to 4, 41 is a power switch, 42 is a slot for inserting the magnetic sheet 1, and when the inject button 43 is turned on while the magnetic sheet 1 is inserted into the slot 42, the power switch is turned on automatically. The magnetic sheet 1 is injected when the magnetic sheet 1 is opened. 43 is the inject button, 44A, 4
4B is the aforementioned PB.LED and REC.LED, 45 is a remote control light receiving unit that receives a signal from the remote control device shown in FIG. 4, 46 is an interval mode display LED that lights up when interval playback is executed, 48 is a display LED that displays whether field playback or recording, frame playback or recording is set, 25 is the aforementioned two-digit 7-segment LED, 50A, 50B,
Reference numeral 50C is an LED indicating the operation status of a program playback setting switch 58, an interval time setting switch 57, and a program track setting switch 62, which will be described later.

51 is a REC mode switch for setting the recording mode and checking whether the track accessed by the head in recording mode is recorded or unrecorded; when this switch is turned on, the head is accessed. (If the track being accessed by head 3-1 has already been recorded during field recording, the track accessed by either head 3-1 or 3-2 during frame recording is has already been recorded)
The REC.LED flashes to indicate that the track being accessed by the head cannot be recorded, and if it has not been recorded, or if the control circuit 30 determines that no video signal is input, the REC.
The LED lights up to indicate that recording is possible.

Reference numeral 52 denotes a REC switch that determines the timing of recording operation, and when the recording mode is set by the REC mode setting switch 51 and the switch 51 is turned on, recording is performed on the magnetic sheet 1. . Furthermore, if continuous recording has been set in advance by a track feed speed setting switch 56, which will be described later, continuous recording will be performed while the heads 3-1 and 3-2 are automatically shifted while the switch 51 is on. be exposed.

53 is a PB mode setting switch for setting the playback mode, and when the switch 53 is turned on, the PB.LED indicating the playback mode is lit.

Reference numeral 54 denotes a track UP switch. By operating the switch 54, the driver 23' is controlled, the step motor 24 is rotated, and the heads 3-1 and 3-2 are moved by the head moving mechanism 4. Shift 3-1, 3-2,
The track that the head is accessing is changed toward the inner circumference. Further, when recording is performed in frames using a field/frame setting switch 59, which will be described later, the recording progresses two tracks at a time. When playback is set, when the track UP switch 54 is turned on, the heads 3-1 and 3-2 are shifted by 2 tracks, and the 7 segment LED 25 also shows the track number 2 instead of the track number shifted by 1 track. The track number shifted one track at a time is displayed, and when the track UP switch 54 is turned on when field recording or playback is set, the heads 3-1 and 3-2 are shifted one track at a time toward the inner circumference. 7 segment LED 25
The shift number shifted one track at a time is also displayed.

Furthermore, when the recording mode is set and the heads 3-1 and 3-2 are shifted by operating the track UP switch 54, the tracks accessed by the heads 3-1 and 3-2 are recorded. If completed, REC.RED44B flashes.
55 is a track DOWN switch, opposite to the track UP switch 54, for changing the access of the heads 3-1 and 3-2 toward the outer circumference.

When the switch 55 is also set to frame playback in the same way as the track UP switch 54, when the switch 55 is operated and the tracks on the outer circumference of the first track and the tracks on the outer circumference of the second track are being recorded as frames, Hano 7 segments
The track number shifted by 2 tracks is displayed on LED 25 instead of the track number shifted by 1 track, and when field recording or playback is set, the switch 5
When 5 is operated, the track number shifted by one track is displayed.

Also, in the case where the recording mode is set in advance in the same way as explained with the track UP switch 54, and when the heads 3-1 and 3-2 are shifted by the operation of the track DOWN switch 55, access is made. If the track has been recorded, the REC.LED 44B flashes.

Reference numeral 56 indicates whether the operation is automatically performed continuously while shifting the head when storing or reproducing information, or whether it is performed singly, and further indicates how many times per second the operation is performed when the operation is performed continuously. This is a track feed speed setting switch for setting the track feed speed.

When the switch 56 is pressed once and turned on, 7
The segment LED 25 displays the track feed speed instead of the track number, and in this state, if the track feed speed setting switch 56 is turned on again within the predetermined time clocked by the timer 28 shown in FIG. Each time the 7-segment LED 25 is turned on, the 7-segment LED 25 will display, for example, "〓" indicating continuous recording or playback of 2 screens per second, "〓" indicating continuous recording or playback of 5 screens per second, 1 second. to 10
Indicates continuous recording or playback of the screen.
“〓”, “〓” indicating single-shot recording or playback is displayed cyclically. Also, by turning on and then turning off the switch 56, 7
If the track feed speed is displayed instead of the track number on the segment LED 25 and the timer 28 completes counting the predetermined time without turning on the switch 56 again, the LED 25
returns from the state where the track feed speed is displayed to the state where the normal track number is displayed.

Also, when the track feed speed is changed by the switch 56, the field/
When frame video recording is set by the frame setting switch 59 and the REC mode setting switch 51, continuous recording of 10 screens per second is not set.

57 is an interval time setting switch.
That is, the interval time setting switch is used to set the interval time for track forwarding when continuous playback is performed but the playback interval time is relatively long, or when program playback is set by the program track setting switch 58, which will be described later. The interval time is set using the ten key switches 63 to 72 within 10 seconds after the switch is turned on.

Incidentally, when any switch other than the 10 key switches 62 to 73 is turned on after the interval time setting switch 57 is turned on, the interval time setting is automatically canceled. Reference numeral 58 denotes a program playback setting switch for setting a program playback mode in which the order of playback tracks is programmed in advance and the playback operation is performed continuously at the interval time interval set by the interval time setting switch 57.

To specify the order of playback tracks, first press the switch 58.
The program playback mode is set by turning on the track UP switch 54 and the track DOWN switch 55 to change the track being accessed by the heads 3-1 and 3-2 and select the desired track. Play video and monitor 1
This is done by turning on a program track setting switch 62, which will be described later, while checking the track number on the monitor 13 while checking the track number. Reference numeral 59 denotes the aforementioned field/frame setting switch, and each time the switch is turned on, the field recording or reproduction mode and the frame recording or reproduction mode are alternately switched.

If the continuous recording mode of 10 screens per second is set in advance by the REC mode setting switch 51 and the track feed speed setting switch 56, and the frame recording is selected by the field/frame setting switch 59, the track feed will start. The speed is automatically changed to continuous recording mode of 5 screens per second.

That is, compared to field recording, when recording frames, the heads 3-1 and 3-2 must be shifted by two tracks at a time, so when recording 10 screens per second, the headers 3-1 and 3-2 must be shifted by 20 tracks per second. It is necessary to perform a head shift of two tracks in 4/60 seconds, taking into account the time to record the video signal, but such a high-speed head shift is difficult, so in this embodiment Continuous recording of 10 frames per second is prohibited.

60 is a start switch for performing continuous interval playback or program playback; when the start switch is turned on, if interval playback is set, the recorded tracks will be played back sequentially starting from the first track during the interval time. Setting switch 57, numeric key switch 63-72
Interval playback is started according to the interval time set by , and program playback is started when program playback is set. 6
Reference numeral 1 denotes a stop switch that stops the reproduction operation started by the start switch 60, and when the switch 61 is turned on during program reproduction, the reproduction of the program is stopped while the track being reproduced at the time is being reproduced.

62 is the aforementioned program track setting switch.

Reference numeral 73 is a switch for starting ID setting in the recording mode and for switching whether or not to display the contents of the ID in the playback mode. That is, by turning on the switch 73 in the recording mode, the mode becomes the ID setting mode, and by turning on the switch 73 in the playback mode.
It is possible to switch between displaying and not displaying the contents of the ID. 74, 75,
Reference numerals 76 indicate a switch that is turned on to set the year as the ID when the ID setting mode is entered by the switch 73, a switch that is turned on when the month is set, and a switch that is turned on when the day is set. . In FIG. 1, switches 74, 75, 76 and the aforementioned switches 57, 5 are shown for convenience.
Although 8 and 62 are shown as independent switches, in this embodiment, switches 74, 75, and 76 are also used as switches 57, 58, and 62, respectively, as shown in the remote control device of FIG. In other words, the operation of the program setting by the interval time setting switch 58 by the switch 57 and the program track setting by the switch 62 is ID.
This is done independently of the year, month, and day settings, so in this embodiment, the switch is also used to reduce the number of switch members and improve operability and reliability.

In addition, various other combinations can be considered when the switch is also used.

77 is an erase standby switch for temporarily putting the device into an erase standby state when erasing information recorded on the magnetic sheet 1; 78 is an erase standby switch for executing the erase operation in the erase standby state set by the erase standby switch 77; This is an erase switch. Reference numeral 79 is an all-track erase standby switch that sets a mode for erasing all tracks.

When erasing the information recorded on the sheet 1, the switch 77 is first turned on to set an erasing standby state. In such a state, the reproduction mode is automatically set, so that the video recorded on the track to be erased can be checked on the monitor 13 or on the printer 13' before erasure is executed. In addition, by operating the 10 key switches 63 to 72 in the standby state, the number of tracks to be continuously erased can be specified. Next, by turning on the erase switch 78, the heads 3-1,
3-2 is connected to the recording amplifier 16, and the information recorded on the track is erased by the erase signal shown in FIG. 32 generated from the erase signal generator 85. Also, turn on the all track erase standby switch 79 and then turn on the erase switch 7.
If you turn on 8, all tracks will be automatically deleted.

Next, Fig. 5 to Fig. 20, Fig. 23, Fig. 25 to
The operation of the embodiment of the present invention will be explained using the flowchart shown in FIG.

First, when the power switch 41 shown in FIG. 3 is pushed in, the power of the device shown in FIG. 1 is turned on, and power is supplied to each part of the circuit to start operation.

#1: Then register S, which will be described later in FIG.
is reset to "0", the PB mode flag is set, and the track feed speed is initially set to 2 screens per second and the interval time to 3 seconds. Therefore, when the power is turned on, the continuous playback mode is automatically set in advance.

#2: Detect whether or not the jacket having the magnetic sheet 1 is inserted. When the jacket is pushed in, the flow branches to #3, and when it is not pushed in, the flow skips #3 and branches to #4.

#3: When the jacket having the magnetic sheet 1 is being pushed in in #2, the DC motor 3 is driven.

#4: The head 3-1 is turned on by detecting whether the switch 5 shown in FIG.
The flow branches to #6 when the head is accessing the 50th track, and when the head 3-1 is not accessing the 50th track. Then, the flow branches to #5, and the loop of #4 and #5 is repeated so that the step motor 24 shown in FIG. 1 is driven and the head 3-1 accesses the 50th track.

#6: When the head 3-1 accesses the 50th track, the flow reaches this step, where the register N for accessing the memory (RAM 27) is set to 50.

#7: In this step, it is detected whether or not the DC motor 2 is being driven. When the jacket having the magnetic sheet 1 described above is inserted, the DC motor 2 is driven by executing #3, so the flow advances to step #8 and the field flag is set. When the jacket is not inserted, the flow proceeds without passing through #3, so the DC motor 2 is not driven. Therefore, the flow returns to #2 to detect whether a jacket is inserted.

#8: When the DC motor 4 is being driven in #7, the field flag is set. Therefore, the field mode shown in Fig. 3 is shown.
The LED 44A lights up and a display indicating that it is a field is performed. That is, in this embodiment, when the power is turned on and the jacket is inserted, the field mode is automatically set.

#9: The output of the level detection circuit 7 shown in FIG. 1 is detected to determine whether or not the track being accessed by the head 3-1 is a recorded track. Here, since the track being accessed by the head 3-1 has already been recorded, when the output of the level detection circuit 7 becomes H level, the flow advances to #10.
When the output of the level detection circuit 7 becomes L level, the flow advances to #16.

Here, we will first explain #16.

#16: Set “0000” to address N in memory. Here, "0000" indicates that the track corresponding to the memory address is unrecorded.

Next, the flow from #10 onwards will be explained.

#10: At #9, the output of the level detection circuit 7 is H
When the level is determined, the signal recorded on the track is reproduced and the ID signal is taken in from the data demodulator 12.

#11: Detect the contents of the ID signal to determine whether the video signal recorded on the track is a field video signal or a frame video signal. If it is a field video signal, the flow advances to #15, and if it is a frame video signal, the flow advances to #12.

#12: In this step, it is determined whether the video signal of the track that the head 3-1 is accessing is an inside track or an outside track of the frame video signal. If it is an inside track, flow goes to #14. If it is an outside track, flow goes to #13.

#13: If the video signal of the track that the head 3-1 is accessing is a track outside the frame video signal, set the memory address N to "0011". Note that when proceeding to this step for the first time from #1, N is set to 50 in #6.

#14: For the inner track of the frame video signal, set the memory address N to "0010".

#17: When the head 3-1 is shifted to the first track and it is detected that N=1, the flow proceeds to #20, and if N=1, the flow proceeds to #18.

#18: When it is detected in #17 that N=1 is not true, the head 3-1 is shifted toward the outer circumference by one track.

#19: In #18, when the head 3-1 is shifted to the outer circumferential side, it is subtracted from N and set as N.

#20: When N=1 is detected in #17, that is, when the head 3-1 accesses the first track provided on the outermost circumference and the presence or absence of recording is set in the memory, the memory is set here. If you read the data at address N, that is, the first address of the memory, and it is "0011", specifically, if the first track is the outer track of the two tracks that make up the frame video signal, go to #21. Flow proceeds, otherwise flow proceeds to #23.

#21: If it is detected in #20 that the first track is a track outside the tracks constituting the frame video signal, the flow advances to this step. In this step, if the data at address N+1 of the memory, that is, the second address of the memory, is read and it is "0010", specifically, if the second track is the inner track of the two tracks constituting the frame video signal. Proceed to #22.

#22: The flow moves to this step when frame video signals are being recorded on two tracks, the first track and the second track. Therefore, the field flag set in #8 is cleared and the field mode is changed to frame mode. Therefore, the field frame display LED 48 shown in FIG. 3 lights up to indicate the frame mode.

#23, #24: Display the register N indicating the address of the memory mentioned above on the 2-digit 7-segment LED 25 shown in FIGS. 1 and 3.

This display allows the user to recognize the number of the track that the head 3-1 is accessing.

When this flow ends, the process jumps to the next flow shown in A. The flowchart shown in FIG. 6 will be explained below.

#A-1: Detects whether the REC mode setting switch 51 is turned on, and when the switch 51 is turned on, the flow calls a subroutine and sets the recording mode, and when it is not turned on, #A Proceed to -2.

#A-2: Detect whether the REC switch 57 is turned on. If the switch 52 is turned on, a subroutine is called; if it is not turned on, the process proceeds to #A-3.

#A-3: Detect whether the PB mode setting switch 53 is turned on, and when the switch 53 is turned on, call the subroutine, and when it is not turned on, proceed to #A-4.

#A-4: When the track UP switch 54 is turned on, the flow calls a subroutine,
If it is not turned on, proceed to #A-5.

#A-5: When the track DOWN switch 55 is turned on, the flow calls a subroutine, and when it is not turned on, the flow advances to #A-6.

#A-6: Track feed speed setting switch 5
When 6 is turned on, the flow calls a subroutine, and when it is not turned on, the flow advances to #A-7.

#A-7: When the interval time setting switch 57 is turned on, the subroutine is called, and when it is not turned on, the process advances to #A-8.

#A-8: When the program setting switch 58 is turned on, the subroutine is called; when it is not turned on, the process advances to #A-9.

#A-9: Program track setting switch 62
When it is turned on, a subroutine is called, and when it is not turned on, it proceeds to #A-10.

#A-10: Field frame setting switch 59
When it is turned on, a subroutine is called, and when it is not turned on, it proceeds to #A-11.

#A-11: When the start switch 60 is turned on, a subroutine is called; when it is not turned on, the process proceeds to #A-12.

#A-12: When the stop switch 61 is not turned on, a subroutine is called, and when it is not turned on, the process proceeds to #A-13.

#A-13: When the jacket detection switch (corresponding to the detection circuit 80 in FIG. 1) is turned on, the process jumps to the subroutine, and when it is not turned on, the process advances to #A-14.

#A-14: Clear the program playback mode flag and program playback execution flag.

#A-15: 10 When any of the key switches 63 to 72 is turned on, a subroutine is called, and when it is turned on, the process advances to #A-16.

#A-16: When the ID switch 73 is on, call the subroutine, and when it is on, proceed to #A-17.

#A-17: When the year setting switch 74 is on, call the subroutine, and when it is on, proceed to #A-18.

#A-18: When the month setting switch 75 is on, call the subroutine, and when it is on, proceed to #A-19.

#A-19: When the date setting switch 76 is on, call the subroutine, and when it is on, proceed to #A-20.

#A-20: When the erase standby switch 77 is on, call the subroutine, and when it is on, proceed to #A-21.

#A-21: All track erase standby switch 7
When 9 is on, the subroutine is called, and when it is on, the process advances to #A-13.

As explained above, after the head 3-1 has accessed the first track of the magnetic sheet by executing the flow shown in FIG. 5, the flow jumps to the flow shown in FIG. While detecting the state of each switch shown in FIG. 4, the flow shown in FIG. 4 is repeatedly executed until the state of each switch changes, and a subroutine corresponding to the operated switch is called.

Here, track setting feed speed switch 56
The subroutine called when is turned on will be explained using FIG.

FIG. 7 is a flowchart showing a subroutine executed when the switch 56 for changing the track setting feed speed is turned on.

#F-1, #F-2: The set value of the track feed speed is read from the memory, and the set value is set in a track number display buffer (not shown).

Therefore, the track feed speed is displayed on the two-digit seven-segment LED 25 shown in FIG. When the flow comes to this step for the first time, "ⓓ" is displayed because the track feed speed of 2 screens per second is set in #1.

#F-3: Track feed speed setting switch 5
When the switch 56 is on, the flow repeats #F-3, and when the switch 56 is turned off, the flow moves to #F-4.

As mentioned above, once the track feed speed setting switch 56 is turned on, the display of the track number is switched from the display of the track number to the display of the track feed speed on the two-digit 7-segment LED 25 shown in FIG. The track feed speed is changed by turning on the switch 56. #F-3 is provided so that the track feed speed is switched only when the switch 56 is turned on, turned off, and then turned on again as described above.

#F-4, #F-5, #F-6, #F-7: In these steps, the track feed speed setting switch 56 is turned on, and the 2-digit 7-segment LED 25 display shown in FIG. This switch is provided to stop setting the track feed speed if the switch 56 or any other switch is not turned on for a predetermined period of time (2 seconds) after switching from displaying the number to displaying the track feed speed. These are the steps that are being taken.

When the track feed speed setting switch 56 is turned on within a predetermined time (2 seconds) after the clock of timer 1 starts, the flow advances from #F-7 to #F-10 and time measurement of timer 1 is completed. When the switch is turned on or when another switch is turned on, the flow proceeds from #F-6 to #F-8.

#F-8: Clear the count value of timer 1.

#F-9: Contrary to #F-1, the two-digit 7-segment LED 25 shown in FIG. 3 returns to displaying the track number.

#F-10: Clear the count value of timer 1.

#F-11: Track feed speed setting value is single (once recorded or played back, the head is shifted by one track in field mode,
In the frame mode, the head is shifted by two tracks and then stopped). If it is a single, the flow advances to #F-12, and if it is not a single, the flow advances to #F-13.

As described above, when the flow reaches this step after the power switch 41 is turned on, the track feed speed is preset at 2 screens per second in #1.

#F-12: If the track feed speed setting value is single, change the setting value to 2 screens per second, return to #F-1, display the changed track feed speed, and repeat the steps from #F-3 to above. Execute #F-7.

#F-13: Track feed speed setting value is 2 per second
If the screen is 2 screens per second, go to #F-14, and if it is not 2 screens per second, go to #F-
The flow advances to 15.

#F-14: Track feed speed setting value 5 per second
Change the screen and return to #F-1, display the changed track feed speed, and return to #F-3 as described above.
~ Execute #F-7.

#F-15: Track feed speed setting value is 5 per second
If there are 5 screens per second, go to #F-16, if not 5 screens per second, that is, every second
If 10 screens are set, the flow advances to #F-17.

#F-16: Determine whether the PB mode flag is set. If the PB mode flag is set, that is, the playback mode is set, #F-18. If the PB mode flag is reset, that is, the recording mode is set, it is #F-19. The flow continues.

#F-17: Change the track feed speed setting value to single, return to #F-1, display the changed track feed speed, and proceed to #F-3~ above.
Execute #F-7.

#F-18: In the playback mode, regardless of whether the video signal recorded on the track of the magnetic sheet 1 is a field video signal or a frame video signal, field playback is performed during continuous track feeding. Therefore, in such a case, the track feed speed setting value is changed to 10 screens per second, and the flow returns to #F-1.

#F-19: Detects whether or not the field flag is set, and if the field flag is set, that is, if track advance is set at 5 screens per second in recording mode and in field mode, #F is detected. The flow branches to −18.

If the field flag is not set, that is, if the track feed speed setting value of 5 screens per second is set in the recording mode, and if the frame mode is selected, the flow advances to #F-17 and the track feed speed setting value is set to single. Change to

Therefore, in the subroutine described above, when the track feed speed setting switch 56 is turned on, the track feed speed is displayed on the 2-digit 7-segment LED 25 shown in FIG. the switch 56
The track feed speed is changed by turning on again.

In addition, the range of change is 3 types: single, 2 screens per second, and 5 screens per second when in frame recording mode, and 4 types: single, 2 screens per second, 5 screens per second, and 10 screens per second when not in frame recording mode. It is becoming.

The range of such changes is head 3-3 shown in Figure 1.
This relates to the track shift capability of the moving mechanism 1, 3-2, etc., and is set in advance to an appropriate range depending on the track shift capability.

Next, using FIG. 8, we will explain the subroutine that is called when the track UP switch 54 and the track DOWN switch 55 are turned on while the subroutine shown in FIG. 6 is being executed. First, the track UP switch 54 is turned on. This section explains the flow that is called when the

#D-1: When the flow reaches this step,
Whether or not the track being accessed by head 3-1 is the innermost track is determined by detecting whether register N is 50 or not.

As a result, if N is not 50, #D-2
If N is 50, the flow advances to #D-34, which will be described later.

#D-2: Determine whether the PB mode flag is set. When the PB mode flag is set, that is, in playback mode, #D-
When the PB mode flag is not set to #8, that is, when the recording mode is selected, the flow advances to #D-3.

#D-3: Detect whether the N+1 address of the memory is "0000", that is, the N+1 track is unrecorded, and if it is unrecorded, it is set to #D-4; if it is already recorded, it is #D-7. Flow branches.

#D-4: If it is determined in #D-3 that the N+1th track has not been recorded, it is determined in this step whether or not the field flag is set, and if it is set, it is determined. #D-6
If it is not set, the flow advances to #D-5.

#D-5: When it is determined in #D-4 that the field flag is not set and the frame mode is in effect, this step is reached. In this step, the memory N+
It is detected whether the second content is "0000", and if it is "0000", that is, if the N+2 track is unrecorded, go to #D-6;
If it is not "0000", that is, if the N+2 track has been recorded, the flow advances to #D-7.

By executing steps #D-3 to #D-5, if two consecutive tracks are unrecorded in frame mode, go to #D-6.
If at least one of the two consecutive tracks has been recorded, the flow advances to #D-7.

#D-6: Head 3- when in field mode
In the frame mode, the track being accessed by head 3-1 and the track being accessed by head 3-2, which is one track inner than this track, are unrecorded. In other words, if recording is possible, the flow reaches this step, and the REC shown in Figure 3 is executed.
LED44B lights up.

#D-7: Head 3-1, 3 opposite to #D-6
If the track that -2 attempts to access and record has already been recorded, the
By blinking the REC LED 44B, a warning is displayed to make the user aware that recording is not possible.

#D-8: If the PB mode flag was set in #D-2, the flow reaches this step and the field flag is set.

For the meaning of this step, see #D-9.
This will be explained in #D-10 and #D=13.

#D-9: Memory address N is “0011”, i.e. #13
As explained above, it is detected whether or not the track being accessed by the foot 3-1 is the outermost track of the two tracks that make up the frame video signal, and if it is the outermost track of the two tracks. If the track is not on the outer circumferential side, the flow proceeds to #D-13.

#D-10: Detects whether address N+1 of the memory is "0010", that is, the track being accessed by the head 3-2 is the inner track of the two tracks making up the frame video signal, If the track is on the inner side of the two tracks, go to #D-11; if it is not on the outer side, go to #D.
The flow advances to −13.

That is, if the inner track of the two tracks making up the frame video signal is erased, or if a new video signal is recorded after erasing, the track accessed by head 3-1 will make up the frame video signal. Even if the track is on the outer circumferential side of the two tracks, the track that the head 3-2 is accessing may not be the inner track among the two tracks. Therefore, in this case, when shifting the heads 3-1 and 3-2 to the inner circumferential side, it is necessary to shift only one track and reproduce the track on which the video signal is newly recorded after erasing or erasing. .

However, in such a case, the head 3-1,
When head 3-2 is shifted inward by one track, the frame video signal is not necessarily recorded on the track that heads 3-1 and 3-2 are accessing, and each head is recorded in a completely different field. In some cases, video signals are recorded. In this case, if the field flag is reset, a problem arises in that two separate field video signals are reproduced as a frame video signal. Therefore, by providing step #D-8 mentioned above, in this embodiment, when shifting the head toward the inner circumference side, the field mode is set by setting the field flag in advance in this step. In this case, it is possible to solve the problem that a completely different field video signal is reproduced as a frame video signal in the above case.

#D-11; In this step, register N is
49, and if N is 49, go to #D-13; if N is not 49, go to #D-12
The flow branches to

#D-12: The flow reaches this step when frame video signals are being recorded on the two tracks accessed by heads 3-1 and 3-2. When such a recording is made, when the track UP switch is turned on, the driver 23 is driven to shift the heads 3-1 and 3-2 by one track in this step, and then one more time in #D-13. Truck head 3-
Shift 1, 3-2. Further, as described above, N is updated by 1 each time the heads 3-1 and 3-2 are shifted.

#D-13; Similar to #D-12, head 3-1, 3-
2 by one track.

#D-14; Similar to #23, display N on the 2-digit 7-segment LED 25 shown in FIG.

In this embodiment, such steps are #D-12,
Since it is provided in the flow after #D-13, when a frame video signal is recorded on the track being accessed by heads 3-1 and 3-2,
The track number displayed on LED25 is 2.
When a field video signal is being recorded, the track number displayed on the LED 25 will be updated by 1, indicating whether the field video signal or the frame video signal is recorded on the magnetic sheet 1. can be displayed.

In addition, if this step is also provided between #D-12 and #D-13, if frame video signals are recorded on the two tracks being accessed by heads 3-1 and 3-2. Even trucks
When the UP switch 54 is turned on, the track number displayed on the LED 25 is updated one by one.

#D-15; Determine whether the PB mode flag is set. #D if set
-16, if not set, #D-19
Flow branches. If set, branch to #D-15-1.

#D-15-1; Here, the CPU 40 takes in the reproduction ID signal output from the data demodulator 12 in FIG. 1 into the RAM 27. The flow is #D-15-
Proceed to step 2.

#D-15-2; Here, it is determined whether the mode is one in which the ID is superimposed on the video signal and monitored. For details on such modes, see Section 2.
This will be explained using Figure 0. If it is in this mode, proceed to #D-15-3; otherwise, proceed to #D-15-4.

#D-15-3; When the flow reaches this step, the ID is superimposed on the video signal and monitored, so the CPU reads the reproduced ID signal from the RAM 27 and controls the character generator 40 to generate the character pattern. is generated and superimposed on the playback video signal on the monitor. Flow is #D-15-4
Proceed to. In other words, at this point, the track currently being accessed was recorded on the monitor.
The ID DATA signal will be displayed on the monitor.

#D-15-4: If the automatic track feed flag is not set, the flow branches to #D-20, and if it is, the flow branches to #D-16.

#D-16; Memory address N is “0011” head 3
It is determined whether the track being accessed by -1 is the outermost track among the tracks on which the frame video signal is recorded. Here N
As repeated above, head 3-1,
This corresponds to the track number that head 3-1 is accessing after moving head 3-2. Here, the content at address N of the memory is “0011”
If it is, the flow branches to #D-17. If it is not "0011", the flow branches to #D-19.

#D-17: Determine whether the contents of address N+1 of the memory are "0010", that is, the track being accessed by head-3-1 is the inner track of the two tracks where the frame video signal is recorded.

Here, if the N+1 address of the memory is "0010", the flow branches to #D-18, and if it is not "0010", the flow branches to #D-19.

#D-18; If the flow reaches this step via #D-16 and #D-17, heads 3-1 and 3
Since frame video signals are recorded on the two tracks accessed after the movement of D-2, the field flag set in #D-8 is cleared and the frame playback mode is set. Note that this step is executed only if the automatic track feed flag is set. (If the automatic track feed flag is not set, the flow branches from #D-15-4 to #D-20, so the field flag remains set in #D-8, so field playback is performed. ) #D-19: In this step, it is determined whether or not the automatic track feed flag is set, and if it is set, the process returns to #D-20, and if it is set, the process returns from this subroutine. (RTS).

The automatic track feed flag is a flag that is set in a subroutine that will be described later.
It is designed to help you escape from.

#D-20; Load the track feed speed setting value from memory.

#D-21; Determine whether the track feed speed setting value is single or not. If it is single, go to #D-34; if not, go to #D-
The flow branches to 22.

#D-22; Determine whether or not the track feed speed setting value is 2 screens per second. If it is 2 screens per second, flow to #D-23, and if not 2 screens per second, flow to #D-24. branches.

#D-23; Set the WAIT TIMER register in the CPU 40 to 28.

#D-24; Track feed speed setting value is 5 per second
The flow branches to #D-25 if there are 5 screens per second, and to #D-26 if there are not 5 screens per second.

#D-25; Set the WAIT TIMER register to 10.

#D-26: If 10 screens per second is set as the track feed speed setting value, the flow reaches this step and the WAIT TIMER register is set to 4.

Note that the WAIT TIMER register set in #D-23, #D-25, and #D-26 is used to control the track feed speed, and the DC The value is subtracted every time the magnetic sheet rotates once by the motor 2.

#D-27; Determine whether or not the REC execution flag is set, and if it is set, #D-27;
28, and when it is not set, the flow branches to #D-31. Here, the REC execution flag is a flag that is set in the subroutine, and is a WAIT flag that is set when the subroutine is called while running a program that repeats recording while automatically sending tracks.
This is provided to obtain the time equivalent to the time required for recording by subtracting 2 or 5 from the TIMER register in #D-29 and #D-30. That is, in the recording mode, the rotation state of the magnetic sheet 1 is detected from the PG coil 21 to determine the timing for recording the signal to be recorded from a predetermined position on the magnetic sheet, and to record the signal on the magnetic sheet 1. It is provided for.

#D-28 #D-29 #D-30; Through these three steps, it is determined whether or not the field flag is set. If it is set, 2 is subtracted from the WAIT TIMER register and the field flag is set. In case there is no
Subtract 5 from the WAIT TIMER register.
If 10 screens per second is set as the track feed speed, the WAIT TIMER register will be set to 4, but such a setting is only possible in field mode, so in this case, 5 will be set from the WAIT TIMER register. It is never subtracted.

#D-31; Detects whether or not there is a pulse from the reference signal generator 19 shown in Figure 1. If there is a pulse, go to #D-32; if not, go to #D-31. Repeat the flow.

#D-32; Subtract 1 from the contents of the WAIT TIMER register.

#D-33; Content of WAIT TIMER register is 0
Determine whether it has become 0, and if it is 0, #D-
34, and if it is not 0, branches to #D-31.

In steps #D-32 to #D-33, a timer is set to control the track feed speed.
WAIT TIMER register and reference signal generator 19
And so. Therefore, compared to the method of configuring a timer by subtracting the contents of the WAIT TIMER register according to the output of the waveform shaping circuit 22 that shapes the waveform of the output of the PG coil 21, stable and more accurate clock operation can be performed. I can do it. That is, PG coil 2
The output of the reference signal generator 19 may contain errors due to uneven rotation of the magnetic sheet 1, etc.
The output of is substantially free of such errors. Furthermore, when performing interval recording, it is desirable to stop the rotation of the DC motor 2 during the interval time in order to save power consumption. When performing such an operation, the method of subtracting the WAIT TIMER register according to the output of the waveform shaping circuit 22 does not allow the interval time to elapse; however, according to the method of this embodiment, when performing such an operation, Stable timekeeping operation can be performed even when

#D-34; Determine whether or not the REC execution flag is set, and if it is set, return (RTS) to the original program that called the subroutine; if not set, #D −
Branch to 35.

#D-35: Determine whether or not the track UP switch 54 is on, and if it is on, further shift the track accessed by the heads 3-1 and 3-2 to the inner circumferential side. #D to do
-1, and when it is off, the flow branches to #D-36.

#D-36; To determine whether the track DOWN switch 55 is on or not, and when it is on, shift the track accessed by the heads 3-1 and 3-2 to the outer circumferential side. When the subroutine is off, the subroutine branches to #D-37.

#D-37: If the PB mode flag is set, go to #D-38; otherwise, go back to the program that called the subroutine.

#D-38 #D-39 #D-40; Similarly to D-6, 17, and 18, in the case of a video signal recorded in frames, the field flag is cleared for frame playback. Thereafter, the process returns to the pologram that called the subroutine.

In the above example, #D-12 in PB mode
Regardless of whether the track passes through #D-12 or not, the value set in WAIT TIMER is not changed in #D-23, 25, and 26, so #D-12 is passed for the time it takes to perform one track feed. If this happens, the track feed speed will be delayed, but in order to match this,
At #D-27, if #D-12 is passed, the time required to feed the head for one track is
If you subtract it from the WAIT TIMER, you can match the track feed speed without any problems.

Next, a subroutine executed when the track down switch 55 is turned on will be explained.

Each step of the subroutine #E-1 to #E-
13 are each subroutine step #D-1~
Since this is the same step as #D-13, detailed explanation will be omitted.

However, the subroutine is executed when the track DOWN switch 55 is turned on.
For example, in #E-1, it is detected whether N=1, and in #E-9, the memory (N-
1) Detect whether the battery is "0010", that is, the (N-1)th track is the inner track of the two tracks constituting the frame video signal, and in #E-10, the memory address (N-2) is detected. Detects whether or not the (N-2)th track on the "0011" side is the outer track of the two tracks constituting the frame video signal, and whether or not N=2 in #E-11. is detected, and in #E-12 and #E-13, the heads 3-1 and 3-2 are shifted by one track toward the outer circumferential side.

Next, using FIG. 9, the subroutine called when the field/frame changeover switch 59 and the REC mode setting switch 51 are turned on,
I will explain about it.

#J-1: When it is detected in #A-10 shown in FIG. 6 that the field/frame changeover switch 59 is turned on, the flow advances to this step, and the field flag is set in this step. If there is, go to #J-2,
If not set, the flow branches to #J-4.

#J-2; If the field flag was set in #J-1, the field flag is cleared in this step.

#J-3; Determine whether or not the PB mode flag is set, and if it is set, #J
-8, and if not set, the flow branches to #J-5.

#J-4: When it is detected in #J-1 that the field flag is not set, the field flag is set in this step.

If the PB mode is not set, that is, in the recording mode, and the field flag is cleared in #J-2, the frame recording mode is entered, and as explained in the subroutine, 10 frames per second are continuously recorded. I can't. Therefore, when switching from field mode to frame mode in a subroutine, if the track feed speed is set to 10 screens per second,
Such switching should be prohibited.

Therefore, according to this embodiment, #J to be explained next
-6 and #J-7, when a track feed speed of 10 screens per second is set, the track feed speed setting value is automatically changed to a track feed of 5 screens per second.

#J-5; CUP track feed speed setting value
Incorporate into 40.

#J-6: If the track feed speed setting value taken in #J-5 is 10 screens per second, the flow branches to #J-7, and if it is not 10 screens per second, the flow branches to #J-8.

#J-7; Set track feed speed to 5 per second.
Change to screen.

#J-8; Field/frame setting switch 5
If 1 continues to be on, this step will be repeated, and only when it turns off from on will the 6th
Return to step #A-1 in the figure.

Next, a subroutine called when the REC mode setting switch 51 is turned on will be explained.

#B-1; In #A-1 shown in Figure 6
When it is detected that the REC mode setting switch 51 has been turned on, the flow branches to this step, the PB and LED 44A shown in FIG. 3 are turned off, and the PB mode flag is cleared.

#B-2 #B-3 #B-4 #B-5 #B-6; These five steps are the same as #D-3 to #D-7 shown in Figure 8, so explanations will be omitted. Omitted.

#B-5-1: In this step, the CPU 40 controls the character generator 84 to temporarily stop generating characters.

#B-5-2; Determine whether or not it is in ID setting mode, and if it is in setting mode, #B-5
Proceed to -3, otherwise proceed to #B-6'.

#B-5-3; The CUP 40 reads the set ID from the RAM 27 and controls the character generator 84 to generate a character pattern. Therefore monitor 1
3, the ID is displayed superimposed on the video signal input from the video signal input terminal 18. The flow then proceeds to #B-6'.

#B-6'; Repeat this step while the REC mode setting switch 51 continues to be turned on.
When the switch is turned off, the flow branches to #B-7.

#B-7; When the REC mode setting switch 51 is turned off, it is determined in this step whether the field flag is set, and if the field flag is set, #A-
The flow returns to step 1, and if the field flag is not set, jumps to subroutine #J-5, and steps #J-6 to #J
By executing -8, when the track feed speed setting value is 10 screens per second, it is automatically corrected to 5 screens per second. Therefore, when the REC mode is set by the REC mode setting switch 51 and the frame mode is set, the track feed speed setting value is limited to a maximum of 5 screens per second.

Next, a subroutine called when the PB mode setting switch 53 is turned on will be explained using FIG. 10.

#C-1; PB in #A-3 shown in Figure 6
When it is detected that the mode setting switch 53 is turned on, the flow branches to this step.
The REC LED is turned off and the field flag is temporarily set. That is, separate field video signals are recorded on the two tracks being accessed by heads 3-1 and 3-2, and a frame recording mode is set in which the PB mode flag is cleared and the field flag is reset. In this case, when it is detected that the PB mode setting switch 53 is turned on and the track being accessed by the heads 3-1 and 3-2 is immediately played back, separate field video signals are prevented from being played back in an interlaced manner. In order to do this, a field flag is once set in this step.

#C-2; Detects whether the memory address is "0011", that is, the track being accessed by head 3-1 is the outermost track of the two tracks on which the frame video signal is recorded, and the memory address is "0011". If it is, go to #C-3. If it is not "0011", go to #C-5.
Flow branches.

#C-3; Detects whether the memory address N+1 is "0010", that is, the track being accessed by the head 3-2 is the inner track of the two tracks on which the frame video signal is recorded, and sets it to "0010". If it is, go to #C-4 If it is not “0010”, go to #C-
The flow branches to 5.

#C-4; Head 3 in #C-2 and #C-3
When it is detected that frame video signals are recorded on the two tracks being accessed by -1 and 3-2, the flow reaches this step, the field flag is cleared, and the frame mode is set. .

#C-5: The PB and LED 44A shown in FIG. 3 light up, the PB mode flag is set, and the playback operation is started.

#C-5-1: In this step, the CPU 40 controls the character generator 84 to temporarily stop generating characters. In addition, the CPU 40 is a data demodulator 12
The demodulated ID DATA is stored in the RAM 27.

#B-5-2; Determine whether or not it is the ID display mode, and if it is the display mode, #C-5-
If not, proceed to #C-6'.

#C-5-3; The CPU 40 reads the ID demodulated by the data demodulator 12 from the RAM 27,
A character generator 84 is controlled to generate a character pattern. Therefore, the ID is displayed on the monitor 13 superimposed on the video signal reproduced from the magnetic sheet. Flow then proceeds to #C-6.

#C-6; If the PB mode setting switch 53 continues to be turned on, repeat this step, and if it is turned off, #A-14 shown in Fig. 6
Return to #A-1 via.

Next, a subroutine called when the interval time setting switch 57 is turned on will be explained using FIG. 11. First, in subroutine #G-0, a timer T' is initialized to 0, and an interval time Ti is displayed on the 7-segment LED 25.

#G-1: When it is detected that the interval time setting switch 57 is turned on in #A-7 of FIG. 6, the timer T' is initialized to 0, and the flow then reaches this step. 10 more
When the key switches 63 to 72 are turned on, the flow branches to #G-2, and when the ten key switches 63 to 72 are not turned on, the flow branches to #G-3.

#G-2; Change the interval time Ti to the interval time Ti set by the 10 key switches 63-72.

#G-3; Determine whether any switches other than the 10 key switches 63 to 72 are turned on or not. If they are turned on, branch to #G-4. If not, branch to #G-5. .

#G-4; Detects whether or not the interval time setting switch 57 is turned on. If it is turned on, the switch #G-1 is turned on; if it is not turned on, the switch #A-1 shown in FIG. The flow branches.

#G-5: Increase the aforementioned T' by 1. The flow moves to #G-6 every second.

However, T' is a timer that is incremented by 1 every second, and no addition is made unless one second has elapsed.

#G-6; Determine whether T' is 10 or not, and if T' is
In the case of 10, in #A-1 shown in Figure 6,
If T′ is not 10, branch to #G-1,
The aforementioned #G-1, #G-3, #G-5 and #G
-6 loop is repeated until T' reaches 10, returning to #A-1.

Therefore, in the above subroutine, if no other switch is turned on within 10 seconds after the interval time setting switch 57 is turned on, the process returns to #A-1 shown in FIG. 6 and the interval time setting is canceled. . While the subroutine is being executed, the interval time Ti is of course displayed on the two-digit 7-segment LED 25, but the display of the interval time Ti is stopped when returning to #A-1 at #G-6.

In addition, when the interval time Ti is set to "0" in this subroutine, an external trigger mode is set that causes an operation to be performed when connecting to a printer, for example, as described in the subroutine as a reproducing operation.

Next, the subroutine called when the REC switch is turned on will be explained using FIG. 12.

#N-1: When it is detected in #A-2 of FIG. 6 that the REC switch 52 is turned on, the flow reaches this step, and it is detected whether the PB mode flag is cleared, When it is not cleared, the flow returns to #A-14 shown in FIG. 6 (RTS) because it is in the playback mode, and when it is cleared, the flow branches to #N-2. Therefore, if the REC mode is not set, no recording will be performed even if the REC switch 52 is turned on.

#N-2; It is determined whether the N address of the memory is "0000", that is, whether the track being accessed by the head 3-1 is unrecorded or not. If it is not unrecorded, the process shown in FIG. 6 is performed. The flow returns to #A-14, and if it is unrecorded, the flow branches to #N-3.

#N-3; It is determined whether the field flag is set, and if it is set, the flow branches to #N-5; if it is not set, the flow branches to #N-4.

#N-4: This step is entered when the frame recording mode is set, but if address N+1 of the memory is "0000" or the track being accessed by head 3-2 is unrecorded. If it is determined whether or not it is unrecorded, the flow returns to #A-14 shown in FIG. 6. In such a case, the REC and LED 44B are blinking in advance.

If such a track is unrecorded, the flow branches to #N-6.

#N-5; 1 per track on magnetic sheet 1
The video signal for the field is recorded by the head 3-1. At this time, SW6 shown in Figure 1
is turned off, and the output of the character generator 84 is no longer output to the monitor. Also, 0001 is set in memory address N.

#N-6: When the flow reaches this step, the frame recording mode is set, so the video signal for one field is sent to the two tracks on the magnetic sheet 1 to the heads 3-1 and 3-2. 0011, N+1 is recorded at memory address N.
0010 is set in the base and SW6 is set like #N-5.
is turned off. Next, the step motor 24 is driven to shift the heads 3-1 and 3-2 inward by one track.

In addition, when executing #N-5 and #N-6, SW2~
SW5 is driven as explained in FIG. Also, when recording is executed in #N-6, the ID set from RA27 by CPU40
is read out and outputted to the data modulator 14, whereby the ID modulated into a DPSK signal is input from the data modulator 14 to the recording amplifier 16, where it is superimposed on the video signal and ID recording is performed.
However, the ID display mode will be explained later in Figure 20 c)
In this case, even if the data is set, the ID
will not be recorded. However, DATA indicating whether the frame is inside track, outside track, or field recording is simply recorded together with the video signal. Furthermore, even in the display modes shown in Fig. 20a and b, by executing #N-5 and #N-6, the ID DATA signal is displayed on the monitor because SW6 is turned off during recording. will no longer appear.

#N-7: The REC execution flag is set and SW6 in FIG. 1 is turned on.

By executing #N-1 to #N-7,
When the set ID is generated by the character generator 84, superimposed on the video signal, and output to the monitor, the character signal generated only during REC execution is turned off by SW6 in FIG. As a result, the characters will disappear. #N-7
ID again because SW6 is turned on again at
DATA is displayed.

#N-8; Call subroutine, head 3
If -1 is accessing a track other than the 50th track, the flow moves from #D-1 and #D-2 to #D-3. Next, execute #D-3 to #D-14 to move the heads 3-1 and 3- to the inner circumferential side by one track.
Move 2. In the frame recording mode, the heads 3-1 and 3-2 have been moved inward by one track in #N-6, so even in the frame recording mode, the heads 3-1 and 3-2 are moved inward by #D-6.
Access the track next to the track recorded in step 14. Further, when the tracks recorded by the heads 3-1 and 3-2 have been recorded, the REC shown in FIG. 3 and the LED 44B blink to warn the user.

Next, the flow branches from #D-15 to #D-19, and the flows shown in #D-20 to #D-34 are executed via #D-19.

That is, if the set value of the track feed speed is single, the flow branches from #D-21 to #D-34, and according to the REC execution flag set in advance in #N-7, the flow branches to #N-9. Return to

If 2 or 5 screens per second is set, only the time required to record with #D-28
WAIT TIMER register is subtracted and WAIT
Count down the TIMER register and WAIT
When the TIMER register becomes 0, the flow returns from #D-33 to #D-34 to #N-9 in accordance with the REC execution flag set in #N-7 as described above.

#N-9; Clear the REC execution flag.

#N-10: This step is similar to #D-20, and the set value of the track feed speed is read from the memory.

#N-11: If the set value of the track feed speed is single, go to #N-12; if not, go back to #A-14 shown in FIG.

#N-12: When the track feed speed is set to single, this step is repeated as long as the REC switch 52 is turned on, and the subroutine is executed again to control so that no recording is performed.

When the track feed speed is set to other than single and the REC switch 52 is turned on, #A-11 to #A-14 are
1. The sample routine is called from #A-2, the above-described flow is executed, and as long as the REC switch 52 is on, recording is performed continuously at the set track feed speed. If the REC switch 52 is turned off, the flow will be #A-14, #A-1, #A
-2, but the continuous recording ends without calling the subroutine at #A-2.

Next, a subroutine called when the program setting switch 58 is turned on will be explained using FIG. 13.

#H-1: When it is detected that the program setting switch 58 is turned on in #A-8 of FIG. 6, this step is reached, and it is determined whether the PB mode flag is set and the When it is set, the process returns to #H-2, and when it is not set, the process returns to #A-1 shown in FIG. 6 (RTS). This step is provided to prohibit program settings in recording mode. That is, in this embodiment, when setting a program, the playback mode is selected in advance, so that the program setting is performed while checking the video recorded on the magnetic sheet 1 on a monitor, for example. .

Further, by automatically setting the PB mode flag when the program setting switch 58 is turned on, the operation to the reproduction mode can be performed automatically. In this case, a step similar to the step shown in the subroutine, that is, a CALLC that calls the subroutine may be provided in place of the step shown in #H-1.

#H-2: When a program is reproduced in the program track memory shown in FIG. 14 where the program is stored, the I register indicating the address where the track number to be reproduced next is stored is set to 0.

#-3; Set the program playback mode flag indicating that the program is in program playback mode and press #A.
Return to -1.

Next, a subroutine called when the program track setting switch 62 is turned on after the program reproduction mode is set by the subroutine will be described with reference to FIG.

#I-1; Determine whether the program playback mode flag is set; if it is set, go to #I-2; if not, go to #A
The flow branches to -1. Therefore, when the program playback mode is not set by the program setting switch 58, no program setting operation is performed even if the program track setting switch 62 is turned on.

#I-2; Register S indicating the start address where the program of the program track memory mentioned above is stored (S=
(initialized as 0) is written to register M.

#I-3: Store the program track memory data at the address stored in register M at an address that is 1 larger than the address. In other words, the data indicating the track number stored in the program track memory is stored at an address that is 1 larger than the address where the data is stored.

#I-4; Write the value obtained by adding 1 to the contents of register M to register I.

#I-5; Subtract 1 from the contents of register M.

#I-6: Determine whether the contents of register M are 0 or not. If the content is 0, the flow branches to #I-7, and if it is not 0, the flow branches to #I-3.

The flow from #I-3 to #I-6 is repeated, and when the contents of register M become 0, all data stored at each address in the program track memory is transferred to an address larger by 1. Therefore, repeat this flow and #I-
When the flow branches from #6 to #I-7, no data is stored at address 1 of the program track memory.

#I-7: The number of the track being accessed by the head 3-1 is stored at address 1 of the program track memory. Therefore, by turning on the program track setting switch 62, the number of the track on which the video being accessed and reproduced by the head 3-1 is recorded is programmed.

#I-8; Add 1 to the contents of register S. By executing this step, the start address (largest address) where the program track memory data moved by executing flows #I-3 to #I-6 is stored is always stored in register S. will be done.

#I-9; Program track setting switch 62
If it is turned on, repeat this step, and if it is turned off, return to #A-1.

If the user wants to continue setting the program, turn on the track UP switch 54 or track DOWN switch 55 to change the track being accessed by the heads 3-1 and 3-2 and set the desired one. Once the track has been played back, program settings can be made by turning on the program setting switch 62 while checking the played video.

It should be noted that each time the program setting switch 62 is turned on, the data stored in each address of the program track memory shown in FIG. 14 is stored in a larger address one by one. Also, during program setting, register S and register I have exactly the same contents.

Next, by turning on the program setting switch 58 and the program track setting switch 62, program playback is performed to play the program set, and recorded tracks are set in order from the track being accessed by the head 3-1. A program that is executed when performing interval playback in which playback is performed at an interval time will be described with reference to FIGS. 16 to 18.

First, the subroutine called when the start switch 60 is turned on will be explained using FIG. 16.

#K-1: When it is detected that the start switch 60 is turned on in #A-11 of FIG. 6, the flow reaches this step, and it is detected whether the PB mode flag is set and the PB mode flag is set. #A- when the mode flag is not set
1, and when the PB mode flag is set, the flow branches to #K-2. Therefore, in this embodiment, if the playback mode is not set in advance, interval playback or program playback cannot be performed, so even if the start switch 60 is turned on by mistake during the recording mode, interval playback or program playback will not be possible. can be prevented from starting. Also #K-1
If a step similar to the step shown in the subroutine is provided instead, it is possible to immediately start playing the interval playback program simply by turning on the start switch 60 without setting the playback mode in advance.

#K-2; Determine whether the program playback mode flag is set or not; if it is set, go to #K-3; if not set, go to #K
The flow branches to -4. Here, the flow will be explained when the program playback mode flag is not set, that is, when interval playback is performed.

#K-4; Determine whether the memory address N is "0000", that is, the track being accessed by head 3-1 is unrecorded, and if it is unrecorded, #K
-6 If not recorded, the flow branches to #K-5. First, assuming that the track being accessed by head 3-1 is unrecorded, #K-
6 and below will be explained.

According to this embodiment described below, when the track being accessed by the head 3-1 is other than the 49th or 50th track, the interval playback is performed from that track to the track being accessed by the head 3-1. When it is the 49th or 50th track, only the tracks that have been recorded sequentially from the 1st track are played back, but between #K-2 and #K-4, the head 3-1 is set to the 1st track. If a step is inserted to drive the step motor 24 so as to access the tracks, only the recorded tracks are always reproduced sequentially starting from the first track.

Therefore, when the head 3-1 is not accessing the first track but is accessing another track, it is extremely effective to perform a search by automatically performing interval playback sequentially from the first track. It's expensive.

#K-6; Set the automatic track feed flag indicating that interval playback is in progress.

#K-7; Determine whether or not the field flag is set, and if it is set, #K
-8, the flow branches to #K-9.

#K-8; Determine whether or not the track being accessed by the head 3-1 is the innermost track by detecting whether N is 50.
If it is detected, go to #K-10, 50
#K-11 when it is not detected that
Flow branches.

#K-9; Determine whether or not the track being accessed by the head 3-1 is a track located one point outside the innermost circumference by detecting whether N is 49; #K-10 when detected
#K if 48 is not detected.
The flow branches to −11.

#K-10: In this step, it is determined whether or not the interval time Ti set by executing the subroutine is "0". As will be described later, when the interval time Ti is "0" and when the head 3-1 is shifted according to a preset program according to an external trigger signal, the interval time Ti is "0". ”, the flow branches to #A-1, and when it is not set to “0”, the flow branches to #K-12.

#K-11; Call subroutine, #D-1
The flow shown in ~#D-18 is executed. When the subroutine is called in the subroutine, the PB mode flag is set, so the flow branches from #D-2 to #D-9.
The track accessed by the head 3-1 in #K-4 is on the outer side of the frame and one track inner than this track, and is the inner track of the two tracks on which the frame video signal is recorded. When it is determined that head 1 is not accessing the 49th track, head 3-1,
If 3-2 is shifted to the inner circumference side by 2 tracks by #D-12 and #D-13 and cannot be determined, #D
-13, heads 3-1, 3 for one track only
-2 is shifted to the inner circumferential side. Also head 3-
If a frame video signal is recorded on the accessed track 1 or 3-2, the field flag is cleared and the flow moves from #D-19 to #K-
Move to 14.

#K-12; Call subroutine #E-1~
The flows shown in #E-13 and #D-14 to #D-19 are executed, and the track on the outer circumference adjacent to the track accessed by the head 3-1 in #K-4 and the track on the outer circumference by one more track are executed. When frame video signals are recorded on two of the tracks, heads 3-1 and 3-2 are #E-12 and #E
-13, it is shifted to the outer circumference by two tracks,
In other cases, only one track is shifted toward the outer circumference by #E-13.

Similarly to #K-11, if a frame video signal is recorded on the tracks being accessed by 3-1 and 3-2, the field flag is cleared and the flow moves from #D-19 to #K-13.

#K-13; Determine whether the track being accessed by head 3-1 is the outermost track by detecting whether the content of register N is 1, and determine whether it is 1. When 1 is detected, the flow branches to #K-14, and when 1 is not detected, the flow branches to #K-12. Therefore, if the flow branches to #K-12 at #K-8 or #K-9, that is, bed 3-1 becomes the 49th bed.
When accessing the track or the 50th track, the head 3-1 is controlled to access the first track by repeating steps #K-12 and #K-13.

#K-14; Clear the automatic track feed flag.

As explained above, the flow from #K-4 to #K-14 is executed, and when the flow branches from #K-4 to #K-5, the head 3-1 connects the track on which the video signal is recorded. Tracks on which no video signals are recorded are essentially skipped without being played back.

Furthermore, by executing flows #K-4 to #K-14, when the flow branches from #K-4 to #K-5, the two tracks being accessed by heads 3-1 and 3-2 are If a frame video signal is recorded, the field flag is cleared in #D-18, so the frame playback mode is automatically set. Also, heads 3-1, 3-2
When a field video signal is recorded on the track being accessed, the field playback mode is automatically set. Therefore, during interval playback, the most appropriate playback mode is automatically set according to the recording method of the video signal.

#K-5; The interval time Ti set in the subroutine is fetched from the memory into the register T' of the CPU 40.

#K-15; Interval time like #K-10
Detect whether Ti is “0” and if it is “0”, go to #K-17, if it is not “0”, go to #K-
The flow branches to 16. Here, #K-16 and subsequent steps will be explained assuming that the external trigger mode is not set.

#K-16; Start timer 1 timing operation, #K
Proceed to −18.

#K-18; Detects whether or not the timer 1 has counted one second. If the time has been counted, the flow branches to #K-19, and if the time is in the middle of counting, the flow branches to #K-20.

#K-20; Detects whether the stop switch 61 is on, and if it is on, #A-1
However, when it is not turned on, the flow branches to #K-21. Here, when the flow branches to #A-1, the steps from #A-1 to #A-12 are executed again, so when the stop switch 61 is turned on in the normal state, the flow branches to #A-12. The subroutine will be called from. The subroutine will be explained below using FIG. 17.

#M-1; Detects whether or not the program playback mode flag is set. If it is not set, go to #A-14; if it is set, go to #M-1.
The flow branches to 2.

#M-2; Detect whether the program playback execution flag is set. If it is set, go to #M-3; if not set, go to #M-4.
Flow branches.

#M-3; Make the contents of register I the same as the contents of register S.

#M-4: Set register S to 0 and then execute #M-3.

Such subroutines will be further detailed in the program playback mode. Below, #K-21 and later will be explained in detail.

#K-21; Detects whether the track UP switch 54 is on, and when it is detected that it is on, calls a subroutine to the head 3-1,
3-2 is shifted to the inner circumferential side and when it is not detected that it is on, the flow branches to #K-22.

#K-22; Detects whether the track DOWN switch 55 is on, and when it is detected that it is on, calls a subroutine and switches the head 3
-1 and 3-2 are shifted to the outer circumferential side, and when it is not detected that they are on, the flow branches to #K-18.

#K-19; Subtract 1 from T'.

#K-23; When T′ is “0”, to #K-24,
When T' is not "0", the flow branches to #K-16.

Therefore, by executing steps #K-15 to #K-23 described above, the track UP switch 54 and track DOWN switch 5 are turned off during interval playback.
By turning on 5, the video recorded on the track adjacent to the track being played back can be played back. In that case, by keeping switch 54 or switch 55 on, the tracks being played can be automatically updated sequentially according to the track feed speed set in the subroutine, and during interval playback, You can also easily play the video a few screens earlier.

In addition, the truck UP switch 54,
When the DOWN switch 55 is turned on to play back the video recorded on the track adjacent to the track being played back, in this embodiment, the track being played back before the switches 54 and 55 are turned on is played. interval time Ti
When the remaining time is played, the flow is #K
-23 to #K-24 and the playback is updated to a new track, but as shown by the dotted line in Figure 16, if the flow is jumped to #K-5, the interval time T' is reset. Te switch 54,
55 can be reliably observed for a certain period of time.

#K-24; When updating the track to be played after the interval time T' ends, detect whether the program playback mode is set;
When set, the flow branches to #K-3, and when not set, the flow branches to #K-6.

Next, the routine that branches when the program playback mode flag is set in #K-2 will be explained with reference to FIG.

#O-1; Detects whether the contents of register S is “0” and when “0” is detected, #A-
#O when it is detected that it is not “0” to 1
The flow branches to -2. As mentioned above, register S stores the start address of the program in the program track memory, and the content of register S is "0" if no program is stored in the program track memory. Therefore, when the value is "0", the process returns to A in FIG.

#O-2; Detects whether the contents of register I are “0” and when “0” is detected, #O-2;
3, and when it is detected that it is not "0", the flow branches to #O-3.

As mentioned above, register I stores the address of the track memory where the next track number to be played is stored when program playback is executed, and as shown in #O-14 below, when program playback is executed. 1 is subtracted each time one step program playback is executed. Therefore, the reason why the flow branches to #O-2 and register I is detected as "0" is because register S, where the program is set, is not "0" and all steps of program playback are executed. It shows that you have done something wrong. In other words, the flow branches to #O-3 when the program playback has been executed once, and to #O-5 during the program playback.

#O-3; Import the interval time Ti set in the subroutine and set the interval time.
It is detected whether Ti is "0", and if it is "0", the flow returns from the routine to #A-1 and ends the program playback operation.

Therefore, in the external trigger mode set by setting the interval time to "0", the program playback operation is stopped after the program playback has been executed once.

Further, during normal program playback when the interval time Ti is set to a value other than "0", the flow shifts to #O-4.

#O-4; Write the contents of register S to register I.

Program operation is started again.

#O-5; Program track memory address data set in register I ()
(The data written to the address set in register I of the program track memory is shown with a bracket around I).

#O-6; If data () is subtracted from N indicating the track number currently being accessed by head 3-1 and it is not less than "0", then #O-7
, if it is smaller, the flow branches to #O-8.

#O-7; Set field flag. This set is to prohibit head feeding in the frame mode like #D-8.

#O-8; Heads 3-1 and 3-2 1 in the outer circumferential direction
Shift by track.

#O-9; Detect whether the data () is equal to N indicating the track number that the head 3-1 is accessing. If they are equal, check #O-10. If not, that is, the data () is greater than N indicating the track number. ) is larger, the flow branches to #O-11.

#O-10; Heads 3-1 and 3-2 1 in the inner circumferential direction
Shift by track.

#O-11 #O-12 #O-12; This is the same step as #D-16, #D-17, and #D-18, and the video signal recorded by this step is a frame video signal or a field video signal. Frame playback and field playback are automatically performed depending on the situation.

By repeating steps #O-6 to #O-10, the head 3-1 is controlled to access the tracks programmed in the program track memory.

#O-14; Subtract 1 from register I.

#O-15; Program playback execution flag is set. This step allows the flow to be branched by determining whether the program reproduction mode flag is set at #K-24. The flow then jumps to #K-5.

Therefore, when branching to the routine at #K-3, it is first determined whether or not a playback program is actually set, and then it is determined whether or not the external trigger mode is set. When set, the program will only be executed once; otherwise, the program will be played repeatedly.

Next, a flow when the external trigger mode is set will be explained. When the external trigger mode is set, the flow branches from #K-15 to #K-17.

#K-17'; Detects whether the printer connected as an external device is busy (executing a printer operation) or not. If it is busy, the signal is #A-1; if it is not busy, the signal is #K-1. The flow branches at 18′.

#K-18': Send a print start signal to the printer as an external device. The print start signal is executed by setting the signal level of the terminal connected to the printer to H level.

#K-19'; Wait for 150msec #K-20'; When the printer is busy, #K-
21', and if not busy, the flow branches to #K-24.

#K-21'; Detects whether or not the stop switch 61 is turned on, and if it is not turned on, #K
-20', and when turned on, the flow returns to #A-1.

When executing #K-17' to #K-21' above, if the printer connected as an external device is busy, the flow returns to #A-1 as described above and other switches are activated again. 16th until turned on
Repeat the flow shown in the figure. If the start switch 60 is turned on again while repeating the flow shown in FIG. 16, the aforementioned flow is repeated.
#K-17' will be executed again.

When no printer is connected as an external device, the terminal to which the signal from the busy signal output terminal of the printer 13' shown in FIG. 1 is input is opened at #K-17' and becomes H level.
Therefore, if a device such as a printer is not connected even though the external trigger mode is set, the track being accessed by heads 3-1 and 3-2 will continue to be played. The existing tracks will not be updated.

Also, if a printer is connected as an external device and the printer is not busy, #K-
When the flow progresses from 17' to #K-18', printer operation is started after waiting 150mspc shown in #K-19 after sending the print start signal to the printer, and if the printer becomes busy. #K-20', #K until the printer operation is completed or the stop switch 60 is turned on.
-21' is repeated, and when the printer operation is finished, the flow branches from #K-20' to #24, and program playback is set by detecting whether the program playback mode flag is set. Determine whether the Here, if program playback is set, the flow branches to #K-3 described above, and if program playback is not set, the flow branches to #K-6. Further, when the stop switch 60 is turned on, the flow is as described above.

Also, if external trigger mode is selected when program playback is set, #O-
As explained in Section 3, once the program playback has been executed once, the program playback operation is stopped.

Further, according to this embodiment, even when the external trigger mode is selected and the program playback is not set, since #K-10 is provided, the heads 3-1 and 3-2 The playback operation is stopped after the playback is performed in sequence from the track being accessed to the last track.

Therefore, in external trigger mode, even if program playback is set or not, the playback operation will stop after one round of playback has been performed, so devices that use external triggers When a printer is used as a printer, only one print is performed.

On the other hand, in modes other than external trigger mode, even if program playback is set or not, playback will start again from the beginning after playback has been performed in a predetermined order. will be held. Therefore, when such a playback device is used in a mode other than the external trigger mode, so-called endless playback can be performed because playback is repeatedly performed in a predetermined order.

Further, although a printer is shown as the external trigger device in this embodiment, it may be a device having an electric transmission function, or any other device as long as it processes a reproduced signal.

Next, the case of setting ID will be explained.

In the flow of 10 key switches 63-72
When turned on, the flow branches to a subroutine shown in FIG.

#R-1: If the PB mode flag is set, branch to #R-10 and return to the flowchart. Therefore, even if the 10 key is turned on in a mode other than recording mode, virtually nothing is executed in this subroutine. If the PB mode flag is not set, that is, if it is in the recording mode, the flow branches from #R-1 to #R-2.

#R-2; Here, it is determined whether the ID setting mode is selected, that is, the ID is superimposed on the video signal to monitor the mode. The method for setting this mode will be described in detail with reference to FIG. 20. If you are not in this mode, #R-
10 and returns to #A-1 of the flowchart shown in FIG. If the mode is set, the process branches to #R-3.

#R-3; The CPU 40 reads the set position from the register P of the RAM 27, which is used to store the set position indicating where on the monitor the ID set here is to be displayed, and selects one of the 10 key switches 63 to 72. Data corresponding to the turned-on switch is written to the address of the RAM 27 corresponding to the set position. Then CPU
40 is monitor B according to the read set position
character generator 84 to display said data on the
control.

#R-4; Here, the process waits until the 10 key switches 63 to 72 are turned off once. If the switches that were turned on are turned off, the flow advances to #R-5.

#R-5; Here, the setting position of the data other than the date in I is from 0 to 10 as shown in Figure 21.
Since it is 11 points, register P is now
If it is equal to 10, branch to #R-6; otherwise, branch to #R-7.

#R-6; Here, register P is set to 0,
The setting position of DATA is initialized.

#R-7; Here, 1 is added to the value of register P.
The DATA setting position moves to the next setting position.

#R-7-1; Data at the position stored in register P blinks (blinks).

#R-8; In this step, it is determined whether or not the 10 key switches 63 to 72 are turned on. If they are turned on, the process branches to #R-3 and the 10 key switches 63 to 72 are turned on according to the flow described above. The ID set by is displayed on the motor 13. If it is not turned on, #R-
Branches into 9.

#R-9; Here, it is determined whether any switches other than the 10 key switches 63 to 72 are turned on, and if they are not turned on, the process branches to R-8. If it is turned on, it branches to #R-11.

#R-9-1; Stop blinking the ID displayed on the monitor. Flow proceeds to #R-10.

#R-11; Here, register P at the ID setting position
Set O to initialize the ID setting position and press #R.
Proceed to -9-1.

Return to the flow of #R-10;

As explained above, when the PB mode flag is not set and the ID is in the ID setting mode, that is, the mode in which the set ID can be monitored,
Each time the 10 key switches 63 to 72 are turned on, the CPU 40 controls the character generator 84 to generate the data corresponding to the switch at the position determined by the register P.

Next, the ID switch 73 will be explained.

When the switch 73 is turned on, the subroutine shown in FIG. 20 is called from the flow shown in .
Here, the subroutine will be explained.

#Q-1; Here, it is determined whether or not the PB mode flag is set. If it is set, the process branches to #Q-2; otherwise, the process branches to #Q-7.

#Q-2; Here, check whether it is in ID display mode or not.
That is, it is determined whether the mode is such that the ID is output on the monitor superimposed on the video signal. #Q-4 if in ID display mode
Otherwise, branch to #Q-3.

#Q-3; Here, the CPU 40 is the character generator 84
is output from the generator 84 by controlling
Stop displaying ID. From here, the flow advances to #Q-6.

#Q-4; Here, CPU40 is from RAM27,
The reproduced ID is taken into the CPU 40, and the flow advances to #Q-5.

#Q-5; Here, the CPU 40 controls the character generator 84 based on the reproduced ID, and causes the character generator 84 to output the reproduced ID as a character pattern as shown in FIG. 21a. The flow then proceeds to #Q-6.

#Q-6: Here, if the switch 73 is turned on, the process waits; if it is turned off, the flow advances to the next step and returns to the flow of step .

#Q-7; When the PB mode flag is not set and the recording mode is selected, it is determined whether the mode is ID setting mode or not. That is, ID is character generator 8
#Q if the mode is superimposed on the video signal and output as a character pattern according to 4.
The flow advances to -9. If not, #Q
The flow advances to -8.

#Q-8; Here, if it is likely to be determined whether or not the mode in which the character "ID" is output by the character generator 84 is determined, go to #Q-10; otherwise, go to #Q-11. The flow continues.

#Q-9; In this step, the CPU 40 controls the character generator 84 to stop displaying the ID, and displays "ID".
A two-character pattern of ``ID'' is generated by the character generator 84 as shown in FIG. 21b, and the "ID" character display mode is set. The flow then proceeds to #Q-6. In other words, when in ID setting mode, ID switch 7
Turning on 3 sets the “ID” character display mode.

#Q-10: In this step, the CPU 40 controls the character generator 84 to stop displaying all character patterns as shown in FIG. 21c. The flow then proceeds to #Q-6.

#Q-11; If the flow reaches this step,
Since the CPU 40 is neither in the ID setting mode nor in the "ID" character display mode, that is, in a mode that stops displaying the ID on the monitor, the CPU 40 imports the set ID from the RAM 27 and uses the character generator 84.
The character generator 84 outputs the set ID as a character pattern as shown in FIG. 21a. That is, the ID setting mode is set by this step. Then the flow is #Q-6
Proceed to.

As explained above, the display format of the ID is rewritten every time the ID switch 73 is turned on. In other words, in the playback mode, there is an ID display mode in which ID DATA is superimposed on the video signal and monitored every time the ID switch 73 is turned on;
The ID hidden mode in which playback ID DATA is not output will be repeated. Specifically, the ID display mode c shown in FIG. 21a and the ID non-display mode are repeated. Also, when in recording mode, all IDs to be set are displayed.
Setting mode and “ID” displaying only “ID” characters
The character display mode and the mode in which the ID is not displayed on the monitor are repeatedly switched each time the ID switch 73 is turned on. Specifically, the second
The modes shown in Figure 1 a, b, and c will be repeatedly switched. The ID display in recording mode will be further described below. 2nd in recording mode
When video signals are recorded in the modes shown in Figures 1a and b, in Figure 12 #N-5 and #N-6, the ID is recorded along with the video signal after being frequency-multiplexed with the DPS-modulated video signal. will be done. Furthermore, when recording a video signal in the mode shown in FIG. 20c, no ID data is recorded. However, whether it is inside or outside the frame,
DATA, which indicates field recording, is always deleted along with the video signal.

That is, in this embodiment, the display regarding the ID on the monitor 13 can be switched in either the recording mode or the playback mode depending on the number of times the ID switch is pressed.

Furthermore, in this embodiment, in the recording mode in which the ID is recorded together with the video signal, there is an ID setting mode in which the display shown in FIG. 21a is displayed, and an "ID" character display mode in which the display is shown in FIG. 21b. However, the reason for providing these two display modes will be explained. That is, although the year, month, day, and 11-digit number can be set as an ID, a considerable area on the screen of the monitor 13 is required to display all of the ID information, as shown in Figure 21a. Since there is a problem that the screen may occupy a large area of the screen and obstruct the viewing of the image, a display mode as shown in FIG. 21b is provided to solve this problem.

Next, a method of displaying a reproduced ID in the reproduction mode will be explained. That is, a display method will be described when reproducing an ID recorded together with a video signal when the mode shown in FIGS. 21a and 21b is set by the ID switch 73 in the recording mode. In the playback mode, when the head is moved to a new track, the ID recorded on that track will be played back on the monitor 13. This is because the ID reproduced by the data demodulator 12 shown in FIG. 1 is demodulated, the CPU 40 reads this output, and the character generator 84
This is done by driving the . Here the CPU
The ID read by 40 is stored in RAM 27 by CPU 40.
will be held. The display of such an ID has been described with reference to FIG. 21a, but in this embodiment, the characters stored in the RAM 27 have two display modes shown in () and () below.

() The first display mode that is displayed when an ID recorded with only the year, month, and date set as ID data and no other data set is played back.

() The second display mode when playing back an ID in which the year, month, date and other numerical data are set and recorded using ID DATA.

The display of the ID in parentheses is shown in FIG. 22a.

The display of the ID in parentheses is shown in FIG. 22b.

That is, the display in parentheses displays only the year, month, and day in the lower right corner of the monitor, and the display in parentheses displays the year, month, date, and other data in the lower right corner of the monitor. Therefore, the ID information is always displayed in the lower right corner of the monitor screen to prevent it from interfering with the video signal as much as possible. Further, in this embodiment, the display is displayed in the lower right corner of the screen, but it may be displayed anywhere as long as it is in the corner of the screen.

In order to execute this operation, after reading the output signal of the data demodulator 12 shown in Fig. 1 with the CPU 40, and after confirming that all data other than the year, month, and day are not set, a character is generated. That's fine. That is, the CPU 40 controls the character generator 84 so that the character generation position differs between cases () and () above.

Further, even when it is determined that data other than the date is not the data recorded by this device, the display shown in FIG. 22b is performed.

This ID is a well-known check code.
This can be determined by recording it as DATA.

Next, the case where the year, month, and day are set as the ID will be explained. In the flow, when the year setting switch 74 is turned on, the flow jumps to the subroutine shown in FIG.

#S-1: If the PB mode flag is set here, the flow advances to #S-14 and returns to the flow. If not set, #S-
Proceed to step 2.

#S-2; Here, it is determined whether the mode is ID setting mode, that is, a mode in which ID data is superimposed on the video signal and output to a monitor or printer. If it is not in this mode, proceed to #S-14 and return to the flow. If it is in this mode, proceed to #S-3.

#S-3; Here, change the year setting position on the monitor 13.
10 in the year setting position where the 10th digit number blinks
Blinking a digit in the digits means blinking the character at the position shown in Figure 24a. This means that the CPU 40 controls the character generator 84 to generate the character at this position, or This is done by ensuring that it does not occur. This is done by well-known interrupt processing. The flow then proceeds to #S-4.

#S-4; At this point, wait until the switch 74 is turned off. When switch 74 is turned off, the flow advances to #S-5.

#S-5; Here, it is determined whether the 10 key switches 63 to 72 are turned on. 10 If the key switch is on, the flow is #S-6
Proceed to. If not, proceed to #S-12.

#S-6; Here, the CPU 40 writes the input data from the 10 key switch to the RAM 27, and generates a character pattern at the year setting position shown in FIG. 24a by controlling the character generator 84. . Then the flow is #S
-Proceed to 7.

#S-7; Blink the first digit of the year setting position. This means that the characters at the positions shown in FIG. 24 blink. blink is
This is accomplished by CPU 40 controlling character generator 84. The flow proceeds to #S-8.

#S-8; At this point, wait until the 10 key switch is turned off. 10 When the key switch is turned off, the flow advances to #S-9.

#S-9; Here, it is determined whether the 10 key switch is turned on or not. If turned on, the flow goes to #S-10, otherwise #S-
Proceed to 13.

#S-10; When the 10 key switch is turned on
The CPU 40 writes the data inputted by the 10-key switch into the RAM 27, and controls the character generator 84 to generate a character pattern at the position shown in FIG. 24a, which is the first digit of the year setting device. The flow then proceeds to #S-11.

#S-11; Blink the characters at the year setting position
The CPU 40 controls the character generator 84 to stop it. This allows the user to know that the year setting has been completed. The flow advances to #S-14.

#S-12; If the 10 key switch is not turned on in #S-5, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, the flow branches to #S-5 and steps #S-5 and #S-12 are repeated, and if any switch other than the 10 key is turned on, the flow branches to #S-11. move on.

#S-13; Here, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, the flow branches to #S-9, and if it is turned on, the flow branches to #S-11. Therefore, by repeating steps #S-9 and #S-13, the characters at the year setting position will continue to blink until a switch other than the 10 key is turned on, allowing the user to set the year using the 10 key switch. encourage.

#S-14: If the PB mode flag is set, if the mode is ID setting mode, or if the blinking is stopped by #S-11, the flow returns to step S-14.

As explained above, when the year setting switch 74 is turned on, the number in the 10th digit of the year setting position starts blinking, informing the operator of the position where the data is to be set. Here, by inputting numbers using the 10 key switch, the data input at the blinking position is generated as a character pattern by the character generator 84, and
The CPU holds the data in RAM27. When the setting of the 10th digit is completed, the number in the next 1st digit position will start blinking, and in the same way it will move to this position.
DATA settings are made. Here, when the setting of the first digit is completed, the year setting mode ends and the process returns to the flow shown in , but it is also possible to proceed to the flow shown as it is and enter the month setting mode.

Next, the setting of the month DATA will be described in detail with reference to the subroutine shown in FIG.

In the flow, when the switch 75 is turned on, the subroutine is called and the monthly data is
setting mode.

#T-1: If the PB mode flag is set here, the flow advances to #T-16 and returns to the flow. If the PB mode flag is not set, the flow advances to #T-2.

#T-2; Here, it is determined whether the mode is ID setting mode, that is, a mode in which ID data is superimposed on a video signal and output to a monitor or printer. If you are not in this mode, #T-
Proceed to step 16 and return to the flow. If it is in this mode, proceed to #T-3.

#T-3; Here, blink the 10th digit of the month setting position on the monitor. Month setting position 10
The blinking of the digits in the digits means that the characters in the positions shown in Figure 24a are blinking. This is accomplished by the CPU 40 controlling the character generator 84 to generate or not generate characters. The flow then proceeds to #T-4.

#T-4; At this point, wait until the month setting switch 75 is turned off. When the switch 75 is turned off, the flow advances to #T-5.

#T-5; Here, it is determined whether the 10 key switches 63 to 72 are turned on. 10 If the key switch is on, the flow is #T-
Proceed to 6, otherwise proceed to #T-13.

#T-6; Here, it is determined whether the data input by the 10 key switch is 2 or more.
If the number is 2 or more, the flow proceeds to #T-14; otherwise, the flow proceeds to #T-7. In other words, in the case of month setting, the first number entered is "1"
Alternatively, the flow is branched according to the number set in this step so that the first digit number is accepted only in the case of "0".

#T-7; Here, the CPU 40 stores the input data in the RAM
27 and controls the character generator 84 to generate a character pattern at the position shown in FIG. Flow proceeds to #T-8.

#T-8; Here, press the first digit of the month setting position. This means that the character at the position shown in Figure 24a blinks.
The flow proceeds to #T-9.

#T-9; At this point, wait until the 10 key switch is turned off. 10 When the key switch is turned off, the flow advances to #T-10.

#T-10; Here, it is determined whether the 10 key switch is turned on. If it is on, the flow goes to #T-11, otherwise it goes to #T-
Proceed to 15.

#T-11; Here, the CPU 40 writes the data input by the 10 key switch in #T-5 or #T-10 to the RAM 27, and generates a character at the position shown in FIG. 24, which is the first digit of the month setting position. The character pattern is generated by controlling the device 84, and the flow then proceeds to #T-12. Furthermore, #T-
If branching from 14 to this step, #T-
14, by executing #T-11, #T-5
The data entered by the 10 key switch is displayed in the first digit, and the 10th digit is “0”.
is displayed.

#T-12; Stops blinking of the data at the month setting position and displays that the month setting is completed. Flow proceeds to #T-16.

#T-13; This step includes 10 in #T-5.
Branches if the key switch is not turned on.
Here, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, it branches to #T-5, and if it is turned on, it branches to #T-12. i.e. #T until the 10 key switch or other switch is turned on.
-5, repeat the flow of #T-13, and if the 10 key switch is turned on, the flow will be #T-6
If a key switch other than 10 is turned on, the flow branches to #T-12.

#T-14: The process branches to this step when it is determined in #T-6 that the input data is "2" or more. Here, CPU40 is RAM2
Write data “0” to 7 and press 10 of the month setting device.
The character generator 84 is controlled to generate a character pattern "0" in the digit. Flow proceeds to #T-11.

#T-15; Here, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, it branches to #T-10, and if it is turned on, it branches to #T-12.

Return to the flow of #T-16;

As explained above, when the switch 75 is turned on, the 10th digit at the month setting position first blinks, thereby first indicating the position where data to be input using the 10th key switch should be set. If 2 or more data is entered here, “0” is automatically set to the 10th digit and 1
The input data will be set in the first digit. Of course, if a value less than 1 is entered, it will be entered in the 10th digit and the next blink position will be moved to the 1st digit, and the next data entered using the 10 key will be set to the 1st digit. Nor. Therefore, according to this embodiment, when setting the month, it is possible to easily set the month by taking advantage of the fact that 2 or more is never set in the 10th digit.

Further, in #T-3, only the 10th digit is blinked here, but the 10th digit and the 1st digit may be blinked together.

Furthermore, when the setting of the next first digit is completed, the process returns to the flow in this example.
It is also possible to proceed to the subroutine shown in FIG. 6 and enter the day setting mode.

Next, the day data setting will be described in detail with reference to FIG. Switch 7 in the flow of
When 6 is turned on, the day data setting mode is called and the flow jumps to .

#U-1: If the PB mode flag is set here, the flow advances to #U-16 and returns to the flow. If the PB mode flag is not set, proceed to #U-2.

#U-2; Here, it is determined whether the mode is the ID data SET mode, that is, the mode in which the ID data is superimposed on the video signal and output to the monitor or printer. If you are not in this mode, proceed to #U-16 and return to the flow. If this mode is selected, proceed to #U-3.

#U-3; Here, the number in the 10th digit of the date setting position on the monitor blinks. The blinking of the 10th digit number in the month setting position means that the characters in the position shown in Figure 24a blink. means.
This is accomplished by the CPU 40 controlling the character generator 84 to generate or not generate characters. The flow then proceeds to #U-4.

#U-4: At this point, wait until the date setting switch 76 is turned off. When the switch 76 is turned off, the flow advances to #U-5.

#U-5; Here, it is determined whether the 10 key switches 63 to 72 are turned on. 10 If the key switch is on, the flow is #U-6
If not, proceed to #U-13.

#U-6; Here, it is determined by the 10 key switch whether the input data is 4 or more. If it is 4 or more, the flow proceeds to #U-14, otherwise the flow proceeds to #U-7. In other words, in the case of month setting, the first number entered is "3", "2",
In order to accept the first-digit number only in the case of "1" or "0", the flow is branched according to the number set in this step.

#U-7; Here, the CPU 40 stores the input data in the RAM
27 and controls the character generator 84 to generate a character pattern at the position shown in FIG. 21a, that is, at the blinking position #U-3. The flow proceeds to #U-8.

#U-8; Here, blink the first digit of the date setting position. This means that the character at the position shown in Figure 24a blinks. The flow proceeds to #U-9.

#U-9; At this point, wait until the 10 key switch is turned off. 10 When the key switch is turned off, the flow advances to #U-10.

#U-10; Here, it is determined whether the 10 key switch is turned on. If turned on, the flow goes to #U-11, otherwise #U-
Proceed to 15.

#U-11; Here, the CPU 40 writes the data input by the 10 key switch in #U-5 or #-10 to the RAM 27, and writes the character generator 84 to the position shown in FIG. 24, which is the first digit of the date setting position. is controlled to generate a character pattern, and the flow then advances to #U-12. Furthermore, #U
If branching from −14 to this step, #U
-14, by executing #U-11, #U-
In step 5, the data entered using the 10 key switch is displayed in the first digit and “0” is displayed in the 10th digit.
is displayed.

#U-12; Stop blinking the data at the date setting position and display that the date setting is completed. Flow proceeds to #U-16.

#U-13; 10 in #U-5 for this step
Branches if the key switch is not turned on. Here, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, it branches to #U-5, and if it is turned on, it branches to #U-12. In other words, repeat the flow of #U-5 and #U-13 until the 10 key switch or other switch is turned on.
When a key switch is turned on, the flow branches to #T-6, and when a key switch other than 10 is turned on, the flow branches to #U-12.

#U-14: The process branches to this step when it is determined in #U-6 that the input data is "4" or more. Here, the CPU 40 is RAM
Write data “0” to 27 and set the month setting position.
The character generator 84 is controlled to generate a character pattern "0" in the 10th digit. Flow is #U-11
Proceed to.

#U-15; Here, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, it branches to #U-10, and if it is turned on, it branches to #U-12.

Return to the flow of #U-16;

As explained above, when the switch 76 is turned on, the 10th digit at the day setting position first blinks, thereby first indicating the position where data to be input using the 10 key switch should be set. If 4 or more data are input here, "0" is automatically set in the 10th digit and the input data is automatically set in the 1st digit.
Of course, if there is an input of 3 or less, it will be entered in the 10th digit and the next blink position will move to the 1st digit, and the next data entered with the 10 key will be set to the 1st digit. Nor. Therefore, according to this embodiment, when setting the day, 4 is placed in the 10th digit.
Taking advantage of the fact that the above settings are never made, it is possible to perform a simple date setting.

Further, in #U-3, only the 10th digit is blinked here, but the 10th digit and the 1st digit may be blinked together.

In the embodiment described above, the display is blinked to indicate the setting position, but the setting position may be indicated by other methods such as changing the brightness or changing the color.

Next, the erase sequence will be explained. When erasing, the erase execution switch 78 and erase standby switch 77 shown in FIG. 1 are used. In other words, when erasing is to be performed, the switch 77 is
The data is placed in a standby state for erasure, and then erasure is executed only when the erase execution switch of switch 78 is turned on. Furthermore, there are two modes for erasing: a mode in which a plurality of tracks are continuously erased, and a mode in which only a single track is erased. The above operation will be described in detail below based on the flowchart shown in FIG. In the flowchart A in FIG. 1, when the switch 77 is turned on, the flow calls a subroutine and proceeds to #V-1. At this point, the erase standby state is set, and at this time, "FF" is set in the buffer memory E for storing the number of erased tracks. In addition, the 2-digit 7-segment LED 25 displays the truck number.
The track number being accessed by the head 3-1 performs a blinking operation that repeatedly turns on and off at a cycle of about 2 Hz. In other words, by blinking the track number display LED (2Hz cycle),
The operator can confirm that the erase standby mode has been set.

That is, compared to a method that uses a dedicated display element to indicate that the erase standby state is in effect, the method of this embodiment not only does not require the use of such a dedicated display element, but also displays the track number. By changing the display form of the display, the standby state for erasing is displayed, making it easier to recognize the track number that is about to be erased. In addition, in this example, 7 segments
Although the standby state for erasing is indicated by blinking the display on the LED 25, it is of course possible to use other liquid crystals as the display element, and in addition to blinking, the color and brightness of the display may be changed. Various methods are possible, such as changing the form of displayed characters.

In addition, if a display that displays other information than the track number, such as a display that displays the number of free tracks, is provided, the display format of the display can be changed as described above to enable erasure standby. The status may be displayed.

The flow then proceeds to #V-2.

#V-2; Here, it is determined whether or not the PB mode flag is set, and if it is set, the flow advances to #V-4; otherwise, it is determined that the switch 77 has been turned off. After recognition, the flow advances to #V-3.

#V-3; Here, the subroutine for setting the playback mode described above is called, the playback mode is set, and the flow advances to #V-4. Therefore, when the erase standby switch 77 is turned on, #V -2 and #V-3, the playback mode is always set and the erase standby state is set.

#V-4; Here, it is determined whether the switch 78, that is, the erase execution switch is turned on. If it is turned on, the flow advances to #V-4-1; otherwise, the flow advances to #V-15.

#V-4-1; Here, the branch destination of this step is determined by a switch that is prepared in advance in the case (not shown) of the magnetic sheet 1 and that determines the presence or absence of a claw. In other words, this claw has the function of preventing accidental erasure, and if it is broken off, it is promised in advance not to erase the data. Therefore, if accidental erasure prevention is set, the flow advances to #V-18. If not set, the flow advances to #V-5.

#V-5: In this step, it is determined whether the value set in the buffer memory E (hereinafter referred to as E) for storing the number of erased tracks is "0". In addition, buffer memory E is #V-1
Although it is preset to "FF" in , it is also possible to change the setting value in #V-15, which will be described later. Here, if the value set in buffer memory E is "0", the flow is #V-18, otherwise, it is #V-5-1.
The flow advances. Next, #V-5-1 will be explained.

#V-5-1: In this step, it is determined whether the value set in the buffer memory E is "FF" or not. If it is “FF”, the flow goes to #V-6; if it is not “FF”, the flow goes to #V-6.
Proceed to -5-2.

#V-5-2; The field flag is set and the field playback mode is set. The flow proceeds to #U-6.

#V-6; Here, the blinking of the 7-segment LED 25 for displaying the track number is switched from the 2Hz set in #V-1 to a faster cycle of 5Hz. In addition, when performing continuous track deletion, the set track number is displayed on the 7-segment LED 25 instead of the track number being accessed by the head 3-1 in #V-17, which will be described later. 7 segments by executing #V-6 even if
The LED 25 is automatically switched to display the track number. Therefore, when erasing consecutive tracks, the user can confirm which track is currently being erased.

#V-7; Here, the CPU 40 is the erase signal generator 8
5 to generate an erase signal and perform erasing. When erasing is to be performed, switches 2 and 3 shown in FIG. 1 are controlled to connect at least one of the heads 3-1 and 3-2 to the recording amplifier. Here, when the field flag is set, that is, in the field reproduction mode, the erase current flows only to the head 3-1 shown in FIG. 1 which is being reproduced, and one torque is erased. When the field flag is cleared, that is, when frame playback is selected, the head 3-1, shown in FIG.
Erasing current flows simultaneously to both of the signals 3-2, and one frame's worth of tracks, in other words, two adjacent tracks' worth of video signals are erased. In this embodiment, erasing in frame mode is executed only when the flow advances from #V-5-1 to #V-6 without passing through #V-5-2. There is. That is, when the value of buffer memory E is set to "FF" in #V-5-1, that is, when the continuous erase mode described later is not selected.

#V-8; Wait here until erasing is completed.
When erasing is completed, the flow advances to #V-8-1.

#V-8-1; Here, it is determined whether E is equal to "FF". If it is equal to "FF", it is the single erase mode, so the flow proceeds to #V-18; otherwise, since continuous track erase is set, the flow proceeds to #V-9.

#V-9; Here, the value of buffer memory E is subtracted by 1. Flow proceeds to #V-10.

#V-10: In this step, it is determined whether the value of buffer memory E is greater than 0 or not. That is, the number of tracks to be erased when continuous track erasure is set is detected, and if it is greater than 0, the flow proceeds to #V-11; otherwise, it is assumed that continuous track erasure has ended. Proceed to #V-18.

#V-11: In this step, it is determined whether the stop switch 61 is turned on. If it is turned on, the flow branches to #V-18, and if it is not turned on, the flow proceeds to #V-12. In other words, the continuous erase mode described later is selected,
While executing this, the stop switch 61
Continuous erasing can be interrupted by performing this operation. Flow then proceeds to #V-12.

#V-12: In this step, it is determined whether N in the track number buffer memory is 50 or more, that is, whether the track being accessed by the head 3-1 is the final track. If so, the flow proceeds to #V-18 and the erase operation is terminated.If not, the flow proceeds to #V-13.

#V-13: By executing this step, the track positions accessed by the heads 3-1 and 3-2 are moved inward by one track. Further, as the heads 3-1 and 3-2 move, N+1 is set to N in the track number memory. The flow then branches to #V-5-2.

Therefore, when erasing continuous tracks, #V-5-2 remains active until the stop switch 61 is turned on or until the innermost track is erased.
The flow from #V-13 is repeated until the value of the buffer memory E becomes 0, that is, until the set number of tracks is erased.

Next, the flow after #V-15 for setting the continuous erase mode executed as described above will be explained.

#V-15: Determine whether any of the 10 key switches 63 to 72 in FIG. The flow advances to 15-1.

#V-16: In this step, the continuous track erase mode will be set. That is 10
The number input by the key switches 63 to 72 becomes the number of tracks on which continuous erasure is to be performed. The numerical value of the turned-on 10 key is set in the erase track number buffer E in the 1's digit. Flow then proceeds to #V-17.

#V-17; 7 segments in this step
The value of E is displayed on the LED 25. This situation will be explained with reference to FIG. 28. At #V-15, the value of the first 10 key switch turned on is E.
is set in the 1s digit (#V-16), and
In this step, as shown in FIG. 25a, it will be displayed in the 1's position of the LED 25. Here, before reaching the display shown in FIG. 22a, the track number is displayed on the display and is blinking. Further, F set to E is displayed as "0". In addition, the numerical value displayed on the display is the same as that shown in Figure 25a because the 2Hz blinking operation is being performed repeatedly in #V-1.
The “〓” display shown in will flash. The flow then proceeds to #V-17-1.

#V-17-1; At this point, wait until the 10 key switch is turned off. When turned off, the flow is #V
Proceed to -15-1.

#V-15-1; Erase standby switch 7 here
7 is turned on. If it is turned on, the flow advances to #V-18, and if it is not turned on, the flow advances to #V-15-2.

That is, by turning on the erase standby switch 77, the erase standby state set in #V-1 is automatically canceled by turning on the switch 77 again and in the steps after #V-18. Therefore, there is no need to provide a dedicated release switch.

#V-15-2; Here, it is determined whether any switches other than the switch 78 and the 10 key are turned on. If turned on, the flow is #V
Branches to −18, #V if not turned on
Branch to -4.

In other words, the erase standby state is automatically canceled by turning on any switch other than the 10 key as well by the steps after #V-18. Therefore, there is no need to provide a dedicated release switch. Therefore, there is no need to take the trouble to provide a separate switch. #V-15-1, #V-15- mentioned above
If you pass step 2 with NO, #V-
The above-mentioned steps after #4 will be repeated, but the operation when executing steps after #V-4 when the 7-segment LED 25 is already displaying "ⓓ" shown in FIG. 25 will be explained.

When the 10 key switch is turned on in #V-15, the number entered by the switch in #V-16 is set to the first place in buffer memory E, and the number that was previously set in first place is set to the first place in buffer memory E. Moves to 10th place, and the number set at 10th place disappears.

Here, for example, “5” out of 10 key switches
If the key is turned on, #V-16, #V-
7 segment LED2 by running 17
5, the display shown in FIG. 28b is displayed. Of course, the value set in buffer memory E in this case is 15. Next, when a good "2" is inputted to the 10-key switch in the same manner, the display shown in FIG. 25c is produced. The above display example shows 1, 5, and 1 of 10 key switches in the erase standby state.
2 shows the display performed by the LED 25 when the LEDs 2 are turned on in sequence. Furthermore, the displayed numerical value matches the value set in E as it is. In other words, “2” is set by the 10 key switch.
When the above numerical value is set, this is equivalent to selection of the continuous erasing mode, and the set numerical value becomes the number of tracks on which continuous erasing is performed.
This situation can be seen in #V-
If the value of buffer memory E is greater than 0 at 10, the flow proceeds to #V-11, otherwise branches to #V-18, and if the track number N is less than 50, the flow proceeds to #V-11. UP the track at 13 and branch to #V-5-2,
Continuous erasing is performed by executing steps after #V-6. In other words, #V
If the stop switch 61 is not turned on at -11, erasing will continue until the value of E becomes equal to 0 or until track No. 50, which is the innermost track, is erased. Next, steps #V-18 to #V-20, which are executed after executing the steps described above, will be explained.

#V-18; At this point, the blinking of the 7-segment LED 25 is stopped and track NO N is displayed on the display. The flow then reaches #V-19.
In other words, this step erase standby state is released.

#V-19; If the switch 77 is turned on, waits, and if it is turned off, #V-20
Proceed to.

#V-20; At this point, the flow returns to the flow shown in A of FIG.

As explained above, when performing erasing, in this embodiment there are two modes: a mode in which erasing is performed only once, a mode in which it is performed continuously, and a mode in which erasing is performed after specifying the number of tracks to be continuously erased in advance. However, regarding erasure when the number of erase tracks is not set using the 10 key switch, since the value of E in #V-5-1 is set to "FF" in advance, #V- Move to #V-6 without passing through 5-2. Therefore, if the field flag is cleared in the erase standby state, erase in frame mode, that is, 2
Erasing for one track is performed, and if the field flag is set, erasing for one track is performed in field mode. In other words, when playing back in frame mode, two tracks used for playback are erased, and when playing back in field mode, one track is erased. However, if the number of erased tracks is set using the 10-key switch, the process goes through #V-5-2, so erasure is always performed in field mode. However, if "0" is set by the 10 key switch, the process branches to #V-18 at #V-5, so erasure is not executed. Also, “1”
is set, the field flag is set in #V-5-2, so even if frames were being played back, only the outer track of the two tracks that make up the frame image would be 1. The number of tracks will be deleted.

Therefore, it is possible to erase only the signal recorded on one of the two tracks constituting a frame image.

Furthermore, when performing continuous track erasure, it is generally a prerequisite in many cases to record new information, such as a video signal, on the erased track. In the embodiment described above, when continuous track erasing is completed, the head 3-1 is located on the last erased track, so when recording new information, the user must press the track UP switch 54 and the track DOWN. It is necessary to operate the switch 55 so that the head 3-1 accesses the track on which erasing has started.

Therefore, the next step is to execute continuous track erasing, and when this is completed, to automatically access the head 3-1 to the track where continuous erasing has started. is shown in FIG. The flow shown in FIG. 29 is a flow inserted between steps #V-18 and #V-19 shown in FIG. 27.

First, when executing subroutine V, #V
-1, the track number N being accessed at that time is stored in the memory N'. Then, erasing is executed according to the flow described above #V
-18, the flow shown in FIG. 29 is executed. That is, in #V-18-1, it is determined whether the number of the track that the head 3-1 is accessing at that time matches the number of the track stored in the memory N' in #V-1;
If they do not match, #V-18-2, #V-18
-3 is executed, the head 3-1 is controlled to access the outer track by one track, and N is set to N-1, and the 7-segment LED 25
Memory N is displayed. The flow then returns to #V-18-1 and continues #V- until the number of the track being accessed by head 3-1 matches the number of the track stored in memory N'.
18-2, repeat #V-18-3, head 3-1
When accesses the track on which erasing has started, the flow branches from #V18-1 to #V-19, and the steps from #V-19 onwards are executed. Therefore, by executing the flow shown in FIG. 29, when the erasing is completed, the head 3-1 automatically accesses the track where erasing started, so it is not necessary to manually search for the position where erasing started for the next recording. can be omitted.

Furthermore, when performing continuous erasing, it is not possible to play back the video to be erased for a certain period of time, have the operator confirm this, and determine whether or not the stop switch 61 is turned on before starting the erasing operation for that track. This is extremely effective in preventing accidental erasure.

To realize this function, one track is required in #V-13 of subroutine V shown in Fig. 27.
After executing N+1 for UP and N, and before executing #V-7, it is desirable to provide a step for a delay of about 1 second, for example, in the step immediately after #V-6, and furthermore, during this delay, a stop switch is switched. 6
It is sufficient to provide a step for determining whether or not 1 is turned on and branching to #V-7 if it is not turned on, and branching to #V-18 if it is turned on.

By providing such a step, it is possible to check the video signal to be erased, so that if a video that is not desired to be erased is reproduced, continuous erasing can be interrupted by turning on the stop switch 61. Therefore, the probability of erroneous erasure is dramatically reduced.

In addition, when performing continuous erasing, in the above-described embodiment, the flow branches from #V5-1 to #V5-2 in the subroutine, and by executing #V5-2, all 1 in field mode.
Tracks are erased one by one, but in order to shorten the execution time of continuous erasing, two tracks are erased in frame mode.
When erasing consecutive tracks, it is effective to erase two tracks at least once by sending an erase signal to two heads at the same time. An example in this case will be described below.

First, in FIG. 30, the flow shown in FIG. 30a is a step inserted between steps #V-6 and #V-7 shown in FIG.
The flow shown in is a step inserted between steps #V-11 and #V-12. Next, the flow will be explained.

After the subroutine shown in FIG. 27 is executed up to #V-6, #V-6-1 is executed following #V-6. In this step, it is determined whether the erase track buffer E is 2 or more, that is, whether continuous track erase is being performed. If the number is 2 or more, the flow proceeds to #V-6-2; otherwise, the flow proceeds to #V-7. # In V-6-2, set E to E-1 and clear the field flag. The flow reaches #V-7. Here, an erase signal is generated at #V-7 shown in FIG. 27, but in this case, if the field flag is set, one
If the erase signal is supplied to the other head, that is, the head that is performing field reproduction, and the field flag is cleared, the head 3-
The erase signal is supplied to both 1 and 3-2 at the same time. After erasing is completed, #V-8 to #V-
11 as described above, and if the continuous erase operation is not completed, the flow changes from #V-11 to #V-11-
1, and it is determined whether or not the field flag is set. If continuous track erasure is not set and the field flag is set, the flow advances to #V-12 and follows the flow described above. Further, if continuous track erasure is set in #V-11-1 and the field flag is not set, #V-11-1 is set as described above.
Since two tracks have been erased in step 7, the flow reaches #V-11-2, N is set to N+1, and head 3-1 is erased on the inner circumference side of one track.
1, 3-2 moves. After that the flow is #V-13
Then, the head moves one track further inward according to the flow described above.

If you do the above, when performing continuous deletion,
Erasing is performed in frame mode until the number of remaining tracks in continuous erasing becomes 1, so that the execution speed of continuous erasing can be increased. However, in this case, if you want to check the video to be erased before executing the erase, follow #V-6, and if the field flag is set, press the head 3-1, 3-2 in Figure 1 for a certain period of time. It is necessary to select each of them to perform field reproduction by head 3-1 and field reproduction by head 3-2. In addition, by omitting steps #V-2 and #V-3 and switching between PB mode and REC mode, you can select a mode in which the played video that will be erased when performing continuous erasure is checked and a mode in which it is not confirmed. You may also do this. In other words, if you select a mode in which you do not check the video to be erased when performing continuous erasing, and add the flows shown in Figures 30a and b to the flow shown in Figure 27, the time for continuous erasing will be the shortest. This is a very effective means when erasing all tracks.

Next, a subroutine executed when the all track erase standby switch 79 is turned on will be described with reference to FIG.

#W-1: “〓” indicating all track erase standby state on 7 segment LED25
(ALL-ERASE) blinks at 2Hz.

#W-2: Determine whether or not the PB mode flag is set, and if it is not set, #W
-3, the flow branches to #W-4.

#W-3-1: Clear the PB mode flag to prohibit reproduction of magnetic sheet 1.

#W-3-2: Detects that the switch 79 is turned off and proceeds to #W-4.

#W-4: Determine whether the erase switch 78 is on or not. If it is on, the flow branches to #W-9; if not, the flow branches to #W-5.

#W-5: All track erase standby switch 7
9 is turned on or not. If it is on, the flow branches to #W-7, and if it is not on, the flow branches to #W-.

#W-6: Determine whether any switch other than switch 79 has been turned on. If it is on, #W-7
If it is not on, the flow branches to #W-4.

#W-7: Stop blinking of the LED 25 and display N, that is, the track number being accessed by the head 3-1 on the LED 25.

#W-8: Wait until the switch 79 is turned off, and if it is turned off, return to step.

#W-9: When the erase switch 78 is turned on in #W-4, the flow branches to this step. In this step, it is determined whether there is an accidental erasure prevention claw (not shown), and if so, go to #W-10.
If not, the flow branches to #W-7.

#W-10: Determines whether N is "1", that is, the track number accessed by head 3-1 is "1", and if it is "1", it is sent to #W-12 with "1". If not, the flow branches to lW−11.

#W-11: The heads 3-1 and 3-2 are moved to the outer circumferential side by one track, and 1 is further subtracted from N, and the flow returns to #W-10. Therefore #W-
10. By repeatedly executing #W-11, when the number of tracks being accessed by head 3-1 becomes number 1, the flow starts at #W-12.
Branch to.

#W-12: Display N blinking (5Hz) on LED25. This allows the user to know which tracks have been erased when all tracks are erased.

#W-13: Field flag is cleared and frame mode is set. Therefore, head 3-
Track erasure is performed using both 1 and 3-2.

#W-14: These two steps are #V-7, #V-
8 #W-15: Same as.

#W-16: Both heads 3-1 and 3-2 are used to erase two tracks without moving the heads, so in this step, the heads are moved to the outer circumferential side by two tracks and further N is erased. Add 2 to .

#W-17: Determine whether N is 50 or not, if it is 50, go to #W-7, if not 50, go to #W-12
The flow branches to step #W-12 to #W-17 until all tracks are erased.

As explained above, in the all track erase mode, which is executed by turning on the all track erase standby switch and then turning on the erase switch, clear the PB mode flag and check the video to be erased before erasing. Also, use both magnetic heads 3-1 and 3-2 to
Since erasing is performed track by track, the time required to erase all tracks is extremely short compared to the method of erasing one track at a time. Furthermore, when erasing all tracks, the head is moved to the end of the track (in this example, the outermost periphery) and then all the tracks are sequentially erased toward the opposite end. When attempting to erase all tracks, no matter which position the head 3-1 is accessing, all tracks can be surely erased.

Furthermore, during erasing, the number of the track being accessed by the head 3-1 is displayed on the LED 25, so that the user can recognize to what extent the erasing operation is being performed.

In the above embodiment, the magnetic sheet 1 is used as the recording medium, but it may also be an optical recording medium. A magneto-optical recording medium or other recording medium may also be used. As a recording means, a means according to the recording medium,
For example, in the case of an optical disk, an optical head may be used.

In the above-described embodiment, the determining means for determining the type of information recorded on the recording medium is carried out in steps #10 to #12 shown in FIG. 5, that is, whether the video signal to be recorded is a field video signal or a frame video signal. The head 3-1, 3-3 shown in FIG.
-2 and an erasing signal generator 85, and a control means for controlling the erasing range of the recording medium by the erasing means based on the determination result of the determining means, when the continuous erasing mode is not selected and the information on a single screen is In the erase mode, the type of video signal of the track being accessed by the heads 3-1 and 3-2 is determined by the head 3-1 based on the field flag whose setting and clearing are controlled by the data read from the memory. A subroutine that controls whether to erase two tracks by applying an erase current to both heads 1 and 3-2, or erase only one track by applying an erase current to only head 3-1, especially #V-5. -1,
#V-6 and #V-8.

As mentioned above, in this embodiment, the continuous erasing mode is not selected, and the heads 3-1 and 3-2 are used only in the mode of erasing information on a single screen.
Controls whether to erase two tracks or only one track based on the result of determining whether the video signal of the track that is being accessed and is to be erased is a frame video signal or a field video signal. This makes it easier to use and reduces the time required for erasing compared to erasing one track at a time, but it is of course possible to perform this operation in continuous erasing mode. It is.

In addition, in this embodiment, the information recorded on the recording medium is a field video signal and a frame video signal, but the information is not limited to such information, and even if the recording medium is used to record other information, the type of information may vary. Of course, the present invention can be implemented as long as the erasing range is controlled accordingly.

〔Effect of the invention〕

As explained above, according to the present invention, whether the image information recorded on the recording medium is the image information recorded in the first recording mode or the image information recorded on the recording medium is A mode for automatically setting a range to be erased depending on whether the image information is recorded in a recording mode, and a mode for controlling the erasing range so as to erase image information in a range according to the operation of an operating member. mode, it is possible to freely switch between the two modes depending on the purpose.Especially when erasing, the first mode is initially set with priority over the second mode, so the user does not have to worry about anything special. It is possible to use a mode in which the erasing range is set according to the type of image information recorded on the recording medium without any manual operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a combination of switching states of SW2 to SW5 shown in FIG. 1, and FIG. 3 is a front view of the device of this embodiment. Figure 4 is a front view of the remote control device used with the device;
Figures to Figures 20, 23, 25 to 27
Figures 29 to 31 show the CPU shown in Figure 1.
40, FIG. 21, FIG. 22, and FIG. 24 are diagrams for explaining the I/D signals displayed on the monitor. FIG. 28 is a diagram for explaining the flow of FIG. 27, and FIG. FIG. 32 is a diagram for explaining signals generated from the erase signal generator 85 shown in FIG. 1. 1...Magnetic sheet, 3-1, 3-2...Head, 40...CPU.

Claims (1)

[Scope of Claims] 1. Reproducing means for reproducing information recorded on a recording medium, whether the image information recorded on the recording medium is image information recorded in a first recording mode or not in the first recording mode. Discrimination means for determining from the playback output of the playback means whether the image information is recorded in a high-quality second recording mode with a larger amount of information; and erasing means for erasing the image information recorded on the recording medium. , an operating member, a first erasing mode for automatically controlling an erasing range of the recording body by the erasing means according to a discrimination result of the discrimination means with respect to a given erasure instruction; and a second erasing mode for controlling the erasing range of the recording medium by the erasing means so as to erase image information in the range specified by manual operation of the operating member in response to a given erasing instruction. An erasing device comprising: second control means for initializing the first erasing mode with priority over the second erasing mode during erasing.