JPH0471208B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for restarting a data processing device, and in particular, the present invention relates to a method for restarting a data processing device. This invention relates to a method for restarting a processing device.

[Conventional technology]

Conventionally, in a data processing apparatus, the following method is used to recover from a failure immediately after power is turned on.

The first method is to reissue a power-on reset if a failure occurs during the initial program load (IPL) immediately after power-on because the flip-flop could not be initialized during the power-on reset. By re-initializing the flip-flop etc.
The aim is to recover from failures.

The second method, for example, as disclosed in Japanese Patent Application Laid-Open No. 50-45534, assumes that the failure is caused by malfunction due to variations in the electrical characteristics (particularly voltage margin) of each element constituting the circuit. When restarting, the power supply voltage is changed and reset to within a margin that allows normal operation of each element constituting the circuit, thereby attempting to recover from the failure.

[Problem that the invention seeks to solve]

In the above conventional technology, transient phenomena at the time of power-on (change in power supply voltage to steady voltage, change in each element from inactive state to active state, change in temperature due to heat generated by each element itself, etc.) Accidental failures, such as failures caused by uninitialized clocks or flip-flops in the control system due to power-on reset, or temporary circuit contact due to condensation that occurs in cold conditions during power-down. No consideration is given to the disabilities that may be the cause.

On the other hand, the integration of electronic components used in data processing devices is becoming larger year by year. As the density of such circuits increases, data processing equipment becomes smaller, has higher performance (higher speed), and becomes more power efficient (current saving).
Although these advantages arise, the reliability of individual elements within the integrated circuit generally decreases. For example, there is a reduction in the noise margin and a reduction in the margin for soft errors due to the miniaturization of dynamic RAM cells. Therefore, countermeasures against accidental failures due to transient phenomena at the time of power-on are becoming increasingly important.

SUMMARY OF THE INVENTION An object of the present invention is to provide a restart method that improves the recovery rate from the above-mentioned accidental failures immediately after the data processing apparatus is powered on.

[Means for solving problems]

The present invention provides, in a data processing device equipped with a service processor or the like that executes IPL, etc., a power control section that turns on and off the system power of the data processing device. If there is no report from the service processor, etc. that the system is operational within a certain amount of time, the system will not function properly. After turning off the power,
There are provided means for re-applying the system power, means for counting the number of times the system power is turned off and re-applied, and means for inhibiting the re-applying of the system power when the number of times the system power is disconnected and re-applied reaches a predetermined value.

[Effect]

When the power switch or the like of the data processing device is turned on, the power control section turns on the system power.
As a result, the service processor etc. start operations such as IPL. At this time, if the service processor etc. cannot operate due to the occurrence of a failure (or if the service processor detects a failure), the service processor etc. will not report to the power supply control unit that it is operable. At this time, the power control unit turns off and turns on the system power. Failures that occur immediately after the power is turned on are often due to transient phenomena occurring when the power is turned on, and are often unrecoverable by retrying while the power is turned on. However, most of these types of failures can be recovered by turning the power back on. Due to the above action of the power control unit, intermittent failure when the power is turned on is almost 100%.
Recover.

Note that if recovery from a failure is impossible, the power may be turned off and turned on again indefinitely. For this reason, we count the number of times the power is turned off and turned on again.
When it reaches a predetermined value, turning on the power again is inhibited. This prevents the power from being turned on again.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of a data processing apparatus according to the present invention. Note that in this embodiment, only the parts related to the present invention are shown.

In FIG. 1, a data processing device 1 includes a central processing unit 2, a service processor 3, a first power supply 7, a second power supply 8, and a first power supply control section 6. The service processor 3 is composed of a microprocessor 4 and a control memory 5.
The first power supply device 7 is for supplying power to the power supply range 9, and is controlled to be turned on and off by the power supply device control section 6 via a control line 13. The second power supply device 8 is for supplying power to the power supply range 10, and is constantly supplying power. This power supply device 8 is composed of, for example, a battery or a capacitor power supply. The microprocessor 4 and the power supply control unit 6 report that the service processor 3 is operational.
It is connected by SVP READY report line 11.

Furthermore, the power supply control section 6 is connected to a power supply switch 12 .

FIG. 2 shows an example of the configuration of the power supply controller 6. As shown in FIG. Here, the power supply control unit 6 includes a fixed time detection counter 21, a power-off/re-on status creation circuit 2,
3. Power on/off control circuit 24, register 2
5, and an AND gate (fixed time detection suppressing means) 22 that suppresses the fixed time detection report from the fixed time detection counter 21 based on the operable report from the service processor 3.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2. When the power switch 12 is turned on, the power supply control section 6 turns on the first power supply 7.
to the control line 1 by the power on/off control circuit 24.
3, a power-on instruction is given, and the detection counter 21 is started for a certain period of time. When power is supplied to the power supply range 9 by the power supply device 7,
In the service processor 3, the microprocessor 4 starts operating according to the microprogram in the control memory 5, performs an initial microprogram load (IPL), etc. on the central processing unit 2, and
Furthermore, for the power supply control unit 6, the SVP
A READY report line 11 reports that the service processor 3 is operational. At this time, a failure may occur in the service processor 3, or
When the service processor 3 detects a failure such as an IPL abnormality, the service processor 3 cannot report to the power supply control section 6 that the service processor 3 is operable or no longer reports it. In the power supply device control unit 6, the power supply device 7
If a report indicating that operation is possible is not received via the SVP READY report line 11 within a certain period of time after the power is turned on, the power-off/re-on status will be displayed via the AND gate 22 due to the certain time detection counter 21 counting over. The creation circuit 23 is activated, and the power on/off control circuit 24 turns the power supply device 7 off and on again to recover from the failure. In this case, the power on/off control circuit 24 turns on the power again after a certain period of time has elapsed after turning off the power, for example, according to the status of the power off/on again status creation circuit 23 .

Here, if recovery from the failure is impossible, the power may be turned off and turned on again indefinitely. The register 25 prevents this. That is, a certain value is set in advance in the register 25, the contents of the register 25 are incremented by 1 by the output of the AND gate 22, and when the value reaches zero, the power-off/re-on status creation circuit 23 This prevents the power from being turned off and turned on again more than a certain number of times.

FIG. 3 shows still another embodiment of the power supply controller 6. In FIG. That is, this power supply control section 6 is composed of a microprocessor 31 and a control memory 32, and the operation shown in FIG. 2 is realized by microprogram control.

FIG. 4 shows an operation flowchart of FIG. 3.
When the power switch 12 is turned on, the microprocessor 31 initializes the power-off/re-start count value A and the SVP READY wait count value B to zero according to the microprogram in the control memory 32, and then switches the control line 13, an instruction is given to the first power supply device 7 to turn on the power. And S.V.P.
The state of the READY report line 11 is checked to determine whether the service processor 3 is operable, and if it is operable, the startup process is terminated normally. If the service processor 3 is inoperable, the SVP READY wait count value B is incremented by 1, and before the count value reaches the maximum SVP READY wait count number m, the service processor 3
When it becomes operational, the activation process is also terminated normally.

On the other hand, even if the SVP READY wait count value B reaches the maximum count number m, the service processor 3
is inoperable, the count value A of the number of times the power is turned off and turned on again is increased by 1, and the SVP
After clearing the READY value B to zero, the power supply device 7 is turned off and then on again to recover from the failure. While the service processor 3 does not recover its operation, the power is repeatedly turned off and then turned on again, and if the service processor 3 is still inoperable even if the execution count value A reaches the maximum number of executions n, It is determined that this is a permanent failure and the startup process is abnormally terminated.

Next, other embodiments of the present invention will be described.

FIG. 5 is a block diagram of another embodiment of the invention. In FIG. 5, a data processing device 101 includes power supplies 102 and 103, an initial microprogram load control section 104, and a power cutoff circuit 10.
5, clock circuit adapter 106, clock circuit 107,
It consists of a time detection circuit 108, a power supply circuit 109, a memory circuit control section 112, and a memory circuit 113 for holding the number of times the power is cut off. Here, the initial microprogram load control section 104 corresponds to the service processor 3 in FIG. Reference numeral 110 indicates a range to which power is supplied by the power supply device 102. Similarly, 111 indicates the range to which power is supplied by the power supply device 103, and it is assumed that the power supply device 103 is always in a power supply state. Since the memory circuit 113 is always supplied with power from the power supply device 103, its stored data is always saved. It is assumed that elements within the data processing device 101 that are not shown in FIG. 5 are included in the power supply range 110.

The initial microprogram load control unit 104 sets an arbitrary value to the clock circuit 107 via the clock circuit adapter 106. In addition, the initial microprogram load control unit 104 accesses data (number of times the power is turned off) in the memory circuit 113 via the memory circuit control unit 112 . When the time detection circuit 108 detects that the clock circuit 107 has clocked a predetermined time, the power supply circuit 109 powers on the power supply device 102 . On the other hand, according to instructions from the initial microprogram load control section 104, the power cutoff circuit 10
5 serves to turn off the power to the power supply device 102.

Next, the operation of the embodiment shown in FIG. 5 will be explained according to the flowchart shown in FIG.

When the data processing device 101 is powered on,
Initial microprogram load control section 1
Initial microprogram loading is executed under the management of 04. If the initial microprogram load is successful, the power-off count of the memory circuit 113 is cleared and the startup process ends.
If it is not successful, the initial microprogram load control unit 104 performs the initial microprogram load again (retry operation). Here, if the predetermined n times are unsuccessful, the initial microprogram load control section 104 loads the memory circuit control section 112.
After accessing the memory circuit 113 via the memory circuit 113 and updating its contents (the number of times the power is turned off), the power-on time is set to the clock circuit 107 via the clock circuit adapter value 106, and the power is input to the power cut-off circuit 105. A disconnection instruction is issued and the power to the power supply device 102 is disconnected. As a result, elements other than those shown in the power supply range 111 are powered off.

On the other hand, the clock circuit 107, which is always supplied with power by the power supply device 103, continues to clock, and outputs a signal when the set time comes. This is the time detection circuit 1
08 detects this, and the power supply circuit 109 turns on the power to the power supply device 102 . As a result, the initial microprogram load control unit 104 executes the initial microprogram load again.

Furthermore, when the initial microprogram load control unit 104 fails to retry the initial microprogram load, it refers to the memory circuit 113 via the memory circuit control unit 112, and when the contents (the number of times the power is turned off) reaches a certain value. , the startup process ends abnormally.

〔Effect of the invention〕

According to the present invention, even if the error rate increases due to the miniaturization of semiconductor cell areas now and in the future, it is possible to retry more unstable areas and retry wider areas, and to start up data processing equipment. Since recovery from occasional failures can be greatly improved, system reliability can be greatly improved. Furthermore, if recovery from a failure is impossible, it is possible to prevent the power-off/re-on operation from falling into an infinite loop.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a data processing device according to the present invention, FIG. 2 is a diagram showing an example of the configuration of the power supply control section in FIG. 1, and FIG. 3 is a diagram showing an example of the configuration of the power supply control section in FIG. Diagram showing another configuration example, No. 4
The figure is a flowchart for explaining the operation of FIG. 3, and FIG. 5 is a block diagram of another embodiment of the present invention.
FIG. 6 is a flowchart for explaining the operation of FIG. 5. 1...Data processing device, 2...Central processing unit, 3...
Service processor, 4... microprocessor,
5... Control memory, 6... Power supply device control unit, 7, 8... Power supply device, 9, 10... Power supply range, 11... SVP
READY line, 12...Power switch, 13...Power control line, 101...Data processing device, 102, 103
...Power supply device, 104...Initial microprogram load control unit, 105...Power cutoff circuit, 1
06... Clock circuit adapter, 107... Clock circuit, 1
08...Time detection circuit, 109...Power supply circuit, 1
DESCRIPTION OF SYMBOLS 10, 111...Power supply range, 112...Storage circuit control part, 113...Storage circuit.

Claims (1)

[Scope of Claims] 1. A processing device, a service processor of the processing device, a system power supply that supplies power to the processing device and the service processor, and a power supply control unit that controls turning on/off of the system power supply. In the data processing device, the service processor has means for reporting operation status to the power supply control unit when the service processor receives system power and operates normally, and the power supply control unit includes: , means for measuring the elapse of time since the system power is turned on, and means for turning off the system power and then turning it on again if there is no operational status report from the service processor within a certain period of time after the system power is turned on. and means for counting the number of times the system power is turned off and turned on again, and means for inhibiting the system power from being turned on again when the number of times the system power is turned off and turned on again reaches a predetermined value. Processing device restart method. 2 The service processor executes an initial program load when the system power is turned on,
2. The method for restarting a data processing device according to claim 1, wherein when the abnormality is detected, a report indicating that the device is operable is not made to the power supply control section. 3. The method for restarting a data processing apparatus according to claim 1 or 2, wherein the system power is turned on again after a certain period of time has elapsed since the system power was turned off.