JPH0472260B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic integrated circuit, and more particularly to a logic integrated circuit that can asynchronously transfer data to and from an external device in a large-scale integrated circuit using a precharge data bus. The present invention relates to an input/output control method that allows data to be transferred asynchronously to and from an external device in a large-scale integrated circuit using a data bus.

As microcomputers have recently become widely used in various fields, it has become necessary to connect the microcomputers to other processing devices and to transfer data between them. In addition, recent microcomputers operate at high speed, so one machine
A circuit configuration is used in which the data bus is precharged during a portion of the cycle, and input/output data is transferred via the data bus by controlling a switch based on, for example, the contents of a register.

Conventionally, in logic integrated circuits such as microcomputers, when data is transferred between a connected external device and an internal register, the internal clock is synchronized with the external device's clock, or the precharge method is used. This is achieved by a method that uses the circuit configuration of the data bus, which does not employ a conventional method.

However, in the former method, in order to transfer data between multiple devices with different clocks,
Synchronization requires complex circuitry, and the latter method requires complex internal register and internal bus interface circuits.

An object of the present invention, in order to eliminate such conventional drawbacks, is to perform high-speed operation using a pre-charge type data bus configuration, and to perform high-speed operation between internal registers and devices that operate using a separate external clock system. Another object of the present invention is to provide a logic integrated circuit that can perform data transfer without substantially increasing the circuit scale.

In order to achieve the above object, a logic integrated circuit of the present invention includes an internal data bus 4, a memory 11 connected to the internal data bus 4, an arithmetic circuit 10, and registers 17 and 18. 1, the clocks φ _OM , φ _1M , φ 1M ,
A clock generator 19' that generates φ _2M and φ _3M , and gate circuits G3 to G6 that input the output of the clock generator 19' and output clocks φ ₀ , φ ₁ , φ ₂ , and φ ₃ of predetermined frequencies. , precharge timing generating means 23 to 2 which receive the outputs of the gate circuits G3 to G6 and generate a precharge timing signal 30 for precharging the internal data bus 4.
5, G2, G7 to G11, and a precharge timing signal 30 of a first period set by a clock of a predetermined frequency output from a precharge timing signal generating means. means T _1-1 and T _1-o for precharging the internal data bus 4, and clocks φ ₀ , φ ₁ , φ ₂ , φ of predetermined frequencies output from the gate circuits G3 to G6 of the clock generation circuit 19; an internal control timing generation circuit 20 that periodically generates internal control timing signals 34 and 33 at the timing of the second period set by ₃ ; Registers 17, 18 and internal data bus 4
A signal transmission circuit T _2-1 that transfers data between
T _3-1 , T _2-o , and T _3-o are connected to the logic integrated circuit 1 via external buses 3, 5, 6, 7, and 8, and the logic integrated circuit 1 When a data transfer request 32 is received from an external device 2 that operates with a clock CLK1 different from a clock with a predetermined frequency of While the output of the clocks φ ₀ , φ ₁ , φ ₂ , φ ₃ having the above-mentioned predetermined frequencies from the output terminals of G3 to G6 is temporarily stopped, the internal control timing generation circuit 20 outputs the timing signal 6 supplied from the external device 2. In response to this, a control timing signal 34 for external data transfer is generated, and at the timing of the control timing signal 34 for external data transfer, the signal transmission circuit T _2-1 ,
T _3-1 , T _2-o , and T _3-o transfer data between registers 17 and 18 and internal data bus 4 to generate logic data via external buses 3, 5, 6, 7, and 8. Data transfer between the integrated circuit 1 and the external device 2 is performed, and the control timing signal 3 for external data transfer is executed.
At the timing of 4, the signal transmission circuits T _2-1 , T _3-1 ,
Before T _2-o , T _3-o transfer data between registers 17, 18 and internal data bus 4, precharge timing signal generating means G2,
G7 to G11 are means _T1-1 for precharging and generating a precharge timing signal 30 using the outputs _φ0M , _φ1M , _φ2M , _φ3M of the clock generator 19' in response to the data transfer request 32; T _1-o uses precharge timing signal 30 to precharge internal data bus 4 and logic integrated circuit 1
comprises an interface input/output circuit 15 connected to an internal data bus 4 and an external bus 3, and the interface input/output circuit 15 responds to a timing signal 6 supplied from an external device 2 to It is characterized by executing data transfer between the data bus 4 and the external bus 3.

Internal data transfer within the logic integrated circuit 1 between the internal data bus 4 and the registers 17, 18 is as follows:
While the clock CLK1 can be executed according to the internal operating clock of the logic integrated circuit 1, the clock CLK1 is different from the frequency of the internal operating clock of the logic integrated circuit 1.
When an asynchronous data transfer request 7 is received from an external device 2 operating at , must be executed in accordance with the timing of the asynchronous data transfer request 7 from the external device 2.

On the other hand, the precharge-type internal data bus 4 inside the logic integrated circuit 1 needs to be precharged periodically according to the internal operation clock of the logic integrated circuit 1 when transferring internal data.
When performing an asynchronous external data transfer with an external device 2, the precharging of the internal data bus 4 by the cycles of the internal operating clock of the logic integrated circuit 1 causes asynchronous external data transfer via this internal data bus 4. There is a risk that this may interfere with the transfer data signal during transfer.

Therefore, when performing such external data transfer, the internal data bus precharge period 30 for internal data transfer and the internal data bus
The generation of clocks φ ₀ , φ ₁ , φ ₂ , φ ₃ of a predetermined frequency that set the data transfer periods 34 and 33 is temporarily stopped, and the control timing signal for external data transfer is stopped in response to the asynchronous data transfer request 7. This external data transfer control timing signal 34 is used to control the signal transmission circuits T _2-1 , T _3-1 , T _2-o ,
T3 _-o signaling is performed to enable the desired external data transfer described above.

Furthermore, since it is necessary to precharge the internal data bus 4 before the above-mentioned desired external data transfer, the precharge means T _1-1 and T _1-o are activated as described above in response to the external data transfer request 7. The internal data bus 4 is precharged prior to the desired external data transfer.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a MOS digital large-scale integrated circuit to which the present invention is applied.

In FIG. 1, a MOS digital large-scale integrated circuit (hereinafter referred to as LSI) 1 and a device (for example, a digital computer) 2 that is connected to it and performs data transfer are shown. It is assumed that the clocks are operating with different frequencies.

The LSI 1 includes an arithmetic circuit (ALU) 10, a data storage device (RAM) 11, a plurality of data registers (REG1, 2) 17, 18, and a storage device (ROM) 1 in which programs for controlling internal operations are stored.
4, an input/output circuit (input/output buffer) 15 serving as an interface with an external digital computer, and a timing control circuit (control) 16.

The LSI 1 and the digital computer 2 have an n-bit data bus 3, an m-bit function bus 5, a chip select signal (CS) 7, a read/write control signal (R/W) 6, and a data transfer timing signal. (IE) Connected with 8.

FIG. 2 is a block diagram of a data transfer circuit using the bus precharge method used inside the LSI of FIG. 1, and FIG. 3 is an operation time chart of FIG. 2.

A data transfer circuit using a bus precharge method, which is generally used for high-speed operation in MOS/LSI, has a data bus D, a precharge transistor T 1 , and a precharge transistor T ₁ as shown in FIG.
It is composed of switch transistors T ₂ and T ₃ , a switch control register 17, a register 18 for setting transfer data, and the like. Also, A is a control signal for precharging the bus, and B is a register 17.
, C is a control signal that gives the timing to output the contents of register 17 to the bus, D is a data bus indicating one of multiple buses, and E is a control signal to take the contents of the bus into register 18. .

The LSI 1 operates in a constant cycle (Tcyc) as shown in FIG. In this cycle,
First, signal A precharges the parasitic capacitance C ₁ of data bus D through transistor T ₁ (see FIG. 3A). This causes data bus D to be at logic level "1" (see FIG. 3D).
After the precharge is completed, the signal C outputs the output B of the register 17 to the data bus D (see FIGS. 3B and 3C). At this time, if the contents of the register 17 are "1", the transistors T ₂ and T ₃ are turned on, and the charge of the parasitic capacitance C ₁ is transferred to the transistor
The data is discharged through T ₂ and T ₃ .
Bus D goes to the "0" state (see low level in Figure 3D). On the other hand, if the output B of the register 17 is "0", no current flows through the transistors T ₂ and T ₃ ;
Data bus D is kept in the “1” state (third
(see high level in Figure D). The state of this data bus D is transmitted to register 18 through inverter G1.
Set by timing pulse E.

FIG. 4 is a configuration diagram of a data transfer control circuit in an LSI showing an embodiment of the present invention, and FIGS. 5 and 6 are operation time charts in FIG. 4.

Data buses 3 and 4 in FIG. 4 have an n-bit configuration. In addition to the circuit shown in FIG. 1, a clock generation circuit 19 and an internal control timing generation circuit 20 that generate control timing
It is shown. φ ₀ , φ ₁ , φ ₂ , and φ ₃ are four-phase overlapping basic clocks that control each part within the LSI 1. Signals A, C, and E in FIG. 3 correspond to signals 30, 34, and 33 in FIG. 4, respectively;
control signal 35, internal normal operation stop signal (Halt) 31, and external LSI1
A signal (Halt-D) 32 is shown that requests data transfer to the internal registers 21 and 22 of.

FIG. 5 shows the timing during normal operation, and FIG. 6 shows the timing of register data read operation when a data transfer request is received from the outside.

In FIG. 5, since the chip select signal 7 for selecting LSI 1 is not input, the 4-phase clock φ ₀ generated by the clock generation circuit 19 shown in FIG.
~ _φ3 , the internal circuit of LSI1 operates.

A precharge signal 30, a data output signal 34, and a data input signal 3 corresponding to the signals A, C, and E.
3 is the internal control timing generation circuit 20 of FIG.
It is generated by combining the basic clocks φ ₀ to φ ₃ . In this state, the input/output control signal 35, data transfer request signal (Halt-D)
32 and the operation stop signal (Halt) 31 are not generated.

On the other hand, when a data transfer request is received from an external digital computer, the transfer request code is given by the function signal 5, and as shown in FIG. 6c, when the chip select signal 7 is input, The control circuit 16 shown in FIG. 4 detects this and sends a data transfer request signal 32 to the clock generation circuit 19. As a result, the clock generation circuit 19 outputs a signal (Halt) 31 indicating that normal operation is to be stopped.

In the clock generation circuit 19, clocks _φ0 to _φ3
is stopped, and a stop signal (Halt) 31 is output with a delay of 1/4 cycle (see FIG. 6l). During this 1/4 cycle, a precharge signal 30 is output by a circuit operation different from the normal time, and the data bus 4 is
is precharged to the level "1" (see m and n in Figure 6). A data output signal 34 is generated from the internal control timing generation circuit 20 in response to an external timing signal 6. Data output signal 34
turns on transistors T _3-1 to _{T 3-o} and transfers the contents of one of registers 17 to 18 to the transistor
It is output to the data bus 4 through T _2-1 to _{T 2-o} (see operation in FIGS. 2 and 3). The contents of data bus 4 are I/O controlled by timing signal 6.
The control signal 35 is output to the external data bus 3 of the LSI 1 and read out to the digital computer 2. When one data transfer is completed, the chip
Since the select signal 7 disappears, this is detected by the control circuit 16 in FIG. 4, and the basic clocks φ ₀ to φ ₃ are generated again, and normal operation begins.

Figure 7 shows the basic clock (φ ₀
~φ ₃ ), a precharge signal 30, and an operation stop signal (Halt) 31. FIG. 8 is a waveform diagram for explaining the operation of the circuit diagram of FIG. 7 in more detail.

The 4-phase clock generator 19' generates 4-phase overlapping clocks (φ _0M , φ _1M , φ _2M , φ _3M ) shown in FIGS. 8a to 8d from the single-phase input clock (CLK2).
occurs.

As shown in FIG. 8f, when the data transfer request signal (Halt-D) 32 of '1' is input, the NAND
When the flip-flop ₂₄ is set at the _1M.2M timing generated by the gate G2, the Q output _Q24 of the flip-flop 24 becomes '1' as shown in FIG. 8g. Next, after the output Q of the flip-flop 14 is set, the flip-flop 23 is set at a timing of _3M .
The Q output _Q23 of the flip-flop 23 is also shown in Fig. 8h.
It becomes '1' as shown in . flip flop 2
While the Q output _Q23 of 3 is '0', the 4-phase overlap clock 4-phase clock signals _φ0M to φ3M input to the NAND gates G3 to _G6 are directly output as the basic clocks _φ0 to _φ3. However, when the Q output _Q23 of the flip-flop 23 becomes '1', the signal transmission function of the NAND gates G3-G6 is stopped, and the basic clock _φ0 is transmitted as shown in FIG. ~ _φ3 output is stopped. On the other hand, when the clock signal _φ0M is '1' while the output Q24 of the flip-flop ₂₄ is '0', the AND gate G1
The output of 1 becomes '1' as shown in FIG. 8n, and the flip-flop 25 is reset. on the other hand,
When the flip-flop 24 is set and its Q output _Q24 becomes '1', when the clock signal _φ2M is '1', the output of the AND gate G10 becomes '1' as shown in FIG. Flip Flop 2
Set 5. Therefore, after that, when the data transfer request signal (Halt-D) 32 becomes ``0'', the flip-flop remains unchanged until the reset signal of AND gate G1 becomes ``1'' as shown in FIG. 8n. The Q output Q ₂₅ of the flop 25, ie, the stop signal (Halt-D) 31, holds ``1'' as shown in FIG. 6l and FIG. 8o.

While the data transfer request signal (Halt-D) 32 is '0', the clock signal φ ₀ is '1', and when the clock signal φ ₂ is '0', as shown in FIG. The output of the AND gate G7 becomes '1' and is output as the data bus precharge signal 30 during normal operation via the OR gate G9 as shown in FIG. 6m.

The data transfer request signal (Halt-D) 32 becomes '1', and the Q output _Q23 of the flip-flop 23 becomes '1'.
1', the Q output of flip-flop 25
During the period when Q ₂₅ is '0', the output of AND gate G8 becomes '1' as shown in Figure 8q, and the data during data transfer with the outside via OR gate G9.
The bus precharge signal 30 is output as shown in FIG. 6m.

Data transfer request signal (Halt-D) 32 is “0”
, the flip-flops 24 and 23 are reset at each timing, and the NAND gates G3 to
The basic clocks φ ₀ to _{φ 3} are output again from G6, and the output of the flip-flop 24 and the clock φ _0M are ANDed by the NAND gate G11 and inputted to the R terminal of the flip-flop 25 to reset it. .

As a result, the stop signal (Halt) 31 becomes "0" and returns to the normal operating state.

In addition, in FIG. 6m, the bus precharge signal 30 generated during data transfer with the outside
(shown with diagonal lines) is the bus frequency that occurs during normal operation.
Although it happens to occur at the same time as the precharge signal 30, it is of course possible to generate it at any different time.

As explained above, according to the present invention, the MOS
When performing high-speed operation using a precharge data bus configuration in a large-scale integrated circuit configured with Furthermore, since a bus precharge signal is generated independently during data transfer with the outside, there is no need to add a circuit for each bit of multiple internal registers, minimizing the increase in the circuit size of the integrated circuit. You can stop it and transfer data to/from the outside.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a logic integrated circuit to which the present invention is applied, FIG. 2 is a diagram of a bus precharge data transfer circuit used in the circuit of FIG. 1, and FIG. FIG. 4 is a configuration diagram of a data transfer control section in a logic integrated circuit showing an embodiment of the present invention. FIGS. 5 and 6 are operation time charts in FIG. 4, and FIG. This figure is a block diagram of a circuit that generates the clock, precharge signal, stop signal, etc. in FIG. 4, and FIG. 8 is a waveform diagram for explaining in more detail the operation of the circuit structure of FIG. 7. 1: Logic integrated circuit (LSI), 2: External device (digital computer), 3: External data bus, 4:
Internal data bus, 7: Chip select signal,
Data transfer request, 19: Clock generation circuit, 2
0: Internal control timing generation circuit, 17, 18,
21, 22: Register, 23, 24, 25: Flip-flop.

Claims (1)

[Scope of Claims] 1. In a logic integrated circuit comprising an internal data bus, and a memory, an arithmetic circuit, and a register connected to the internal data bus, a clock generator that generates a clock of a predetermined frequency; a gate circuit which inputs the output of the clock generator and outputs a clock of a predetermined frequency; and a precharge timing circuit which receives the output of the gate circuit and generates a precharge timing signal for precharging the internal data bus. a clock generating circuit comprising a signal generating means; and a clock generating circuit that periodically generates the internal data using a precharge timing signal of a first period set by the clock having the predetermined frequency outputted from the precharge timing signal generating means.・Means for precharging the bus; and an internal control for periodically generating an internal control timing signal at the timing of a second period set by the clock of the predetermined frequency output from the gate circuit of the clock generation circuit. a timing generation circuit, and the register and the internal data at the timing of the second period of the internal control timing signal.
The circuit further comprises a signal transmission circuit that transfers data to and from the bus, the signal transmission circuit being connected to the logic integrated circuit via an external bus, and having a clock different from the clock of the predetermined frequency of the logic integrated circuit. When a data transfer request is received from an operating external device, the gate circuit of the clock generation circuit is closed in response to the data transfer request, and the output of the clock of the predetermined frequency from the output terminal of the gate circuit is temporarily stopped. Meanwhile, the internal control timing generation circuit generates a control timing signal for external data transfer in response to a timing signal supplied from the external device,
The signal transfer circuit transfers data between the register and the internal data bus at the timing of the external data transfer control timing signal, thereby connecting the logic integrated circuit and the external device via the external bus. Data transfer between
Prior to the signal transfer circuit transferring data between the register and the internal data bus at the timing of the external data transfer control timing signal, the precharge timing signal generating means responds to the data transfer request. In response, the output of the clock generator is used to generate a precharge timing signal, the means for precharging uses the precharge timing signal to precharge the internal data bus; The interface input/output circuit is connected to the data bus and the external bus, and the interface input/output circuit is connected to the internal data bus and the external bus in response to a timing signal supplied from the external device. A logic integrated circuit characterized in that it performs data transfer to and from an external bus.