JPH0472409B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a capacitive load drive circuit that achieves a fast fall speed with a circuit that consumes little steady current.

[Conventional technology]

FIG. 2 is a diagram showing a conventional circuit in which a totem pole type output circuit drives a capacitive load in a TTL circuit. In this figure, T _IN is an input terminal, T _OUT is an output terminal, N ₁ to N ₄ are NPN transistors, C _OL is a capacitive load whose capacitance is _CL ,
B is a power supply whose voltage is V _CC , and I _O is a constant current circuit that supplies constant current I.

In this circuit, when the input terminal T _IN transitions from low level to high level, the NPN transistor
N ₁ and N ₂ turn on and discharge the capacitive load C _OL , but
This discharge current is limited by β _O ·I, where β _O is the common emitter current amplification factor of the NPN transistor N ₂ . Therefore, the falling speed of the output terminal T _OUT does not become faster than β _O ·I/ _CL .

[Problem that the invention seeks to solve]

In the conventional circuit as described above, in order to speed up the fall, it is sufficient to increase the value of the constant current I, but there is a problem that current consumption increases.

The present invention was made to solve these problems, and an object thereof is to obtain a capacitive load drive circuit with low current consumption and a fast falling speed.

[Means for solving problems]

The capacitive load drive circuit according to the present invention includes:
a first transistor having a base connected to a first input terminal to which a pulse input signal is applied and an emitter connected to ground; a first constant current source connected between the collector of the first transistor and a power supply; a second transistor whose base is connected to the collector of the transistor and whose emitter is connected to ground; a capacitive load connected between the collector of this second transistor and ground; and a pulse input signal applied to the first input terminal. The second input signal is given an inverse relationship
a third transistor whose base is connected to the input terminal of the transistor and whose emitter is connected to the ground; a second constant current source connected between the collector of the third transistor and the power supply;
a fourth transistor whose base is connected to the collector of the second transistor; a resistor connected between the collector of the third transistor and the emitter of the fourth transistor; and a resistor between the collector of the fourth transistor and the power supply. It consists of a current mirror circuit whose input is connected between the collector of the first transistor and the power supply, and a fifth transistor for charging the capacitive load, and the collector of the second transistor and the capacitive load. An output terminal is provided in between.

As a current mirror circuit, a sixth transistor having a polarity opposite to that of the first, second, third, fourth, and fifth transistors whose base and collector are connected to the input and whose emitter is connected to the power supply; A seventh transistor having the same polarity as the sixth transistor has its base connected to the base of the sixth transistor, its emitter connected to the power supply, and its collector output.

[Effect]

In this invention, when the capacitive load is discharged by the inverted pulse input signals applied to the first and second input terminals, the fourth transistor conducts and the second transistor controls the discharge. A drive current is applied to the base of the second transistor by a current mirror circuit, and the collector of the second transistor is applied to the base of the second transistor.
The amount of current between the emitters increases instantaneously.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a capacitive load drive circuit according to the present invention. In this figure, the same symbols as in FIG. 2 indicate the same parts, T _IN1 and T _IN2 are the first and second input terminals, _N11 to _N15 are the first to fifth transistors which are NPN transistors,
I ₀₁ and I ₀₂ are the first, which supplies constant currents I ₁ and I ₂ respectively;
In the second constant current source, P ₁ and P ₂ are sixth and seventh transistors made of PNP transistors, and M is a current mirror circuit made of the sixth and seventh transistors P ₁ and P ₂ .

Next, the operation will be explained.

First, consider the case where the first input terminal T _IN1 changes from high level to low level and the second input terminal T _IN2 changes from low level to high level in a state where the capacitive load C _OL is sufficiently charged. At this time, both the second and third transistors N ₁₂ and N ₁₃ are turned on.
Since the base current of the second transistor _N12 is _I1 , if the common emitter current amplification factor of the second transistor _N12 is β, then the second transistor _N12
The discharge current flowing from the capacitive load C _OL to the collector of is β·I ₁ .

At this time, since the third transistor _N13 is on at the same time, the voltage across the terminals of the capacitive load _COL (=
When the output terminal voltage) is V _CL , a current of (V _CL −V _BE14 )/R ₁ flows through the collector of the fourth transistor N ₁₄ . This current is fed back to the base of the second transistor N ₁₂ via the current mirror circuit M, so the total base current of the second transistor N ₁₂ is I ₁ + (V _CL − V _BE14 )/R ₁ becomes. Therefore, the discharge current flowing from the capacitive load C _OL through the collector of the second transistor N ₁₂ is β・[I ₁ + (V _CL − V _BE14 )/R ₁ ], and discharges with a large current in a short time. be able to.

Also, when the discharge of the capacitive load C _OL is completed, the first input terminal T _IN1 is at high level, and the second input terminal
When T _IN2 is at a low level and the capacitive load C _OL is being charged by the fifth transistor N ₁₅ and the second constant current source I ₀₂ , there is no current to the current mirror circuit M, so the steady current consumption can be reduced.

〔Effect of the invention〕

As explained above, the present invention includes a first transistor whose base is connected to a first input terminal to which a pulse input signal is applied, and whose emitter is connected to ground, and a first a constant current source, a second transistor whose base is connected to the collector of the first transistor and whose emitter is connected to ground, a capacitive load connected between the collector of the second transistor and ground,
A third transistor whose base is connected to the second input terminal and whose emitter is connected to ground, to which an input signal having an inverse relationship with the pulse input signal applied to the input terminal of the transistor is applied, and between the collector of the third transistor and the power supply. a second constant current source connected, a fourth transistor whose base is connected to the collector of the second transistor, and a collector of the third transistor;
a resistor connected between the emitter of the fourth transistor; a current mirror circuit having an input connected between the collector of the fourth transistor and the power supply; and an output connected between the collector of the first transistor and the power supply; It consists of a second transistor with an emitter, a third transistor with a base, and a fifth transistor for charging a capacitive load whose collector is connected to a power supply, and between the collector of the second transistor and the capacitive load. Since an output terminal is provided at the terminal, the effect is that the fall speed can be increased with low current consumption.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a capacitive load drive circuit according to the present invention, and FIG. 2 is a diagram showing a conventional capacitive load drive circuit. In the figure, T _IN1 and T _IN2 are the first and second input terminals, T _OUT is the output terminal, N ₁₁ to _{N 15} are the first to fifth transistors, C _OL is the capacitive load, B is the power supply,
I ₀₁ and I ₀₂ are first and second constant current sources, M is a current mirror circuit, and P ₁ and P ₂ are sixth and seventh transistors. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first transistor whose base is connected to a first input terminal to which a pulse input signal is applied and whose emitter is connected to ground, and a first transistor connected between the collector of this first transistor and a power supply. a constant current source; a second transistor having a base connected to the collector of the first transistor and an emitter connected to ground; a capacitive load connected between the collector of the second transistor and the ground; a third transistor having a base connected to a second input terminal to which a pulse input signal having an inverse relationship with an input signal applied to the input terminal of the third transistor is connected, and an emitter connected to the ground;
a second constant current source connected between the collector of the third transistor and the power supply; a fourth transistor whose base is connected to the collector of the second transistor; a current mirror circuit having an input connected between the collector of the fourth transistor and the power supply, and an output connected between the collector of the first transistor and the power supply; , an emitter in the second transistor, a base in the third transistor,
a fifth transistor for charging a capacitive load, the collector of which is connected to a power source, and an output terminal is provided between the collector of the second transistor and the capacitive load. drive circuit. 2. A first transistor whose base is connected to a first input terminal to which a pulse input signal is applied and whose emitter is connected to ground; a first constant current source connected between the collector of this first transistor and a power supply; a second transistor whose base is connected to the collector of the first transistor and whose emitter is connected to ground; a capacitive load connected between the collector of the second transistor and the ground; and a capacitive load applied to the first input terminal. a third transistor having a base connected to a second input terminal to which a pulse input signal having an inverse relationship with the input signal is applied, and an emitter connected to the ground;
a second constant current source connected between the collector of the third transistor and the power supply; a fourth transistor whose base is connected to the collector of the second transistor; a resistor connected between the emitters of the transistor, and an emitter connected to the second transistor;
a fifth transistor for charging a capacitive load having a base connected to the third transistor and a collector connected to the power supply;
transistor, with base and collector at the input,
the first and second emitters connected to the power source;
a sixth transistor having a polarity opposite to that of the third, fourth, and fifth transistors; a current mirror circuit consisting of a transistor of the same polarity and a seventh transistor of the same polarity;
A drive circuit for a capacitive load, characterized in that an output terminal is provided between the collector of the transistor and the capacitive load.