JPH0473175B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Prior Art] Conventionally, as this type of semiconductor memory device, the one shown in FIG. 3 is known. This semiconductor memory device also includes a data register 102 in the memory cell array 101, and has a function of outputting image data, etc. from this data register 102 asynchronously with random access (a semiconductor memory device having such a function This is called a dual portram, and NEC Corporation's μPD41264C is well known). The function of the dual port ram shown in FIG. 3 will be explained below with reference to the timing chart shown in FIG. 4. First, data transfer terminal TR (bar)
After a low level signal is supplied to the chip select terminal CE1 (bar), the chip selection terminal CE1 (bar) is shifted to a low level and a row address is taken in. As a result, one row of data in the memory cell array 101 specified by the row address is transferred to the data register 102 having the same storage capacity. Next, when a low level signal is supplied to the chip selection terminal CE2 (bar), the column address is taken in, and data is serially transmitted from the address specified by this column address through the register output dedicated terminal SO (bar). Output.

[Problems to be Solved by the Invention] When attempting to display a window or the like using the conventional dual port RAM described above, there is a problem in that the timing becomes complicated. For example, as shown in FIG. 5, the memory cell array 101 has 512
It has a storage capacity of 1024 rows x 1024 columns, of which
If you display 400 rows x 640 columns of data and display the data indicated by diagonal lines in a window, the image will be displayed even though the actual window data is stored in the area indicated by solid lines. The information must be displayed as if it were stored in the area indicated by the broken line. Therefore, in the conventional example, data is transferred during the horizontal synchronization period, and the control for the window described above is achieved by transferring data to the display area by software, or by transferring data while displaying, or in the case of the μPD41264C mentioned above, real-time data is transferred. The transfer function is realized in one of two ways. That is, in the example of FIG. 5, at timing C, n
The row data (1024 bits) is once transferred to the register 102, the window data is transferred again at timing A, and the data for the original display (data on the nth line) is transferred again in real time at timing B. There must be.

Therefore, the present invention provides a semiconductor memory device that can easily display the above-mentioned window display.

[Means, operations, and effects for solving the problems] The present invention provides a memory cell array having a plurality of memory cells arranged in a matrix, and a memory cell array having a plurality of memory cells arranged in a matrix, A semiconductor memory device comprising a data register that temporarily stores data of a memory cell to which it belongs and outputs it serially, a register that stores a transfer start column address and a transfer end column address, respectively, and a register that temporarily stores data in the data register. Of the data,
It is characterized by further comprising a mask transfer control means that enables output of only data specified by a transfer start column address and a transfer end column address and disables output of other data, and controls window display or overlapping of figures. When matching, etc.,
The mask transfer control means selectively outputs data to be excluded for window display among the data of each row read out sequentially. As a result, it is possible to display a window or the like without setting complicated timing.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention, and 7 is a memory cell array having a plurality of bits arranged in 128 rows and 128 columns. CE1 (bar) is the chip activation main clock, which latches the row address to the address input buffer 4, transfers the instruction TR (bar) to the row address decoder 5, and activates the timing generator 1 for execution. Activate peripheral circuits such as sense amplifiers and sense amplifiers. C.E.
2 (bar) is input to the timing generator 2 after supplying CE1 (bar) to latch the column address. TR (bar) is memory cell array 7
This is the activation input of the timing generator 3 for transferring one row of data from 1 to the data register 13 via the transfer gate 12. This timing generator 3 activates the registers 8 and 9 and the mask transfer control circuit 10 and executes the transfer. Further, WR (bar) is supplied to the timing generator 14, which generates a control signal for writing column addresses into the registers 8 and 9. Upon receiving this activation signal, if CE1 (bar) is already activated and CE2 (bar) becomes active (if TR (bar) and WR (bar) are active), the column address is taken into register 8. It will be done. Furthermore, CE1
The column address is taken into the register 9 at the timing when CE2 (bar) becomes inactive while CE2 (bar) is active. The above operation timing is shown in FIG. After this, the address information input to the registers 8 and 9 is input to the mask transfer control circuit 10,
When data is transferred from this circuit (actually, TR
(bar) is inactivated or CE1 (bar) is inactivated), a signal to control the data transfer gate 12 is generated to transfer areas other than the areas indicated by registers 8 and 9. is stopped by turning off the gate. On the other hand, during normal data transfer, all data for one row is transferred simply by deactivating WR (bar) in Figure 2.
Column address is serial read address counter 1
1. This counter 11 is counted up by the SC clock during serial reading, and the serial reading is repeated. During mask transfer, it is disconnected from the column address input.

The mask transfer control circuit 10 and transfer gate 12 constitute mask transfer control means.

As explained above, in this embodiment, a mask data transfer cycle is executed in advance using registers 8 and 9, and it becomes possible to rewrite part of the contents of the registers that have already been transferred, so that the actual display There is no need to transfer data during the period, and serial read operations can be performed. Further, more complicated window display or overlapping of figures can be performed during the same horizontal scanning period without complicated timing control.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a timing chart of one embodiment, Figure 3 is a timing chart of one embodiment.
This figure is a block diagram of the conventional example, FIG. 4 is a timing chart of the conventional example, and FIG. 5 is a block diagram showing the data storage state when a window is displayed. 7...Memory cell array, 8...Register, 9
...Register, 10...Mask transfer control circuit, 1
2...Transfer gate, 13...Data register.

Claims (1)

[Claims] 1. A memory cell array having a plurality of memory cells arranged in rows and columns, and data that temporarily stores and serially outputs data of memory cells belonging to a row designated by the row address signal in response to a row address signal. A semiconductor memory device comprising a register that stores a transfer start column address and a transfer end column address, respectively, and a transfer start column address and a transfer end column address of data temporarily stored in the data register. 1. A semiconductor memory device further comprising mask transfer control means for enabling output of only data specified by and disabling output of other data.