JPH0473345B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device, and particularly relates to an improvement in a solid-state imaging device using SIT, that is, a static induction transistor.

As a solid-state imaging device using SIT, the starting technology is disclosed in Patent Application Publication No. 15229 of 1982.
The most basic device is disclosed, and more specific and improved versions of this device are disclosed in patent applications No. 204656 of 1982 and No. 157693 of 1982.
It has been proposed as a number.

The basic structure of SIT is similar to that of J-FET (junction field effect transistor), but it has the advantage that the impurity density of the semiconductor layer in which the channel region is formed is low. For example, common J-
In FET, the impurity density of the semiconductor layer in which the channel region is formed is about 10 ¹⁵ to 10 ¹⁷ cm ^-3 , whereas in SIT it is about 10 ¹² to 10 ¹⁵ cm ^-3 .

Therefore, the depletion layer formed in the channel region is formed over a wide range even in a state of thermal equilibrium where no voltage is applied from the outside, and furthermore, the length of the channel is short.

Due to the features described above that are different from ordinary J-FETs, the channel enters a pinch-off state in a state of thermal equilibrium or with the gate slightly reverse biased, and a potential barrier appears just in front of the source electrode. This makes it possible to control the movement of carriers constituting the source-drain current flowing from the source electrode to the drain electrode. That is, the source-drain current is determined by the amount of carriers that cross the potential barrier and reach the drain electrode.

On the other hand, the height of the potential barrier described above changes depending on the drain voltage applied to the drain electrode (with the source electrode as a reference). That is, by applying a drain voltage, electrostatic induction occurs, and since the impurity density in the channel region is low, the height of the potential barrier changes, and furthermore, the peak point of the potential barrier moves.

The height of the potential barrier also changes depending on the accumulation of electron-hole pairs formed by light incident on the channel region. That is, electrons and holes generated near the depletion layer in the channel region move along the potential barrier, are separated, and are accumulated in the gate region. Therefore, the height of the potential barrier changes. The degree of this change corresponds to the amount of incident light. Therefore, by applying an appropriate drain voltage, the source-drain current that flows has a magnitude corresponding to the amount of incident light.

As described above, the height of the potential barrier changes depending on the gate voltage, drain voltage, or incident light. Therefore, for example, if a bias voltage is applied so that the channel remains in the "OFF" state even when light is incident, carriers due to the incident light are accumulated, and then an appropriate readout voltage is applied, Non-destructive readout, that is, image information, that is, the degree of incident light, can be amplified and read out without destroying the accumulated state of carriers. A solid-state imaging device can be configured based on such a principle.

In conventional solid-state imaging devices using SIT, in order to effectively accumulate carriers generated by incident light in the gate region, an insulating layer is interposed between the gate region and the gate electrode. A capacitor was formed between the gate electrode and the gate region.

However, this conventional device has disadvantages in that the structure of the gate portion is complicated and the number of manufacturing steps is increased.

The present invention has been made in view of these points, and an object of the present invention is to provide a solid-state imaging device whose structure and manufacturing process can be simplified.

That is, the present invention forms a gate electrode and a gate region using materials with different forbidden band widths, and forms a depletion layer at the boundary of a heterojunction between the two, thereby equivalently forming a capacitor. The aim is to achieve the above objectives.

Hereinafter, the present invention will be described in detail according to embodiments shown in the accompanying drawings.

FIG. 1 shows an embodiment of a solid-state imaging device using SIT according to the present invention. In this figure, A is a partially cutaway plan view, and B is a partially cutaway plan view.
It is an end view seen from the direction of the arrow in the top view of A. In this diagram B, components that connect each cell are omitted to avoid complicating the diagram.
Further, the end face of a cell corresponding to one pixel, which corresponds to FIG. 1B, is shown enlarged in FIG.

In these figures 1A, B and 2, impurity density using materials such as silicon (Si) is high.
A channel region 12 made of an n ^- layer with low impurity density is formed on the n ⁺ layer substrate 10 .

This channel region 12 is formed. A control gate region 14 made of a p ⁺ layer with high impurity density is provided on the upper surface of the n ⁻ layer. A source region 16 made of an n ⁺ layer with high impurity density is provided around the control gate region 14 . These control gate regions 14 and source regions 16 are arranged in a regular two-dimensional matrix at appropriate intervals, as shown in FIG. 1A. The source region 16 forms a cell corresponding to one pixel.

Between adjacent source regions 16 is a floating gate region 1 made of a p ⁺ layer with high impurity density.
8 is formed. This floating gate region 18 is provided in common to adjacent cells, and is preferably maintained at the same potential as the source region 16 or at a predetermined potential by electrode means (not shown). As a result, a depletion layer or a potential barrier is formed in the channel region 12,
Channel separation between each cell is performed.

Next, a channel region 12 is formed.
A control gate region 14 is provided on the top surface of the n ^- layer.
A silicon oxide (SiO ₂ ) film 20 is formed on the entire source region 16 except for the exposed portion for surface protection. A source electrode 22 is formed in an exposed portion of the source region 16 to connect adjacent cells. The direction of this connection, as shown in FIG. 1A, is a direction that intersects the direction of connection of gate electrodes, which will be described later.

Next, an insulating film 26 is formed over the entire surface of the control gate region 14 except for the exposed portion. This insulating film 26 is formed to prevent a short circuit between the source electrode 22 and a gate electrode, which will be described later.

In the exposed portion of the control gate region 14,
A gate electrode 24 made of a material having a different forbidden band width from that of the control gate region is formed by connecting adjacent cells. The direction of this connection intersects with the direction of connection of the source electrode 22, which makes it possible to read information stored in any cell. That is, any one of the plurality of source electrodes 22 is selected, and the plurality of gate electrodes 2
If any one of 4 is selected, a cell at a position where both electrodes intersect will be selected. At the boundary between the control gate region 14 and the gate electrode 24, the energy band structure is a heterojunction, and the discontinuity of the energy band forms a depletion layer. Therefore, it can be considered that a capacitor is equivalently formed at this boundary portion.

A drain electrode 28 is provided on the side of the substrate 10 opposite to the n ^- layer where the channel region 12 is formed.
is formed.

Next, the electrical equivalent circuit of the solid-state imaging device having the above-described structure, the connection between each electrode, and the connection with the driving means will be described.

FIG. 3 shows the electrical circuit and connections to external devices. Some of the connections with external devices are also shown in FIG. In these figures, a plurality of cells PC corresponding to pixel units are arranged in a second order in a matrix, as shown in FIG. 1A. A read address circuit 30 is connected to each of the plurality of gate electrodes 24, and a read pulse voltage is sequentially applied thereto. On the other hand, the plurality of source electrodes 22 are each connected to the drain of a transistor 40 that performs a switching operation, and the source is connected to the output terminal 3.
8, respectively. The gates of the transistors 40 are each connected to the video line selection circuit 32. The video line selection circuit 32 sequentially outputs selection pulse voltages to the transistors 40, thereby sequentially driving the transistors 40.

For example, the transistor 40 is normally “OFF”
The read address circuit 30 and the video line selection circuit 3 are configured by the SIT in the state of
2 is constituted by, for example, a shift register.

Further, a load resistor 34 and a power source 36 are connected between the output terminal 38 and the ground, that is, the drain electrode 28.
are connected, thereby forming a source-drain current during reading, and further converting the source-drain current into a voltage.

In addition, in Fig. 3, the area indicated by the dashed line
IM corresponds to the part of the structure shown in FIG. 1A etc.

Next, the overall operation of the above embodiment will be explained.

First, when light is incident on each cell, electron-hole pairs are generated in the potential gradient portion formed from the control gate region 14 to the channel region 12. Specifically, the incident light mainly passes through the control gate region 14 and reaches the channel region 12, where electron-hole pairs are generated. Of the generated electron-hole pairs, electrons move toward the drain electrode 28, and holes move toward the control gate region 14 and are accumulated. This accumulation of holes is due to the formation of a capacitor based on a depletion layer between the control gate region 14 and the gate electrode 24.

Through the above operations, image information is accumulated in each cell PC. Next, video line selection circuit 3
A selection pulse voltage is sequentially applied to the plurality of transistors 40 connected to the plurality of source electrodes 22 by the plurality of source electrodes 22 . As a result, the corresponding transistor 40 is driven, and the source electrode 22 and drain electrode 28 of a plurality of cells PC arranged in the corresponding column direction among the cells PC shown in FIG. and is connected to the power supply 36. This completes the preparation for the flow of source-drain current. Note that in this state, each cell
For example, the voltage of the power supply 36 is adjusted so that the PC remains non-conductive.

Through the above operations, a video line from which image information is to be read is selected. Next, the read address circuit 30 selects a plurality of gate electrodes 24.
A pulse voltage is sequentially applied to the two. The cell located on the video line selected by this
The PCs become conductive one after another, and a source/drain current corresponding to the amount of holes accumulated in the control gate region 14, that is, the amount of incident light, flows to the resistor 34, and is further converted into a voltage by the resistor 34, and is output to the output terminal. It is output from 38.

Through the above operation, image information corresponding to the incident light is outputted as a voltage change at the output terminal 38.

In the embodiments described above, the control gate region 14 is surrounded by the source region 16, but it is not necessary to have such a configuration.
The source region 16 may be provided only on a part of the outer periphery of the control gate region 14, or may be provided on the entire outer periphery.

Furthermore, in the above embodiment, holes are accumulated due to light entering the floating gate region 18, resulting in a disadvantage that the cells PC are not well isolated from each other.

Another embodiment that eliminates such inconvenience will be described. 4A and 4B show other embodiments of the present invention, FIG. 4A is a plan view corresponding to FIG. 1A, and FIG. 4B is a plan view corresponding to FIG. 1B. 4B is a corresponding end view taken from arrow V in FIG. 4A; FIG. In this embodiment, the same reference numerals are used for the same components as in the embodiment shown in FIGS. 1 to 3, and the explanation thereof will be omitted.

In the embodiment shown in FIGS. 4A and 4B,
The source region 46 is the control gate region 14
It is not provided around the area, but only on one side.

Further, source region 46 is provided close to floating gate region 18 . That is, if the distance between the source region 46 and the floating gate region 18 is WA, and the distance between the source region 46 and the control gate region 14 is WB, then
The relationship is WA<WB. In this way, the potential barrier formed on the floating gate region 18 side is higher than the potential barrier formed on the control gate region 14 side, so that isolation between the cells PC becomes better.

Furthermore, in this embodiment, an insulating film 26 is formed on the source region 46 and the floating gate region 18.
An aluminum film 44 is formed through the aluminum film. Therefore, floating gate region 1
No light enters the portion 8, and holes are not accumulated in the floating gate region 18. Therefore, isolation between cell PCs becomes better.
Note that the shimmering film 44 may be provided overlapping the gate electrode 24.

Such improvement in isolation between the cells PC can also be achieved by forming the floating gate region 18 deeper in the channel region 12 than in the control gate region 14; This can also be achieved by making the impurity density of the control gate region 18 higher than that of the control gate region 14.

By using one of the above configurations or a combination of multiple configurations, it is possible to improve the separation between cell PCs, and the cell PCs are arranged according to unit area.
The degree of integration can be significantly improved.

Next, the manufacturing process of the solid-state imaging device described above will be explained with reference to FIGS. 5A to 5L.

First, the substrate 10 is made of antimony (Sb).
An n ⁺ type silicon substrate doped with about 10 ¹⁸ cm ^-3 is used. Channel region 12 is formed
The n ^- layer 50 is formed on the (111) plane of the substrate 10 by epitaxial growth. That is, n ^-
Since the layer 50 is a layer in which electron-hole pairs are formed and further separated by incident light and a channel region 12 is formed, it is necessary to sufficiently remove dislocations, defects, etc. It is. this
The n ^- layer 50 is formed to have a thickness of about 5 to 10 μm, and an impurity density of about 10 ¹³ to 10 ¹⁵ cm ^-3 .

Note that in order to prevent recombination of carriers in the n ^- layer 50 and extend the life of the separated carriers, gettering may be applied to heavy metals.

Next, as shown in FIG. 5A, an oxide film 52 is formed over the entire n ^- layer 50 to a thickness of 5000 to 8000 Å. This oxide film 52 is formed by heating the n ^- layer 50 at 1000°C for 1 hour or at 1100°C, for example.
This is done by exposing it to an oxygen atmosphere for about 25 minutes.

Next, wet etching is performed using an appropriate mask, and patterns of the p ⁺ layer 54 corresponding to the control gate region 14 and the p ⁺ layer 56 corresponding to the floating gate region 18 are formed on the oxide film 52. each formed as shown in FIG. 5B,
Further, an impurity serving as an acceptor such as BBr ₃ is implanted to form p ⁺ layers 54 and 56, respectively.
The impurity may be implanted by thermal diffusion after vapor deposition, or by ion implantation. In the case of thermal diffusion, impurities are implanted in an oxygen or wet oxygen (or water vapor) atmosphere at, for example, 1100°C. The thickness of the p ⁺ layers 54, 56 is 1 to 5 μm
The thickness is preferably about 1 to 3 μm.

Next, in order to form an n ⁺ layer 60 corresponding to the source region 16, mask alignment is performed, and a pattern of the n ⁺ layer 60 is formed in the oxide film 52 by wet etching. In this state, an impurity that can serve as a donor, such as arsenic (As), is implanted by thermal diffusion or ion implantation. By this operation, an n ⁺ layer 60 is formed as shown in FIG. 5C.

A DOPOS (phosphorous doped polycrystalline silicon) layer 62 is then formed over the entire surface as shown in FIG. 5D. This DOPOS layer 62 is
It is formed by CVD (chemical vapor deposition) using a gas atmosphere of SiH ₄ and PH ₃ .

Next, a portion of the DOPOS layer 62 is etched by plasma etching using a suitable mask to form an electrode layer 64 corresponding to the source electrode 22. This condition is shown in FIG. 5E. For plasma etching, a gas atmosphere such as CF ₄ , CF ₄ and O ₂ or PCl ₃ is used.

Next, a PSG (phosphorus glass) layer 66 is formed as an interlayer insulating layer over the entire surface as shown in FIG. 5F. This PSG layer 66 is formed by a CVD method, for example, by heating to about 400° C. in a gas atmosphere of SiH ₄ , O ₂ and PH ₃ . Alternatively, it can be carried out by heating to about 750°C in a gas atmosphere of SiH ₄ , H ₂ O and PH ₃ .

Wet etching is then performed using a suitable mask to expose the surface of P ⁺ layer 54 as shown in FIG. 5G.

Next, a transparent electrode layer 7 made of Nesa film (SnO ₂ ) is formed.
0 is formed over the entire surface as shown _in ^FIG .
A heterojunction is formed between the electrode layer 70 and the electrode layer 70 .
As a method for forming the electrode layer 70, for example, first,
A SnO ₂ layer with a thickness of 100 to 500 Å is formed at a relatively high temperature, and then a SnO ₂ layer in which a suitable conductive element such as Sb is implanted is formed on this SnO ₂ layer at a relatively low temperature.
It is formed to a thickness of 2000 to 5000 Å. Instead of the SnO ₂ layer, any material with a wider forbidden band width than silicon may be used. For example, an ITO layer may be formed to form the transparent electrode layer 7.
It may also be set to 0.

Next, plasma etching is performed using a suitable mask, and electrode layer 70 is etched away, except for the portion above p ⁺ layer 54, as shown in FIG. 5I. This operation involves CCl ₄ , CF ₄ , CF ₄ and
This is done using a gas such as O ₂ or PCl ₃ .

Through the above operations, the solid-state imaging device in the embodiment shown in FIGS. 1 to 3 is manufactured. Also, the n ⁺ layer 6 corresponding to the source region 16
The position and shape of 0 can be easily determined by appropriately changing the shape of the mask in the step shown in FIG. 5C.

Next, the formation of the film 44 described in the embodiment shown in FIGS. 4A and 4B will be described with reference to FIGS. 6J to 6L.

First, the area exposed by wet etching
The PSG layer 66 and oxide film 52 are etched as shown in FIG. 5J.

Next, as shown in FIG. 5K, an aluminum coating layer 72 is formed over the entire surface to a thickness of about 1.0 μm. This shimmering layer 72 is formed by vacuum deposition using an electron beam or resistance heating, or by sputtering.

Next, a portion of the phosphor layer 72 is etched using a suitable mask, and an electrode layer 80 made of aluminum is formed on the substrate 10. This condition is shown in FIG. 5L. Formation of this electrode layer 80 is performed, for example, by a method such as sintering.

Note that the shimmering layer 72 is connected to the p ⁺ layer 56 corresponding to the floating gate region 18,
It has a function as an electrode for applying voltage to the floating gate region 18.

The manufacturing process described above is only an example, and other manufacturing processes may be used. Also, other materials may be used, and if the channel region and p ⁺ region are formed of GaAs,
The gate electrode may be formed of AlGaAs and may be hetero-coupled. Further, the n ^- layer 50 may be an intrinsic semiconductor layer into which no impurity is implanted.

In all of the above embodiments, the channel is formed by the n ^-layer , but it is
The channel may be formed by a p ^- semiconductor layer. Furthermore, the same effect can be obtained even if the source and drain correspond to each other in the opposite manner to those in the above embodiment. The same applies to the selection of video lines or the application of pulse voltages for reading, and the above embodiments may be reversed.

Further, a normal transistor may be used as the driving transistor 40, or the transistor 40, the read address circuit 30, and the video line selection circuit 32 may be integrated with the imaging device to form an integrated circuit. . As for the material,
Although silicon is mainly used, the present invention is not limited to this in any way, and germanium,
- group compound semiconductors etc. can also be used. The heterojunction in the control gate section is silicon-
A heterojunction using germanium may also be used. cell
The PCs do not necessarily need to be arranged in a two-dimensional matrix, but may be arranged in a line.

Furthermore, in order to obtain color image information, it is necessary to
For example, configure a matrix of PCs corresponding to red (R), green (G), and blue (B), apply a color filter to the incident light, separate the R, G, and B light, and enter each corresponding cell PC. All you have to do is let it happen.

As explained above, according to the solid-state imaging device according to the present invention, by using a material for the gate electrode that is in direct contact with the gate region and having a different forbidden band width than that of the gate region, the gate region and the gate electrode A depletion layer can be provided at the boundary between the gate region and the gate electrode by forming a heterojunction at the junction with the gate electrode and by discontinuing the energy band at the heterojunction. By forming a capacitor using this depletion layer and directly connecting the read address circuit to this capacitor, the structure and manufacturing process of the solid-state imaging device can be simplified.

[Brief explanation of the drawing]

FIG. 1A is a partial plan view showing an embodiment of the solid-state imaging device according to the present invention, FIG. 1B is a schematic end view seen from the arrow in FIG. 1A, and FIG. FIG. 3 is a circuit diagram showing the configuration of an equivalent electric circuit; FIG. 4A is a partial plan view showing another embodiment of the solid-state imaging device according to the present invention; FIG. 4B is a schematic end view seen from the arrow in FIG. 4A, and FIGS. 5A to 5L are explanatory diagrams showing an example of the manufacturing process. Explanation of symbols of main parts, 12... Channel region, 14... Gate region, 16... Source region, 24
...gate electrode, 70...electrode layer, PC...cell.

Claims (1)

[Claims] 1 A plurality of cells configured by SIT are arranged, and a capacitor is provided in the gate region in order to accumulate carriers corresponding to the amount of light incident on each cell in the gate region adjacent to the channel region. in a solid-state imaging device in which a read address circuit is directly connected to the capacitor, the capacitor has a gate electrode that is in direct contact with the gate region and is made of a material that has a different forbidden band width than that of the gate region. A solid-state imaging device characterized in that a depletion layer is formed at a boundary between the gate electrode and the gate region by a heterojunction between the gate electrode and the gate region. 2. In the device according to claim 1, the gate region is formed of silicon crystal, and the gate electrode is formed of a material containing tin oxide (SnO ₂ ). Characteristic solid-state imaging device. 3. The device according to claim 2, wherein the gate electrode has a first layer in contact with the gate region and a second layer in contact with the first layer, and The layer includes tin oxide formed at a relatively high temperature with respect to the gate region, and the second layer is formed at a relatively low temperature with respect to the first layer and includes a conductive element. Characteristic solid-state imaging device.