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JPH0473569B2 - - Google Patents
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JPH0473569B2 - - Google Patents

Info

Publication number
JPH0473569B2
JPH0473569B2 JP57228948A JP22894882A JPH0473569B2 JP H0473569 B2 JPH0473569 B2 JP H0473569B2 JP 57228948 A JP57228948 A JP 57228948A JP 22894882 A JP22894882 A JP 22894882A JP H0473569 B2 JPH0473569 B2 JP H0473569B2
Authority
JP
Japan
Prior art keywords
electrode
pixel drive
liquid crystal
pixel
drive electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57228948A
Other languages
Japanese (ja)
Other versions
JPS59119322A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP57228948A priority Critical patent/JPS59119322A/en
Publication of JPS59119322A publication Critical patent/JPS59119322A/en
Publication of JPH0473569B2 publication Critical patent/JPH0473569B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects

Landscapes

  • Physics & Mathematics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Description

【発明の詳細な説明】 本発明は、アクテイブマトリツクス液晶表示装
置に関し、製造工程において発生した画素欠陥の
修正を目的としたものである。以下図面を参照し
て説明する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix liquid crystal display device, and is aimed at correcting pixel defects that occur during the manufacturing process. This will be explained below with reference to the drawings.

液晶表示装置は、小型・軽量・低省費電力・受
光表示デバイスといつた特長を活し、時計・電卓
などに広く使用されており、将来有望な表示装置
のひとつである。この内基板内に信号線と画素駆
動電極とをオン・オフするスイツチング素子を形
成したアクテイブマトリツクス型のものは、画素
駆動電圧の保持ができれば液晶の駆動デユーテイ
比100%が可能であり、大画面・微細画素による
高精細度に適している。しかしながら、画素サイ
ズが小さくなるにつれ、画素駆動電圧を保持する
ための画素駆動電極と対向電極との間に液晶を挾
む保持容量が少さくなり、別に容量を追加しない
と電圧が保てなくなる。そのためアクテイブマト
リツク基板内に保持容量を形成する方法がとられ
るが、この場合には、画素駆動電極の一部を用い
る場合には、アクテイブマトリツクス基板を光が
通過するようなTN型液晶を用いた場合などにお
いては、光の透過率が低下し、表示のコントラス
ト落ち、表示品質が悪くなるといつた問題があ
る。そこで画素駆動電極とそれに隣接するワイミ
ング線との間にコンデンサを形成する方法がとら
れる。この方法は非選択レベルにあるタイミング
線との間に容量を作るもので、現在選択レベルに
あるタイミング線のひとつ前のタイミング線と画
素駆動電極によつて形成される。
Liquid crystal display devices are widely used in watches, calculators, etc., and are one of the most promising display devices in the future, due to their features such as small size, light weight, low power consumption, and light-receiving display devices. Among these, the active matrix type, in which switching elements that turn on and off the signal lines and pixel drive electrodes are formed in the substrate, can achieve a liquid crystal drive duty ratio of 100% if the pixel drive voltage can be maintained, and can achieve a large liquid crystal drive duty ratio of 100%. Suitable for high-definition screens and fine pixels. However, as the pixel size becomes smaller, the storage capacitance that sandwiches the liquid crystal between the pixel drive electrode and the counter electrode for holding the pixel drive voltage decreases, and the voltage cannot be maintained unless additional capacitance is added. For this reason, a method is used to form a storage capacitor in the active matrix substrate. In this case, if a part of the pixel drive electrode is used, a TN type liquid crystal that allows light to pass through the active matrix substrate is used. When used, there are problems such as a decrease in light transmittance, a decrease in display contrast, and a deterioration in display quality. Therefore, a method is adopted in which a capacitor is formed between the pixel drive electrode and the wiring line adjacent thereto. This method creates a capacitance between a timing line at a non-selected level and a timing line immediately before the timing line currently at a selected level and the pixel drive electrode.

第1図は、従来のアクテイブマトリツクス基板
の構成を示すものであり、現在選択レベルにある
タイミング線2によりスイツチング素子である
MOSトランジスタ8をオン状態としデータ線1
の信号を画素駆動電極6に充電する。このとき第
2図の回路図に示すようにデータ線1の信号を
MOSトランジスタ8を通じて、画素駆動電極と
液晶セルを構成するガラス基板上の電極によつて
形成される容量4と画素駆動電極と非選択レベル
にあるタイミング線3との間に形成した容量5に
各々充電する。これによつて画素サイズが小さく
なることによる容量4の低下を容量5で補なうこ
とができるが、一方で画素駆動電極と非選択レベ
ルのタイミング線とを重ねた部分3における、上
記画素駆動電極と非選択レベルのタイミング線に
挾まれる絶縁膜におけるピンホールが製造工程に
おいて発生した場合画素駆動電極はタイミング線
の非選択レベルに保たれてしまいデータ線からの
信号は消去されてしまう。このようなピンホール
の発生は、形成される電極7の面積が表示装置全
体ではかなりの大きさになるため確率は高い。こ
の場合表示装置としては、その画素が点灯したま
ま、あるいは全く点灯しないといつた画素欠陥と
なるため、著しい品質の低下をまねく。
Figure 1 shows the configuration of a conventional active matrix board, in which the timing line 2, which is currently at the selection level, indicates the switching element.
MOS transistor 8 is turned on and data line 1
The pixel drive electrode 6 is charged with the signal. At this time, as shown in the circuit diagram of Figure 2, the signal on data line 1 is
Through the MOS transistor 8, the capacitor 4 formed by the pixel drive electrode and the electrode on the glass substrate constituting the liquid crystal cell and the capacitor 5 formed between the pixel drive electrode and the timing line 3 at the non-select level are respectively connected. Charge. As a result, the decrease in capacitance 4 due to the reduction in pixel size can be compensated for by capacitance 5, but on the other hand, the pixel drive in the portion 3 where the pixel drive electrode and the non-selection level timing line overlap, If a pinhole occurs in the insulating film sandwiched between the electrode and the timing line at the non-select level during the manufacturing process, the pixel drive electrode will be kept at the non-select level of the timing line and the signal from the data line will be erased. The probability of occurrence of such pinholes is high because the area of the formed electrode 7 is quite large in the entire display device. In this case, for the display device, the pixel remains lit or does not light at all, resulting in a pixel defect, resulting in a significant deterioration in quality.

そこで本発明においては、このような欠陥の発
生に対して後から修正の方法を与えるもので、第
3図に示すように画素駆動電極6と容量5の電極
7を接続部9以外でスリツト10により分離して
おくパターンとすることである。
Therefore, in the present invention, a method for later correcting such defects is provided, and as shown in FIG. This is to create a pattern that is separated by

このパターンを用いて実際に電極7においてピ
ンホールによる欠陥が発生した場合、接続部9を
レーザなどにより切断し画素駆動電極6と完全に
分離してしまうことにより画素駆動電極がタイミ
ング線の非選択レベルに保たれてしまうこともな
く、かつ画素としての電圧保持容量が容量4だけ
になつてしまうが、点灯か非点灯かといつた極端
な欠陥状態ではなく、データ線からの信号によつ
て一応コントロールされる状態となり、かなり改
善される。
If a defect due to a pinhole actually occurs in the electrode 7 using this pattern, the connecting portion 9 is cut by a laser or the like and completely separated from the pixel drive electrode 6, so that the pixel drive electrode does not select the timing line. It is not maintained at the same level, and the voltage holding capacity as a pixel becomes only capacitor 4, but it is not an extreme defect state such as whether it is lit or not lit, but it is caused by the signal from the data line. It will be under control and will improve considerably.

以上の如く、本発明は液晶表示容量を、接続部
を介して該画素電極と電気的に接続された電極と
前段の該タイミング線とで形成し、該接続部の幅
を、該画素電極の幅よりも狭くしたから、表示容
量を構成する絶縁膜中のピンホールによるリーク
不良があつた場合、表示容量と画素駆動電極との
接続部を切断することにより、表示不良をなくす
ことができ、歩留りの向上と、表示品質の向上を
図ることができる。
As described above, the present invention forms a liquid crystal display capacitor by an electrode electrically connected to the pixel electrode via a connection part and the timing line in the preceding stage, and the width of the connection part is set to the width of the pixel electrode. Because it is narrower than the width, if a leakage defect occurs due to a pinhole in the insulating film that makes up the display capacitor, the display defect can be eliminated by cutting the connection between the display capacitor and the pixel drive electrode. It is possible to improve yield and display quality.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のアクテイブマトリツクス基板の
構成図。第2図は第1図の電気回路図。第3図は
本発明による画素駆動電極と容量電極の構成図。 1……データ線、2……現在選択レベルにある
タイミング線、3……現在非選択レベルにあるタ
イミング線、4……画素駆動電極と対向電極に液
晶を挾んで作られる容量、5……画素駆動電極と
非選択レベルにあるタイミング線3との間に作ら
れる容量、6……画素駆動電極、7……容量5を
構成する画素駆動電極6と接続された電極、8…
…MOSトランジスタ、9……画素駆動電極と容
量電極を分割するスリツト、10……画素駆動電
極と容量電極の接続部。
FIG. 1 is a configuration diagram of a conventional active matrix board. FIG. 2 is an electrical circuit diagram of FIG. 1. FIG. 3 is a configuration diagram of a pixel drive electrode and a capacitor electrode according to the present invention. 1... Data line, 2... Timing line currently at the selected level, 3... Timing line currently at the non-selected level, 4... Capacitance created by sandwiching the liquid crystal between the pixel drive electrode and the counter electrode, 5... Capacitance created between the pixel drive electrode and the timing line 3 at the non-select level, 6... Pixel drive electrode, 7... Electrode connected to the pixel drive electrode 6 constituting the capacitor 5, 8...
...MOS transistor, 9...Slit dividing the pixel drive electrode and capacitor electrode, 10...Connection portion between the pixel drive electrode and capacitor electrode.

Claims (1)

【特許請求の範囲】 1 一対の基板間に挟持されてなる液晶層と、該
1対の基板の一方の基板上にマトリクス状に配置
されてなる画素電極と、該画素電極にデータ信号
を供給してなるデータ線と、該画素電極にタイミ
ング信号を供給してなるタイミング線を有してな
る電気光学表示装置において、 液晶表示容量は、接続部を介して該画素電極と
電気的に接続された電極と前段の該タイミング線
とで形成され、 該接続部の幅は、該画素電極の幅よりも狭いこ
とを特徴とする液晶表示装置。
[Claims] 1. A liquid crystal layer sandwiched between a pair of substrates, pixel electrodes arranged in a matrix on one of the pair of substrates, and a data signal supplied to the pixel electrodes. In an electro-optical display device having a data line formed by a data line and a timing line formed by supplying a timing signal to the pixel electrode, the liquid crystal display capacitor is electrically connected to the pixel electrode via a connection part. A liquid crystal display device, characterized in that the width of the connection portion is narrower than the width of the pixel electrode.
JP57228948A 1982-12-27 1982-12-27 liquid crystal display device Granted JPS59119322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57228948A JPS59119322A (en) 1982-12-27 1982-12-27 liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57228948A JPS59119322A (en) 1982-12-27 1982-12-27 liquid crystal display device

Publications (2)

Publication Number Publication Date
JPS59119322A JPS59119322A (en) 1984-07-10
JPH0473569B2 true JPH0473569B2 (en) 1992-11-24

Family

ID=16884359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57228948A Granted JPS59119322A (en) 1982-12-27 1982-12-27 liquid crystal display device

Country Status (1)

Country Link
JP (1) JPS59119322A (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60230118A (en) * 1984-04-27 1985-11-15 Seiko Instr & Electronics Ltd Storage capacity incorporated type liquid crystal display device
JP2620240B2 (en) 1987-06-10 1997-06-11 株式会社日立製作所 Liquid crystal display
JPH01219824A (en) * 1988-02-29 1989-09-01 Seikosha Co Ltd Amorphous silicon thin film transistor array substrate
JPH0786618B2 (en) * 1988-12-29 1995-09-20 シャープ株式会社 Active matrix display
JPH0298333U (en) * 1989-01-23 1990-08-06
JPH0786619B2 (en) * 1989-04-26 1995-09-20 シャープ株式会社 Active matrix display
JP2818197B2 (en) * 1989-05-23 1998-10-30 株式会社東芝 Active matrix type liquid crystal display
KR940005124B1 (en) * 1989-10-04 1994-06-11 호시덴 가부시기가이샤 LCD
US5392143A (en) * 1989-11-30 1995-02-21 Kabushiki Kaisha Toshiba Liquid crystal display having drain and pixel electrodes linkable to a wiring line having a potential
US5151806A (en) * 1990-04-27 1992-09-29 Mitsubishi Denki Kabushiki Kaisha Liquid crystal display apparatus having a series combination of the storage capacitors
FR2662290B1 (en) * 1990-05-15 1992-07-24 France Telecom METHOD FOR PRODUCING A DISPLAY SCREEN WITH ACTIVE MATRIX AND STORAGE CAPACITORS AND SCREEN OBTAINED BY THIS PROCESS.
US5402254B1 (en) * 1990-10-17 1998-09-22 Hitachi Ltd Liquid crystal display device with tfts in which pixel electrodes are formed in the same plane as the gate electrodes with anodized oxide films before the deposition of silicon
US5287206A (en) * 1990-11-30 1994-02-15 Sharp Kabushiki Kaisha Active matrix display device
JP2650780B2 (en) * 1990-11-30 1997-09-03 シャープ株式会社 Active matrix substrate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552091A (en) * 1978-10-13 1980-04-16 Suwa Seikosha Kk Correcting substrate for liquid crystal panel
JPS5660480A (en) * 1979-10-23 1981-05-25 Canon Kk Display unit
JPS5677887A (en) * 1979-11-30 1981-06-26 Citizen Watch Co Ltd Liquid crystal display unit

Also Published As

Publication number Publication date
JPS59119322A (en) 1984-07-10

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