JPH0473818B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a drop-and-relay method for dropping and adding arbitrary channel signals in the middle of a PCM multiplex transmission path.

Summary of the Invention The present invention provides a method for transmitting data received during a PCM multiplex transmission path.
The PCM multiplexed signal is temporarily stored in a memory circuit, and a part of the signal read out from the memory circuit is branched according to the frame phase output by a frame phase generation circuit independent of the received signal, and then inserted into the time slot of the vacant channel. This is a method of branching and relaying by inserting another channel signal and sending it to a multiplex transmission path.

Conventional technology Conventionally, in order to drop or add arbitrary channel signals from a PCM multiplex transmission line,
The configuration shown in the figure is adopted. The configuration shown in Figure 2 consists of two PCM multiplex converters 1 connected in cascade.
Once the multiplexed signal is separated into multiple channel signals,
The passing channels 2 are connected in cascade as they are, and the signals are multiplexed again together with the branching and adding channels 3 and sent out to the transmission path. In this case, since the multiplexed signal is once separated into channel signals and then cascaded at the channel level, the apparatus becomes complex and large-scale, and the relay quality deteriorates due to the cascading of channels.

The configuration of FIG. 3 is the input/output interface circuit 7.
A branch circuit 5 and an insertion circuit 6 are connected in cascade between them, and any branch channel signal is branched from the branch circuit 5 to the channel input/output circuit 8, and the passing channel signal is passed through as a multiplexed signal, and the insertion channel signal is An insertion circuit 6 inserts the signal into the corresponding time slot in the multiplexed signal. In this case, the circuit scale can be small, and no deterioration occurs due to relaying. However, since the branching and repeating equipment establishes the frame phase from the received signal and operates the branching and adding circuits, if a failure occurs in the multiplex transmission section on the input side, synchronization will occur and the received frame phase will be disrupted. As a result, the operation of the branching and adding circuits is disrupted, and the branching line also becomes a failure. Furthermore, there is a drawback that failures may spread to the multiplex transmission section on the output side one after another. If the frame phase is completely out of sync, the frame phase circuit built into the drop/add circuit will begin to run on its own, so subsequent repeaters and branch/relay devices will gradually recover synchronization, but it will take some time before recovery. will take a considerable amount of time. Furthermore, when the fault on the input side is recovered, it will start operating again using the frame phase of the received signal, but since it is different from the frame phase during free running, the subsequent relay devices will lose synchronization again and start a new one. Synchronous pull-in will be performed on the frame phase. Therefore, when a fault occurs in one multiplex section and when it recovers, synchronization will occur twice in the subsequent multiplex transmission section.

Problems to be Solved by the Invention The present invention solves the above-mentioned conventional drawbacks and provides a branching and repeating method that prevents a failure occurring in the input side multiplex transmission line section from spreading to the output side multiplex transmission line section. It is something to do.

Method for Solving Problems The branching and relaying method of the present invention writes a PCM multiplexed signal into a storage circuit in accordance with the frame phase of a received signal, and reads it from the storage circuit in accordance with a frame phase independent of the received signal. An arbitrary channel signal is separated from the signal and branched, and another channel signal is inserted into the time slot of the empty channel and sent out. Even if a failure occurs on the input side multiplex transmission line, multiplex signals with independent frame phases can be sent to the output side multiplex transmission line, so the failure on the input side will not spread to the output side.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. That is, the output of the receiving circuit 9 is supplied to the memory circuit 11 and the first frame phase generating circuit 10, and the first frame phase generating circuit 10 establishes synchronization with the output signal of the receiving circuit 9, and the first frame phase generating circuit 10 establishes synchronization with the output signal of the receiving circuit 9. Generates a frame phase pulse synchronized with frame phase. The storage circuit 11 starts writing the received signal from address 0 using the frame phase pulse supplied from the first frame phase generation circuit 10, and sequentially writes one frame worth of signals. On the other hand, the second frame phase generation circuit 12 has a built-in oscillator independent of the received signal, and the oscillator causes the storage circuit 1
1 determines the frame phase of the read signal. The memory circuit 11 sends signals sequentially read out from address 0 in accordance with the frame phase supplied from the second frame phase generation circuit 12 to the branch/add circuit 13 . The add/drop circuit 13 is the second frame phase generating circuit 12
According to the frame phase input from the memory circuit 11, an arbitrary channel signal is separated and extracted from the output signal of the storage circuit 11, and branched and outputted to the channel input/output circuit 8, and the channel input/output circuit 8 is inserted into the time slot of the empty channel. Another channel signal inputted from the channel is inserted and inputted to the transmitting circuit 14. The signal is converted by the transmission circuit 14 into a signal waveform (for example, a bipolar signal) suitable for transmission over the transmission path, and is sent out onto the transmission path.

In this embodiment, reading from the storage circuit 11 and branch/insertion of the branch/insertion circuit 13 are performed by the second
Since the first frame phase generating circuit 10 is operated by a unique frame phase pulse generated by the first frame phase generating circuit 12, a failure occurs in the multiplex transmission section on the input side, causing the first frame phase generating circuit 10 to become out of synchronization. However, a unique frame synchronization signal is sent to the multiplex transmission path on the output side. That is, there is an effect that a failure on the input side does not spread to the multiplex transmission section on the output side.

In addition, when the fault is recovered, when the first frame phase generation circuit 10 establishes synchronization with the received signal, each channel signal is sequentially written from address 0 of the storage circuit 11, thereby eliminating the fault. Of course, the channels that were affected will also recover. In this case, the synchronization of subsequent multiplexed sections remains unchanged, so
There is no need to resynchronize as before.

Effects of the Invention As described above, in the present invention, an input signal is written into a storage circuit according to the frame phase of a received signal, and reading from the storage circuit is performed using an oscillator that is independent of the received frame phase. Since reading is performed according to the frame phase, an arbitrary channel signal is branched from the readout signal, and an insertion channel signal is placed on an empty channel and sent out, a failure in the multiplex section on the input side can cause the output side to fail. This has the effect of preventing the synchronization of multiplexed sections from being disrupted and the failure from spreading.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIGS. 2 and 3 are block diagrams each showing a configuration example of a conventional branching and relaying method. In the figure, 1: PCM multiplex conversion device, 2: relay channel, 3: branch channel, 5: branch circuit, 6: insertion circuit, 7: input/output interface circuit, 8: channel input/output circuit, 9: receiving circuit ,1
0: first frame phase generation circuit, 11: memory circuit, 12: second frame phase generation circuit, 13:
Branch/add circuit, 14: Transmission circuit.

Claims (1)

[Claims] 1 Write the PCM multiplexed signal into a storage circuit in accordance with the frame phase of the received signal, separate and branch any channel signal from the signal read out from the storage circuit according to the frame phase independent of the received signal, and create an empty channel. A branching and relaying method characterized by inserting and transmitting another channel signal into the time slot of a channel and transmitting an independent frame synchronization signal to the multiplex transmission path on the output side.