JPH0474732B2 - - Google Patents
Info
- Publication number
- JPH0474732B2 JPH0474732B2 JP10863783A JP10863783A JPH0474732B2 JP H0474732 B2 JPH0474732 B2 JP H0474732B2 JP 10863783 A JP10863783 A JP 10863783A JP 10863783 A JP10863783 A JP 10863783A JP H0474732 B2 JPH0474732 B2 JP H0474732B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- transistor
- terminal
- emitter
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
- G05F1/573—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
- G05F1/5735—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector with foldback current limiting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Emergency Protection Circuit Devices (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は定電圧電源回路における電流制限保護
回路に係り、特に過大電流の制限および負過端の
短絡を検出して通常の制限電流より数分の１に押
へ、制御トランジスタを保護することができる電
流制限保護回路に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a current limit protection circuit in a constant voltage power supply circuit, and in particular, the present invention relates to a current limit protection circuit in a constant voltage power supply circuit, and in particular detects the limit of excessive current and short circuit at the negative overload end, and reduces the current limit by several minutes from the normal limit current. The present invention relates to a current limit protection circuit that can protect a control transistor.
従来のこの種の保護回路の一例を第１図に示し
説明すると、図において、１は電源が印加される
電源入力端子、３は第１の制御用PNPトランジ
スタ（以下、第１の制御トランジスタと呼称す
る）で、そのエミツタは電源入力端子１に接続さ
れ、コレクタは定電圧出力端子１９に接続され、
ベースは抵抗２を介してエミツタに接続されてい
る。６，７はベースおよびエミツタをそれぞれ共
通接続した第３，第４のPNPトランジスタで、
そのエミツタは第１の制御トランジスタ３のベー
スと抵抗２の接続点に接続され、トランジスタ６
のベースとコレクタは共通接続されてカレントミ
ラー回路を構成としている。８，９はエミツタを
共通接続し、その接続点をエミツタ抵抗１０を介
して接地したNPNトランジスタ（以下、誤差増
幅用トランジスタと呼称する）で、これらは誤差
増幅回路１１を構成している。そして、この誤差
増幅用トランジスタ８の、コレクタはトランジス
タ６のコレクタに接続され、ベースは基準電圧源
５に接続され、また誤差増幅用トランジスタ９
の、コレクタはトランジスタ７のコレクタに接続
され、ベースは出力端子１９と接地１８間に直列
接続された第１の抵抗１６と第２の抵抗１７の接
続点である出力電圧調整端子２０に接続されてい
る。
An example of a conventional protection circuit of this kind is shown in FIG. 1 and explained. In the figure, 1 is a power input terminal to which power is applied, and 3 is a first control PNP transistor (hereinafter referred to as the first control transistor). ), its emitter is connected to the power input terminal 1, its collector is connected to the constant voltage output terminal 19,
The base is connected to the emitter via resistor 2. 6 and 7 are third and fourth PNP transistors whose bases and emitters are commonly connected, respectively.
Its emitter is connected to the connection point between the base of the first control transistor 3 and the resistor 2, and the transistor 6
The base and collector of are commonly connected to form a current mirror circuit. 8 and 9 are NPN transistors (hereinafter referred to as error amplification transistors) whose emitters are commonly connected and whose connection point is grounded via an emitter resistor 10, and these constitute an error amplification circuit 11. The collector of this error amplification transistor 8 is connected to the collector of the transistor 6, the base is connected to the reference voltage source 5, and the error amplification transistor 9 is connected to the collector of the transistor 6.
The collector is connected to the collector of the transistor 7, and the base is connected to the output voltage adjustment terminal 20, which is the connection point between the first resistor 16 and the second resistor 17, which are connected in series between the output terminal 19 and the ground 18. ing.
１２，１３はダーリントン接続された第２の制
御用NPNトランジスタ（以下、第２の制御トラ
ンジスタと呼称する）で、その共通接続されたコ
レクタは第１の制御トランジスタ３のベースと抵
抗２の接続点に接続され、ベースはトランジスタ
７のコレクタに接続され、エミツタは電流検出抵
抗１４を介して接地されている。１５は電流制限
検出用のNPNトランジスタ（以下、電流制限検
出トランジスタと呼称する）で、そのコレクタは
第２の制御トランジスタ１２のベースに接続さ
れ、ベースおよびエミツタは上記電流検出抵抗１
４の両端に接続されている。２１は負荷端である
定電圧出力端子１９と接地間に挿入された負荷で
ある。 12 and 13 are Darlington-connected second control NPN transistors (hereinafter referred to as second control transistors), whose commonly connected collectors are connected to the base of the first control transistor 3 and the resistor 2. The base is connected to the collector of the transistor 7, and the emitter is grounded via the current detection resistor 14. Reference numeral 15 denotes an NPN transistor for current limit detection (hereinafter referred to as a current limit detection transistor), whose collector is connected to the base of the second control transistor 12, and whose base and emitter are connected to the current detection resistor 1.
Connected to both ends of 4. 21 is a load inserted between the constant voltage output terminal 19, which is a load end, and the ground.
このように構成された回路の動作は一般によく
知られているので、その詳細な説明は省略する
が、電流制限検出トランジスタ１５のベース・エ
ミツタ間に電流検出抵抗１４を接続することによ
り、この電流検出抵抗１４に流れる電流によつて
発生した電圧で電流制限検出トランジスタ１５を
オンさせ、第２の制御トランジスタ１２，１３へ
流れる電流を押え、ある設定値以上の電流が流れ
ないように電流制限保護をかけている。 Since the operation of the circuit configured in this way is generally well known, a detailed explanation thereof will be omitted, but by connecting the current detection resistor 14 between the base and emitter of the current limit detection transistor 15, this current The voltage generated by the current flowing through the detection resistor 14 turns on the current limit detection transistor 15, suppresses the current flowing to the second control transistors 12 and 13, and provides current limit protection so that the current does not exceed a certain set value. is being applied.
しかしながら、このような電流制限保護回路に
おいては、電流制限は可能であるが、負荷端（出
力端子１９と接地１８間）短絡のような異常な状
態でも同じ電流制限レベルとなり、第１の制御ト
ランジスタ３のコレクタには、その制限の設定値
の電流の電流増幅率hFE倍の電流が流れることに
なり、非常に大きな電力が印加され、破壊すると
いう欠点があつた。 However, in such a current limit protection circuit, although current limit is possible, even in an abnormal state such as a short circuit at the load end (between output terminal 19 and ground 18), the current limit level remains the same, and the first control transistor In the collector of No. 3, a current that is equal to the current amplification factor h FE times the current of the limit setting value flows, and a very large amount of power is applied to the collector, resulting in damage.
本発明は以上の点に鑑み、このような問題を解
決すると共にかかる欠点を除去すべくなされたも
ので、その目的は部品点数を増加することなく、
電流制限を負荷端短絡という異常な状態に対して
通常の電流制限値の数分の１のレベルに下げ、制
御トランジスタを保護することができる電流制限
保護回路を提供することにある。
In view of the above points, the present invention was made to solve such problems and eliminate such drawbacks, and its purpose is to
It is an object of the present invention to provide a current limit protection circuit capable of protecting a control transistor by lowering the current limit to a level that is a fraction of the normal current limit value in response to an abnormal condition such as a short circuit at a load end.
このような目的を達成するため、本発明は電流
制限検出トランジスタをPNP型として、そのベ
ースを出力電圧調整端子に接続し、コレクタを誤
差増幅回路の誤差増幅用トランジスタのエミツタ
抵抗に接続し、エミツタを第２の制御トランジス
タのエミツタと電流検出抵抗の接続点に接続する
ようにしたものである。 In order to achieve such an object, the present invention uses a PNP type current limit detection transistor, whose base is connected to the output voltage adjustment terminal, and whose collector is connected to the emitter resistor of the error amplification transistor of the error amplification circuit. is connected to the connection point between the emitter of the second control transistor and the current detection resistor.
以下、図面に基づき本発明の実施例を詳細に説
明する。
Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第２図は本発明による電流制限保護回路の一実
施例を示す回路図である。 FIG. 2 is a circuit diagram showing one embodiment of the current limit protection circuit according to the present invention.
この第２図において第１図と同一符号のものは
相当部分を示し、２２は電流制限検出用PNPト
ランジスタ（以下、電流制限検出トランジスタと
呼称する）で、そのベースは出力電圧調整端子２
０に接続され、コレクタは誤差増幅回路１１の誤
差増幅用トランジスタ８，９のエミツタ抵抗１０
に接続され、エミツタは第２の制御トランジスタ
１３のエミツタと接地間に接続された電流検出抵
抗１４の接続点に接続されている。 In FIG. 2, the same reference numerals as in FIG.
0, and the collector is connected to the emitter resistor 10 of the error amplification transistors 8 and 9 of the error amplification circuit 11.
The emitter of the second control transistor 13 is connected to the connection point of the current detection resistor 14, which is connected between the emitter of the second control transistor 13 and ground.
つぎにこの第２図に示す実施例の動作を説明す
る。 Next, the operation of the embodiment shown in FIG. 2 will be explained.
いま、基準電圧源５の電圧Vrを1.2V，第２の
制御トランジスタ１３の電流制限値ILnaxを
100mAとすると、電流検出抵抗１４の値は、電
流制限検出トランジスタ２２がオンするに必要な
ベース・エミツタ電圧がエミツタに発生すればよ
いので、誤差増幅用トランジスタ８，９のベー
ス・エミツタ電圧が等しいとし、電流制限検出ト
ランジスタ２２のオンするベース・エミツタ電圧
VBEを0.5Vとすると、
Vr＋VBE／ILnax＝1.2V＋500mV／100mA＝17Ω
となる。 Now, the voltage Vr of the reference voltage source 5 is 1.2V, and the current limit value I Lnax of the second control transistor 13 is
Assuming 100 mA, the value of the current detection resistor 14 is such that the base-emitter voltage required to turn on the current limit detection transistor 22 is generated at the emitter, so the base-emitter voltages of the error amplification transistors 8 and 9 are equal. The base-emitter voltage at which the current limit detection transistor 22 turns on is
If V BE is 0.5V, Vr + V BE /I Lnax = 1.2V + 500mV/100mA = 17Ω.
この電流検出抵抗１４の値17Ωにより、過大電
流が防止され、100mAで電流制限検出トランジ
スタ２２がオンし、コレクタ電流が誤差増幅用ト
ランジスタ８，９のエミツタ抵抗１０に流れ、こ
の誤差増幅用トランジスタ８，９のエミツタ電位
を持ち上げ、同トランジスタのコレクタ電流を絞
り、第２制御トランジスタ１２，１３へ流れ込む
電流を押え、同トランジスタに流れる電流を
100mAで保持する。 The value of the current detection resistor 14 of 17Ω prevents excessive current, and the current limit detection transistor 22 is turned on at 100 mA, and the collector current flows to the emitter resistor 10 of the error amplification transistors 8 and 9. .
Hold at 100mA.
また、負荷端が短絡された場合には、出力電圧
調整端子２０がほぼ接地電位（アース電位）に下
がるので、電流制限検出トランジスタ２２のベー
ス電位も下がることになり、この電流制限検出ト
ランジスタ２２はオンとなり、そのコレクタ電流
が誤差増幅用トランジスタ８，９のエミツタ抵抗
１０に流れ、この誤差増幅用トランジスタ８のエ
ミツタ電位を上げ電流を絞つていく。このとき、
電流制限検出トランジスタ２２のコレクタ・エミ
ツタ間電圧VCEが動作に必要な電圧としてVCE＝
0.15Vとし、誤差増幅用トランジスタ８のベー
ス・エミツタ電圧を電流が絞られたときVBE(8)＝
0.6Vとすると、
｛Vr−VBE(8)＋VCE｝／17Ω
＝1.2V−0.6V＋0.15V／17Ω＝44mA
と約1/2に負荷端短絡時に電流制限レベルを下げ
ることができる。 Furthermore, when the load end is short-circuited, the output voltage adjustment terminal 20 drops to approximately the ground potential (earth potential), so the base potential of the current limit detection transistor 22 also drops, and this current limit detection transistor 22 It turns on, and its collector current flows to the emitter resistor 10 of the error amplification transistors 8 and 9, raising the emitter potential of the error amplification transistor 8 and reducing the current. At this time,
Assuming that the collector-emitter voltage V CE of the current limit detection transistor 22 is the voltage required for operation, V CE =
When the current is limited to 0.15V and the base-emitter voltage of the error amplification transistor 8 is V BE (8)=
If it is 0.6V, {Vr-V BE (8)+V CE }/17Ω = 1.2V-0.6V+0.15V/17Ω = 44mA, and the current limit level can be lowered to about 1/2 when the load end is short-circuited.
このように、通常の過大電流制限値の100mA
の1/2程度に押えられるので、制御トランジスタ
３のコレクタ電流も第１図に示す従来の方式のも
のに比して押えられるという利点がある。 In this way, the normal overcurrent limit value of 100mA
This has the advantage that the collector current of the control transistor 3 can also be suppressed compared to the conventional system shown in FIG. 1.
なお、電流制限検出トランジスタ２２のエミツ
タを第２の制御トランジスタ１３のベースへ接続
することにより、さらに、電流制限レベルを下げ
ることもできる。 Note that by connecting the emitter of the current limit detection transistor 22 to the base of the second control transistor 13, the current limit level can be further lowered.
また、上記実施例においては、電流制限検出ト
ランジスタ２２のコレクタを誤差増幅用トランジ
スタ８，９のエミツタに接続した場合を示した
が、本発明はこれに限定されるものではなく、こ
の誤差増幅用トランジスタ８，９のエミツタに接
続したエミツタ抵抗１０を分割し、その分割点へ
電流制限検出トランジスタ２２のコレクタを接続
しとも同等の利点が得られる。 Further, in the above embodiment, the collector of the current limit detection transistor 22 is connected to the emitters of the error amplification transistors 8 and 9, but the present invention is not limited to this. The same advantage can be obtained by dividing the emitter resistor 10 connected to the emitters of the transistors 8 and 9 and connecting the collector of the current limit detection transistor 22 to the dividing point.
以上説明したように、本発明によれば、複雑な
手段を用いることなく、電流制限検出トランジス
タのベースを出力電圧調整端子に、コレクタを誤
差増幅用トランジスタのエミツタまたはエミツタ
抵抗に、エミツタを電流検出抵抗または第２の制
御用トランンジスタのベースへそれぞれ接続する
という接続変更のみで部品点数を増やさない簡単
な回路構成によつて、電流制限を負荷端短絡とい
う異常な状態に対して、通常の電流制限値の数分
の１のレベルに下げることができ、これに伴つて
制御トランジスタを保護することができるので、
実用上の効果は極めて大である。また、構成の簡
素化にともなつて電流制限保護回路を安価に提供
することができるという点において極めて有効で
ある。
As explained above, according to the present invention, without using complicated means, the base of the current limit detection transistor is used as the output voltage adjustment terminal, the collector is used as the emitter of the error amplification transistor or the emitter resistor, and the emitter is used as the current detection transistor. By using a simple circuit configuration that does not increase the number of components by simply changing the connection by connecting each to the base of the resistor or the second control transistor, the current limit can be set to the normal current even in the abnormal condition of a short circuit at the load end. Since it is possible to lower the level to a fraction of the limit value and protect the control transistor accordingly,
The practical effects are extremely large. Further, it is extremely effective in that the current limit protection circuit can be provided at low cost due to the simplified configuration.
第１図は従来の電流制限保護回路の一例を示す
回路図、第２図は本発明による電流制限保護回路
の一実施例を示す回路図である。
１……電源入力端子、３……第１の制御用
PNPトランジスタ、５……基準電圧源、６……
第３のトランジスタ、７……第４のトランジス
タ、８，９……誤差増幅用トランジスタ、１０…
…エミツタ抵抗、１１……誤差増幅回路、１２，
１３……第２の制御用NPNトランジスタ、１４
……電流検出抵抗、１６……第１の抵抗、１７…
…第２の抵抗、１８……接地、１９……定電圧出
力端子、２０……出力電圧調整端子、２１……負
荷、２２……電流制限検出用PNPトランジスタ。
FIG. 1 is a circuit diagram showing an example of a conventional current limit protection circuit, and FIG. 2 is a circuit diagram showing an embodiment of the current limit protection circuit according to the present invention. 1...Power input terminal, 3...For first control
PNP transistor, 5... Reference voltage source, 6...
Third transistor, 7... Fourth transistor, 8, 9... Error amplification transistor, 10...
...Emitter resistance, 11...Error amplification circuit, 12,
13...Second control NPN transistor, 14
...Current detection resistor, 16...First resistor, 17...
... Second resistor, 18 ... Ground, 19 ... Constant voltage output terminal, 20 ... Output voltage adjustment terminal, 21 ... Load, 22 ... PNP transistor for current limit detection.
Claims (1)
ツタ・コレクタを直列に接続した第１の制御トラ
ンジスタと、第３のトランジスタのベースとコレ
クタを第４のトラジスタのベースに接続したカレ
ントミラー回路と、一方の入力を基準電圧源に、
他方の入力を定電圧出力端子と接地間に直列接続
された第１の抵抗と第２の抵抗の接続点である出
力電圧調整端子にそれぞれ接続された差動増幅器
と、その差動増幅器にバイアス電流を供給するた
めの抵抗とで構成される誤差増幅器を有し、この
誤差増幅器の出力となる前記カレントミラー回路
の出力端子より次段の増幅器として用いる第２の
制御トランジスタのベース端子に電流を駆動し、
この第２の制御トランジスタのコレクタ端子を前
記第１の制御トランジスタのベース端子に接続し
て、そのベース端子を制御することにより電源入
力端子へ加えられる入力電圧を一定に保持して定
電圧出力端子へ出力するようにした定電圧電源回
路において、ベースを前記出力電圧調整端子に、
コレクタを前記差動増幅器のバイアス用抵抗の電
流吸引側に、エミツタを前記第２の制御トランジ
スタのエミツタにそれぞれ接続した電流制限検出
用トランジスタと、さらに前記第２の制御トラン
ジスタのエミツタと接地間に接続した電流検出抵
抗を備えたことを特徴とする電流制限保護回路。1. A first control transistor whose emitter and collector are connected in series between a power input terminal and a constant voltage output terminal, and a current mirror circuit whose base and collector of a third transistor are connected to the base of a fourth transistor. , one input to the reference voltage source,
The other input is connected to the output voltage adjustment terminal, which is the connection point between the first and second resistors connected in series between the constant voltage output terminal and the ground, and the differential amplifier is biased. and a resistor for supplying current, and a current is supplied from the output terminal of the current mirror circuit, which is the output of the error amplifier, to the base terminal of a second control transistor used as the next stage amplifier. drive,
By connecting the collector terminal of the second control transistor to the base terminal of the first control transistor and controlling the base terminal, the input voltage applied to the power supply input terminal is held constant and a constant voltage output terminal is obtained. In a constant voltage power supply circuit configured to output to
A current limit detection transistor having a collector connected to the current suction side of the bias resistor of the differential amplifier and an emitter connected to the emitter of the second control transistor, and further connected between the emitter of the second control transistor and ground. A current limiting protection circuit comprising a connected current sensing resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10863783A JPS60522A (en) | 1983-06-15 | 1983-06-15 | Current limit protecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10863783A JPS60522A (en) | 1983-06-15 | 1983-06-15 | Current limit protecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60522A JPS60522A (en) | 1985-01-05 |
| JPH0474732B2 true JPH0474732B2 (en) | 1992-11-27 |
Family
ID=14489838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10863783A Granted JPS60522A (en) | 1983-06-15 | 1983-06-15 | Current limit protecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60522A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3706331B2 (en) | 2001-11-06 | 2005-10-12 | 大和製衡株式会社 | Positive displacement feeder for powder and granule combination balance |
-
1983
- 1983-06-15 JP JP10863783A patent/JPS60522A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60522A (en) | 1985-01-05 |
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