JPH0474885B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switchable signal compressor/expander.

Conventionally, in order to improve the S/N ratio of a particular communication system or a particular recording/reproduction system, it has been known to use a noise reduction device equipped with a signal compressor and a signal expander in that system. .

In particular, the circuit components of the signal compressor and the signal expander are used in common, and the function of the signal compressor and the function of the signal expander can be switched by switching the mode switch. The equipment is manufactured by the Society of Electronics and
Radio Technician Magazine Volume 8 May 6, 1974
Suggested by the monthly issue.

FIG. 1 shows a circuit block diagram of this switchable signal compressor/signal expander. This type of switchable signal compressor/stretcher is a Dolby B
It is well known to those skilled in the art as a type noise reduction system (the term "Dolby" refers to
) is a registered trademark of Dolby Laboratories.

By switching this Dolby B noise reduction system to a signal compressor, the system becomes an encoder. A signal compressor (encoder) compresses the dynamic range of the input signal before it is recorded on audio tape. By switching the system to a signal expander, the system becomes a decoder. A signal expander (decoder) restores the linearity of the dynamic range to the input signal. The noise introduced during the recording/playback process is considerably reduced, so that the signal compressor-signal expander combination acts as a noise reduction device.

In Dolby B noise reduction systems, signal compression/signal expansion operations are typically performed on signal components above a frequency value of 200 Hz.

The well-known encoder/decoder will now be described in detail with reference to the circuit block of FIG.

_The noise reduction device _shown in _FIG .
and a side path l _s between SW and the output terminal T ₂ .

On the main path l _n there is a coupling circuit 10, an inverter 1
1 is placed.

A variable filter 12, a signal amplifier 13, a control amplifier 14, a rectifier/smoothing circuit 15, and an overshoot suppressor 16 are arranged on the side path _Ls .

If the mode switch SW is connected to terminal _T3 , this circuit block becomes an encoder.
The coupling circuit 10 and the inverter 11 on the main path l _n perform linear amplification.

The variable filter 12 changes the amount of transmission for signal components with frequencies of 200 Hz or higher in accordance with the control signal S _c generated by the rectifier/smoothing circuit 15. To explain in more detail, due to the loop of the variable filter 12, signal amplifier 13, control amplifier 14, and rectifier/smoothing circuit 15, when the level of the input signal at the common terminal of the mode switch SW decreases, the amount of transmission from the variable filter 12 increases. do. Therefore, as the input signal level decreases, the side pass
Signal components with frequencies above 200Hz on l _s increase.

If the circuit block is configured as an encoder, the signal on the side path l _s is routed to the main path l _n
Added to the above signal. Therefore, the amplitude in Fig. 2 -
As shown in the frequency characteristics, signal components of 200 Hz or higher gradually have larger amplitude values as the signal level decreases.

On the other hand, if mode switch SW is connected to terminal _T4 , this circuit block becomes a decoder. The inverter 11 on the main path _ln is configured as a signal inverter, and the output signal of this inverter 11 is applied to the common terminal _T5 of the mode switch SW, so that on the side path _ls A signal having the opposite phase to the input signal applied to the input terminal _T1 is now supplied. Therefore, since the signal on the side path l _s is subtracted from the signal on the main path l _n , the amplitude-frequency characteristic of the decoder output signal is
Signal components of 200 Hz or more gradually have smaller amplitude values as the signal level decreases.

The overshoot suppressor 16 limits the amplitude value of the voltage across the terminals applied to the variable filter 12. If this overshoot suppressor 16 were not in place, undesirable changes would occur in high level transient signals.

By the way, prior to the present invention, in order to stop the noise reduction operation of the switchable signal compressor/signal expander, the present inventor set a mode switch.
We considered placing a new terminal T ₀ on SW.

However, according to the inventor's study of the noise reduction device having the circuit configuration as described above, it has been found that there is wasted power consumption when the noise reduction operation is not performed. That is, when the mode switch SW is connected to the terminal _T0 , the side path _Is is inactive. However, a DC bias current continues to flow through each circuit 12, 13, 14, 15 on the side _path Is even if no input signal is supplied. As a result of further study by the present inventor, it was found that when the DC bias current of each circuit on the side path l _s is cut off and the AC or DC non-operation state is made, each circuit on the main path l _n It turned out that it could work properly.

Therefore, an object of the present invention is to provide a switchable signal compressor/compressor that can operate reliably with low power consumption.
The purpose of the present invention is to provide a signal stretcher.

Hereinafter, the present invention will be specifically explained with reference to the drawings.

FIG. 3 is a circuit diagram of a switchable signal compressor/signal expander illustrating one embodiment of the present invention. dashed line
The circuit components within an IC are constructed within a monolithic semiconductor integrated circuit. The numbers in circles indicate the terminal numbers of the integrated circuit IC. Note that the +V _cc power supply in this embodiment is an ultra-low voltage power supply, and
It shall be supplied from a battery with a voltage of 3V.

Main path between input terminal T ₁ and output terminal T ₂
On l _n , there is a coupling circuit 1 consisting of resistors R ₄ and R ₅ .
0 and an inverting amplifier 11 are provided. The input terminal T ₁ is connected to the No. 1 terminal of the IC via the input coupling capacitor C ₁ . Input amplifier 20A, 20B
are configured in the form of a so-called operational amplifier, and each has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The 1st terminal and the 4th terminal are connected through a resistor R ₁ , and further a resistor R ₁
One end of the reference voltage generator 22 is connected to one end of the reference voltage generator 22 . Reference voltage generator 22 generates a reference voltage V _REF . Note that the non-inverting input terminal (+) of the operational amplifier 20A is connected to the ground potential via a resistor R ₁ and a capacitor C ₃ .

The reference voltage V _REF is the operational amplifier 20A, 20B,
It is supplied to each non-inverting input terminal (+) of the inverting amplifier 11. Therefore, the DC potential of each output terminal of operational amplifiers 20A and 20B becomes approximately equal to the reference voltage V _REF . Note that the resistors R ₂ and R ₃ are connected to the operational amplifier 20.
The amplification degree of the inverting amplifier 11 is determined by the resistors R ₄ , R ₅ , and R ₆ .

On the side _path between the mode switch SW and the output terminal _T2 , there is a variable filter 12, a signal amplifier 13, a control amplifier 14, a rectifier/smoothing circuit 15,
An overshoot suppressor 16 is arranged. The variable filter 12 has a capacitance of C ₄ , 4 ₅ and a resistance.
It is composed of R ₁₀₁ , R ₁₀₂ and a variable impedance 23.

The mode switch SW is connected to the No. 5 terminal of the integrated circuit via capacitors C ₄ and C ₅ . The variable impedance 23 is connected to this fifth terminal.

The variable impedance 23 includes transistors Q ₁ ,
Q ₂ , a voltage-current conversion circuit 23A composed of resistors R ₁₁ , R ₁₂ , R ₁₃ , resistor R ₁₄ , diode D ₁₁ ,
_D12 , and a variable current amplifier 23B made up of transistors _Q3 to _Q6 . transistor
The base of Q ₁ is supplied with a reference voltage V _REF . A change in the base voltage V _BE2 of the transistor Q ₂ , in other words, a change in the voltage level at the No. 5 terminal, is converted into a change in the amount of current flowing through the transistors Q ₁ and Q ₂ .
The change in the amount of current is converted back into a voltage change by the diodes D ₁₁ and D ₁₂ and supplied to the bases of the transistors Q ₃ and Q ₄ , respectively. Between the collectors of transistors Q ₃ and Q ₄ and the ground line,
A current mirror circuit is configured by transistors Q ₅ and Q ₆ . The amplification factor of variable current amplifier 23B corresponds to the amount of control current S _c supplied from voltage-current converter 27, which will be described later.

The input impedance Z _io of the variable impedance 23 is determined as described below.
That is, when the current supplied from the voltage-current conversion circuit 23A to the variable current amplifier 23B is _i1 , it is determined as _i1 =α· _Vio (1). However, in the above equation (1), α is the voltage-current conversion rate of the voltage-current conversion circuit 23A, and _Vio is the base input signal of the transistor _Q2 .

If the current fed back from the variable current amplifier 23B to the voltage-current conversion circuit 23A is i ₂ , it is determined as follows: i ₂ =β·i ₁ =α·β·V _io (2). However, in (2) above, β is the current amplification factor of the variable current amplifier 23B. and,
Since β above corresponds to the control current S _c , β=f(S _c ) (3). Therefore, the input impedance Z _io of the variable impedance 23 is determined by Z _io =V _io /i ₂ =V _io /α·β·V _io =1/α·β (4). That is, the input impedance
Z _io is determined by the reciprocal of the product of the coefficients α and β of the voltage-current conversion circuit 23A and the variable current amplification factor 23B. As is clear from equation (3) above, β corresponds to the control signal S _c , so the input impedance
Z _io is controlled by the control signal S _c current amount.

The signal amplifier 13 is configured in the form of a so-called operational amplifier, and has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The non-inverting input terminal (+) is connected to the fifth terminal and the variable impedance 23. A negative feedback circuit composed of resistors R ₁₅ and R ₁₆ is connected between the output terminal and the inverting input terminal (-) of the signal amplifier 13, thereby setting the voltage gain of the signal amplifier 13.

What should be noted here is that a switching transistor Q ₁₁ is connected between the signal amplifier 13 and the ground line.
is provided. This switching transistor _Q11 is controlled to be on or off by a controller 28, which will be described later. When the switching transistor Q ₁₁ is turned off, the DC bias current of the differential transistors Q ₃₅ and Q ₃₆ in the signal amplifier 13 is cut off. Note that the switching transistor _Q11 is controlled to be in an on state during the noise reduction operation.

The output signal of signal amplifier 13 is supplied to overshoot suppressor 16 and control amplifier 14. Overshoot suppressor 16 prevents undesirable changes caused by high level transient signals. That is, the output signal of the overshoot suppressor 16 is equal to the reference voltage as shown in FIG.
The waveform is amplitude limited around V _REF . The output signal of the overshoot suppressor 16 is transmitted to the side path _Is . Note that a buffer amplifier may be provided between the overshoot suppressor 16 and the resistor _R5 .

On the other hand, the control amplifier 14 is configured in the form of a so-called operational amplifier, and has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. Transistors Q ₁₃ , Q ₁₄ and diode D ₁₃ are control amplifier circuit 1
4 output circuits are configured. A resistor is connected to the output terminal.
The frequency characteristics of the control amplifier 14 are set by connecting a frequency characteristic determining circuit network 26 composed of R ₂₂ , R ₁₀₃ and capacitors C ₆ and C ₇ .
Terminal 6 is the resistance of the frequency characteristic determining circuit network 26
It is arranged for connection of R ₁₀₃ and capacitances C ₆ and C ₇ outside the semiconductor integrated circuit.

A switching transistor _Q12 is provided between the control amplifier 14 and the ground line. This switching transistor _Q12 is supplied with the same control signal as the above-mentioned transistor _Q11 . i.e. switching transistor Q ₁₂
When is turned off, the DC bias current of the differential transistors Q ₃₇ and Q ₃₈ of the control amplifier 14 is cut off.

Transistors Q ₁₃ , Q ₁₄ , Q ₁₅ , Q ₁₆ , Q ₁₇ , Q ₁₈
constitutes a full-wave rectifier circuit, especially the transistor
Q ₁₅ , Q ₁₆ , Q ₁₇ , and Q ₁₈ constitute a current mirror circuit, but since transistor Q ₁₈ is configured as a multi-emitter, this transistor Q ₁₈ also performs a current amplification operation. That is, an AC signal is supplied to the non-inverting input terminal + of the control amplifier 14.
Therefore, output transistors Q ₁₃ and Q ₁₄ operate alternately in an on state and an off state. When the output transistor Q ₁₃ is on, the capacitor is connected to the +V _cc power supply line via the transistors Q ₁₇ and Q ₁₃ and the resistor R ₂₂ .
Charging current flows through C ₆ and C ₇ . A current n times the current flowing through the transistor Q ₁₇ , which corresponds to the emitter area, flows through the transistor Q ₁₈ and the load resistor R ₂₃ . A voltage drop occurs across the resistor R ₂₃ , and the anode voltage of the diode D ₃ gradually increases.

On the other hand, when the transistor _Q13 is in the off state and the transistor _Q14 is in the on state, the transistor _Q15 is turned on by the discharge current of the capacitor _C6 . Since the transistors Q ₁₅ and Q ₁₆ constitute a current mirror circuit, current flows from the +V _cc power supply to the transistors Q ₁₇ and Q ₁₆ . transistor Q ₁₈ ,
A current similar to that in the above case also flows through resistor _R26 . Therefore, the control amplifier 1 is connected across the resistor _R23 .
Regardless of the polarity of the input signal applied to 4, a full-wave rectified output signal appears. The full-wave rectified output signal of the control amplifier 14 is transmitted to a rectifier/smoothing circuit 15.

The rectifier/smoothing circuit 15 includes a rectifier 15a composed of a diode _D3 , and a smoothing circuit 15b composed of capacitors _C8 and _C9 , resistors _R104 and _R105 , and a diode _D4 . Diode _D4 adjusts the so-called attack time and recovery time to appropriate values. Terminals 7 and 8 are arranged for connection of capacitors C ₈ and C ₉ and resistors R ₁₀₄ and R ₁₀₅ of the smoothing circuit 15b outside the semiconductor integrated circuit. The output voltage of the smoothing circuit 15b is transmitted to the voltage-current exchanger 27.

The voltage-current exchanger 27 generates at its output a control signal current S _c corresponding to the output voltage of the smoothing circuit 15b. The impedance value of the variable impedance 23 of the variable filter 12 is controlled according to the magnitude of the control signal current S _c .

The voltage-current converter 27 is a transistor forming a differential pair with the emitter follower transistor _Q21 .
Q ₂₂ , Q ₂₃ , transistors Q ₂₄ , Q ₂₅ , and transistors Q ₂₆ , which constitute a current mirror circuit;
Consists of Q ₂₇ , Q ₂₈ , Q ₂₉ etc. The circuit operation of voltage-to-current converter 27 will be described in conjunction with controller 28.

The controller 28 includes transistors forming a differential pair.
Q ₃₁ and Q ₃₂ , a diode D ₅ and a transistor Q ₃₃ forming a first current mirror circuit, and a diode D ₆ and a transistor Q ₃₄ forming a second current mirror circuit. Note that CS ₁ is a constant current circuit. A bias voltage V _REF ' is applied to the base of the transistor Q ₃₁ from the reference voltage generator 22,
The base of the transistor _Q32 is connected to the movable contact C of the noise reduction switch _SW2 via the No. 9 terminal.

A noise reduction switch (hereinafter referred to as a switch) _SW2 is switched to a fixed contact a when performing a noise reduction operation.

Hereinafter, the circuit operation when performing the noise reduction operation will be described. The switch _SW2 is switched to the fixed contact a, and the + _Vcc power of 3V is supplied to the base of the transistor _Q32 . Transistor Q ₃₂ is turned off and transistor Q ₃₁ is turned on. Then, current flows from the +V _cc power supply to the constant current circuit CS ₁ , resistor R ₂₆ , transistor Q ₃₁ , and diode D ₅ . Therefore the forward voltage V _F of diode D ₅
Accordingly, the base voltage V _BE is supplied to each of the transistors Q ₁₁ , Q ₁₂ , and Q ₃₃ .

The transistors Q ₁₁ and Q ₁₂ are turned on, and the signal amplifier 13 and control amplifier 14 perform the predetermined operations as described above. Furthermore, when the transistor _Q33 turns on, current flows through the diode _D6 . Due to the forward voltage of diode D ₆ ,
Base voltage V _BE is supplied to transistor Q ₃₄ .
Transistor Q ₃₄ is turned on, emitter current is applied to transistor Q ₂₁ , and transistor
The base-emitter voltage V _BE is supplied to Q ₂₂ .
Therefore, the voltage-current exchanger 27 is connected to the switch SW ₂
When Q34 is switched to contact a and transistor _Q34 is turned on, it becomes operational.

The current flowing through the transistor Q ₂₁ is controlled by the output voltage of the rectifier/smoothing circuit 15.

Assume now that the output voltage of the rectifier/smoothing circuit 15 is at a high level. This high level output voltage is transmitted to the base of transistor _Q23 via the base-emitter junction of emitter follower transistor _Q21 . Since a voltage follower circuit with a voltage gain of 1 is formed by the transistors Q ₂₂ to Q ₂₆ and the resistors R ₂₄ and R ₂₅ , the transistors
The base voltage of Q ₂₃ is at a high level similar to that of transistor Q ₂₂ . In order to compensate for the negative temperature dependence of the base-emitter voltage of the emitter follower transistor _Q21 , a diode-connected transistor _Q27 is connected in series with the resistor _R25 . Therefore, from the +V _cc power supply, transistor Q ₂₈ ,
The current flowing through Q ₂₉ , resistor R ₂₅ and transistor Q ₂₇ increases. Transistors Q ₂₈ and Q ₂₉ constitute a current mirror circuit, so transistor Q ₂₈
Correspondingly, the current flowing through transistor Q ₂₉ also increases. The current flowing through the transistor Q ₂₉ is supplied to each emitter of the transistors Q ₃ and Q ₄ forming the signal amplifier 13 as a control current S _c .

The increase in the control current S _c reduces the input impedance Z _io as shown in equations (3) and (4) above.

On the other hand, when the output voltage of the rectifier/smoothing circuit 15 becomes low level, the current flowing through the transistor _Q29 , in other words, the control current S _c also decreases.

As is clear from equations (3) and (4) above, as the control current S _c decreases, the input impedance decreases.
Z _io rises.

As described above, the input impedance is determined by the control current S _c output from the voltage-current converter 27.
Z _io control is performed.

By the way, when noise reduction is not performed, the movable contact c of the switch SW ₂ is switched to the fixed contact b. Therefore, the base of transistor _Q32 is grounded via the No. 9 terminal. From +V _cc power supply,
A current flows to the ground line via the constant current circuit CS ₁ , resistor R ₂₇ , and transistor Q ₃₂ . This in turn turns transistor _Q31 off,
The forward voltage V _F of diode D ₅ does not appear. Therefore, transistors Q ₁₁ , Q ₁₂ and Q ₁₃ are turned off at the same time. As a result, the DC bias current of the signal amplifier 13 and the control amplifier 14 is cut off, and both become inactive.

Also, when transistor Q ₃₃ is in the off state,
No current flows through diode D ₆ and transistor Q ₃₄
is also turned off. Thus, transistor Q ₂₁
Emitter current is no longer supplied to. Transistor Q ₂₁ is therefore in the off state, resulting in
Transistors Q ₂₂ to _{Q 29} are all in the off state,
The DC bias currents of these transistors are cut off, and the voltage-current exchanger 27 does not operate. That is, the control current SC cannot be obtained.

Then, the control current SC is no longer supplied to the transistors Q ₃ and Q ₄ forming part of the variable impedance 23, and the DC bias current of these transistors is cut off. Therefore, the variable impedance 23 also becomes inactive. It has already been mentioned that the signal amplifier 13 is inactive. Therefore, overshoot suppressor 16 is not supplied with an AC input signal. There will be no signal on the side path l _s .

As described above, even if there is no signal on the side path l _s , the circuit operation of the main path l _n from the input terminal T ₁ to the output terminal T ₂ is performed normally. That is, even if the power to each circuit on the side path l _s is cut off, only the circuit operation on the main path l _n will be performed.

In addition, in the embodiment described above, the switch SW ₂
is provided separately from the mode switch SW, but they may be linked together. In this case, the mode switch SW is provided with a free terminal so that when the mode switch SW is switched to the free terminal, the switch SW ₂ is switched to the fixed contact a. In this way, the encoder and decoder operate as described above, and when the mode switch SW is connected to the free terminal, the power to the signal compression and signal expansion circuit system is cut off. Therefore, the power consumption of the battery used to obtain the +V _cc power source can be reduced. Even if the power supply has a voltage of about 3V, it can be used for a long time.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of the circuit configuration of the noise reduction device, Figure 2 is a frequency characteristic diagram,
FIG. 3 is a circuit diagram of a noise reduction device showing an embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the circuit operation. SW……mode switch, SW ₂ ……switch,
20A, 20B, 11...operational amplifier constituting a linear amplification circuit, 13...signal amplifier, 14...
Control amplifier, 15... Rectifier/smoothing circuit, 16...
Overshoot suppressor, 23... Variable impedance, 27... Voltage-current converter, 28
... Controller, Q ₁₁ , Q ₁₂ ... Switching transistors forming the control circuit.

Claims (1)

[Claims] 1. An input amplifier 20A connected in series on the main bus lm between the input terminal _T1 and the output terminal _T2 ,
A coupling circuit 10, an inverter 11, and a variable filter 12 and a signal amplifier 13 connected in series on the side bus LS coupled to the coupling circuit 10.
and a control amplifier 14 and a clearer/smoothing circuit 15 arranged to control the transmission amount of the variable filter 12, and either the input signal of the coupling circuit 10 or the output signal of the inverter 11 as described above. The variable filter 1 is equipped with a mode switch SW for supplying the side bus LS.
2 is composed of capacitive elements C ₄ and C ₅ , a resistive element R ₁₀₂ and variable impedance means 23, and the variable impedance means 23
3A and a variable current amplifier 23B, the voltage-current conversion circuit 23A has an emitter that is a resistive element.
A pair of first transistors Q ₁ and Q ₂ are commonly connected through R ₁₁ and R ₁₂ and connected to one terminal of the power supply through a resistive element R ₁₃ , and one terminal of each transistor is connected to the above-mentioned pair. the first transistor of
A pair of diode elements connected to the collectors of Q ₁ and Q ₂ , the other terminal of which is connected in common and connected to the other terminal of the power supply via a resistive element R ₁₄
D ₁₁ and D ₁₂ , and the variable current amplifier 23
B receives the current formed by the output of the clearer/smoothing circuit 15 at the commonly connected emitters, and connects the voltage-current conversion circuit 23A between the bases.
A pair of second transistors Q ₃ , Q ₄ receiving the output of
and a pair of third transistors Q ₅ , Q ₆ connected to the collectors of the pair of second transistors Q ₃ , Q ₄ .
The signal amplifier 13 and the control amplifier 14 each include an amplifier configured as an operational amplifier having a pair of differential transistors Q ₃₅ , Q ₃₆ , Q ₃₇ , and Q ₃₈ . the common emitter of the second transistors Q ₃ and Q ₄ of the variable current amplifier 23B, the signal amplifier 1;
3 and the common emitters of _the differential transistors Q ₃₇ and _{Q 38 in} the control amplifier 14. A switchable signal compressor/signal expander characterized by: 2. A first switching transistor Q 11 is arranged at the common emitter of the differential transistors Q ₃₅ and Q ₃₆ in the signal amplifier 13, and a first switching transistor Q ₁₁ is disposed at the common emitter of the differential transistors Q 35 and Q _{36 in the signal amplifier 13, and the differential transistors Q 37 and} Q 36 in the control amplifier 14
A second switching transistor Q ₁₂ is disposed at the common emitter of Q ₃₈ , and by turning off the first and second switching transistors Q ₁₁ and Q ₁₂ by the output signal of the control means 28, the signal amplifier is turned off. 13. The switchable signal compressor/signal expander according to claim 1, wherein the DC bias current of the control amplifier 13 and the control amplifier 14 is cut off. 3. The switchable signal compressor/signal expander according to claim 1, wherein the switchable signal compressor/signal expander is operated by a power supply voltage (+V _cc ) supplied from a battery.