JPH0475466B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a speed detection method for detecting the speed of an electric motor or the like with high accuracy and high response using a rotary pulse oscillator.

[Background of the invention]

In order to accurately detect the speed of the motor, a pulse oscillator that outputs a pulse train with a frequency proportional to the speed is used. However, even if the motor rotates at a constant speed, the period of each pulse in the pulse train has slot errors due to manufacturing errors in the pulse oscillator. The slot error here refers to the difference in the pulse width of each pulse of the pulse oscillator when the speed of the motor is constant. Therefore, slot errors are averaged and their influence is reduced by measuring multiple periods of input pulses or measuring the number of pulses over a certain period of time. Therefore, detection time is required, speed control response cannot be made high, and since it is not possible to make high response, it is not possible to compensate for mechanical vibration, and furthermore, it is not possible to compensate for impact drop, and detection accuracy deteriorates at low speeds. There is a problem with doing so.

Hereinafter, the problems of the conventional embodiment will be explained in detail. FIG. 1 is a block diagram of a typical example of a stationary Leonard type control device in which a DC motor is driven by a thyristor converter in which thyristors are connected in a Graetz connection.

In Fig. 1, 1 is a power transformer, 2 is a current transformer that detects alternating current, 3 is a thyristor converter that converts commercial frequency alternating current to variable voltage direct current, 4 is a direct current motor, and 5 is a pulse oscillator ( (hereinafter referred to as PLG), 6 is a speed detector that is the object of the present invention, 7
are the speed feedback value S _F from the speed detector 6 and the speed command value
A speed control circuit that generates a current command value I _R according to the deviation from S _R ; 8 a current detector that _converts the output of the current transformer 2 into DC; A current control circuit 10 generates a control angle command V _R according to the deviation from the current period value I _a of the thyristor converter 3 _. This is an automatic pulse phase shifter that performs ignition control.

The operation of the control device having such a configuration is well known and a detailed explanation will be omitted, but in short, the thyristor converter is controlled at a control angle α according to the control angle command V _R such that the motor current I _a becomes the command value I _R By performing the ignition control in step 3, the motor speed S _F is controlled to become the speed command value S _R.

In such a speed control system, speed detection accuracy and speed response depend on the detection accuracy and detection response of the speed detector 6. Therefore, we are trying to improve accuracy by using a detector that generates a pulse train like PLG5. Conventionally, the speed detection method using PLG is as shown in FIGS. 2 to 4. That is, as shown in FIG. 2, the number n of input pulses within the measurement time T _e is measured, and the detected speed value N is set as N=n·60/P·T _e . Here, P is the number of pulses per revolution of the PLG, in other words, per revolution of the motor. This method has errors due to the times ΔT ₁ and ΔT ₂ that occur because the input pulses are not synchronized with the measurement start and end points, and the period T ₁ to _o due to the slot error between each pulse.
Errors occur because the added value does not become 0. Furthermore, when the speed is low, the number of input pulses is small, resulting in a large error and a long detection time.

As shown in Figure 3, PLG pulse train period (m)
There is a method in which the value N is measured for each pulse and the detected value N is set to N=60· _fe /P·m. where f _c is the frequency of the clock pulse. Although this method has good response, PLG
There is a problem in that the slot error of is directly reflected in the detected value N.

Figure 4 shows a method that reduces the drawbacks of the methods shown in Figures 2 and 3.As shown in the figure, the measurement time is synchronized with the input pulse, and the number and period of input pulses during the measurement time (T _c + ΔT) are m ₄ and the speed detection value N is set as N=60・_fe・n ₁ /P・m ₄ . Although this method can reduce the effect of slot error to 1/n1, it has the problem of requiring a long detection time, and the number of pulses decreases at low speeds.
The problem remains that as n ₁ becomes smaller, the influence of slot error becomes larger.

In other words, speed detection accuracy can be improved by lengthening the detection time for capturing the output pulses of the PLG. However, there was a problem in that as the detection time became longer, the responsiveness deteriorated.

[Purpose of the invention]

The purpose of the present invention is to eliminate the influence of slot errors,
It is an object of the present invention to provide a speed detection method capable of detecting speed at high speed and with high accuracy.

[Summary of the Invention] In order to achieve the above object, the present invention provides a speed detection method for detecting the speed of a rotating body based on a pulse train signal obtained by detecting slots arranged at equal intervals on the rotating body. With the rotating body rotating at a constant speed, the time per rotation of the rotating body is measured, and the measured value is divided by the number of slots per rotation to determine the theoretical interval per pulse interval of the pulse train signal. At the same time as determining the value, each pulse interval of the pulse train signal is sequentially measured, and the ratio of each measured value and the logical interval value is determined and tuned to correspond as a correction value for each pulse interval, and the actual measurement is performed. The present invention is characterized in that the measured value of the pulse interval of the pulse train signal is corrected based on the correction value corresponding to the pulse interval.

With this configuration, according to the present invention, the above object is achieved through the following actions.

That is, in tuning, first the theoretical interval value per pulse interval (hereinafter referred to as the theoretical value) is determined based on the actual pulse train signal (preferably periodic pulses obtained for each revolution), and then this theoretical value and each The ratio of the pulse interval to the measured value is used as the correction value. This correction value indicates the percentage of slot error included in the measured value of each pulse interval, and is a universal value for rotational speed.

Then, in actual measurement, by multiplying (or dividing) the measured value of each pulse interval by the corresponding correction value, a corrected measured value corresponding to the theoretical value is obtained simultaneously with the measurement of each pulse interval. This results in
This means that the pulse interval value from which the slot error has been removed is immediately obtained, and the above objective is achieved.

In addition, since the above correction value is a universal value,
By performing tuning at an arbitrary speed, correction can be performed with the same correction value over the entire speed range including restraint, and the speed can be detected with high accuracy.

[Embodiment of the Invention] FIG. 5 shows an embodiment of the speed detection method of the present invention. In the figure, 11 is an initial setting device that initializes the PLG position counter, 12 is a PLG position counter that detects the position from the periodic pulse of each pulse of the PLG output pulse train, and 13 is a pulse interval measurement that measures the period of the pulse train. 14 is a one-period pulse interval measurement counter that measures the interval between periodic pulses generated every rotation of the motor; 15 is a clock pulse generator; 16 is a timing pulse generator that generates a timing pulse when a pulse of a pulse train signal is input; 17 is a clock pulse generator; Timing pulse generator 18 that generates timing pulses when periodic pulses are input
19 is a register that temporarily stores the measured period of the pulse train signal; and 20 is a register that temporarily stores the measured value of the periodic pulse interval. , 21 is a register for temporarily storing the correction calculation pulse train period calculation value, 22 is a setting device for setting the correction initial value, 25 is a switch for switching the correction value to the initial value during tuning, 24 is a switch turned on during tuning, 23 2 is a switch for switching to a write command for inputting the detection correction value to the memory 18 during tuning; 26 is a divider for correcting the measured value of the pulse train period; and 27 is for tuning.
It is composed of a divider that calculates a base pulse train interval from the interval of periodic pulses of the PLG, a divider 28 that calculates a correction value during tuning, and a divider 29 that converts into speed.

In the above configuration, the initial setting device 11 is the counter 1
This is to set the initial value of 2. Note that two types of initial values are set. In other words, the position of each pulse of the pulse train signal output from the PLG from the periodic pulse is reversed depending on the rotation direction of the motor, so the number of pulses P per motor rotation is measured as 0 during forward rotation and the number of pulses P per motor rotation during reverse rotation. It's getting old. Loading this initial value into the counter 12 is as follows:
This is performed at each periodic pulse input timing in accordance with the contents of the forward/reverse signal. This allows PLG
This can be detected by the position counter 12 from the periodic pulse of each pulse of the pulse train signal output from the pulse train signal. That is, the counter is set to 0 by a periodic pulse input during normal rotation, and counts up every time a pulse train signal of the PLG is input. During reverse rotation, it is set to P when periodic pulses are input, and counts down for each pulse input of the PLG pulse train signal. Therefore, the position of each pulse of the PLG pulse train signal from the periodic pulse can be detected. This detection signal is stored in the memory 18 that stores the correction value.
The correction value can be written (during tuning) and read out according to the position of each pulse of the pulse train signal from the periodic pulse.

On the other hand, the period of the pulse train and the interval between periodic pulses can be measured by counting up the counters 13 and 14 with the clock pulses of the clock generator 15 from the time when each input pulse is input until the time when the next pulse is input. Here, registers 19 and 20 are used to temporarily hold the measured values. counter 1
The start (clear) timing of the counters 3 and 14 and the input timing to the registers 19 and 20 are determined by the timing pulse T _R generated at the rising edge of the input pulse including one cycle pulse of the PLG output pulse, as shown in Fig. 6. Register 19, 20
The counter value is stored in , and then the counters 13 and 14 are cleared by the timing pulse T _A generated after time t ₁ . Furthermore, timing pulses occurring after time t ₂ and after t ₃ are stored in register 21 and memory 18.
Used for write timing.

First, during tuning, the electric motor is rotated at a constant speed and set to tuning mode. The switch 25 is on the initial measurement side, and a fixed value of coefficient 1 is output instead of the correction value. Further, 24 and 25 are switched to the tuning mode side. The counter 14 and the register 20 detect the periodic pulse interval m _R shown in FIG.
The theoretical value m ₀ of the period of the pulse train that can be detected when there is no slot error is calculated by m ₀ =m _R /P. On the other hand, the counter 13 and the register 19 calculate the pulse train period _mX corresponding to each pulse position of the pulse train signal of the PLG, that is, _m1 corresponding to each pulse interval position _A1 of the pulse train signal of the PLG, as shown in FIG. , the period before correction is detected as m ₂ corresponding to A ₂ . This detected value _m
is divided by the correction value K _X by the divider 26, but during tuning, _K
1 outputs _mX .

Next, the divider 28 calculates _mX ÷ _m0 to create a correction value _KX . This value _KX is input into memory 18 through switch 24. Here, x is performed one after another from 1 to P, and tuning is completed.
During normal operation after tuning, the switch 23, 2
4 and 25 are on the normal operation side, that is, the switch 23 is switched to the read signal R side, the switch 24 is switched to the OFF side, and the switch 25 is switched to the correction value side.

Therefore, the output M _X of the divider 26 becomes M _X = m _X ′/K _X = m _X ′·m ₀ /m _x . For example, if it rotates at the _same speed as during tuning _, m _{X ′} = m _X , so M _X = _m

Furthermore _, the speed detection value is set by the divider 29 to N= _{60.fc.K.sub.X} / _P.m.sub.X for each pulse train input to the PLG 5.

According to the embodiment of the present invention, the slot error of the PLG can be corrected, and the speed can be accurately detected for each pulse train input.

Next, FIG. 8 shows the configuration of another embodiment of the present invention, which is an example in which program processing is performed using a processor. In the figure, 31 is a current detector that converts and detects current from analog to digital;
32 is a gate pulse generator, 33 is a processor that performs speed control calculations, current control calculations, speed detection calculations, etc., 34 is a memory for storing programs and data, and 35 is a device that inputs speed commands etc. from an input controller, or inputs actual current, etc. Interface circuit that answers the speed etc. to the host controller, 3
6 is a speed detection circuit, 37 is a forward/reverse detector, and 38 is a
A PLG position detection counter C _A , 39 is a counter C _B for measuring the period of the PLG pulse train, 40 is a counter C _C for measuring the interval between periodic pulses of the PLG, and 41 is a clock pulse generating circuit. The detection operation will be explained with reference to FIGS. 9 and 10. First, the operation after tuning will be explained with reference to the flowchart of FIG. In the same figure, it is determined in step 10 whether a periodic pulse has been input, and if it has been input, the step
If the PLG, that is, the motor, is running in the forward direction, the contents of the PLG position counter 12 are set to the initial value 0 in step 20, and if it is in the reverse direction, the contents of the counter 12 are set to P in step 25, and in step 30. to move to. If no periodic pulse is input to step 10, the process jumps to step 30. step
At step 30, it is determined whether the count pulse of the PLG pulse train has been input. If input, the value _mX of the counter C _B is read in step 35, and then the counter C _B is cleared in step 40. Thereafter, in step 45, the value _AX of the counter C _A is read, and in step 50, a correction value _KX for _AX is read out. Next, in step 55, a pulse train interval correction calculation is performed, and M _X = m _X ÷ K _X
get. Next, in step 60, the speed is converted to obtain the detected value N= _60.fe / _M.sub.X.P . The above series of processes will be considered as a speed measurement subroutine, and the process during tuning will be explained with reference to FIG. When tuning, move from step 2 to step 100, and
Initialize with . Initialization in step 100 is a process such as setting the correction value _KX to 1 (x is 1 to P). Next, it is determined in step 110 whether a periodic pulse has been input, and if it has been input, it is determined in step 115.
Then, the value M _R of the counter C _C is read out, and in step 120, the counter C _C is cleared. Next step
The theoretical spacing value at that speed of PLG at 125 m ₀ =
Calculate M _R ÷P and execute speed subroutine 5A. In this speed measurement subroutine 5A, M X, that is, m _X with respect to the PLG value A _X when the correction value is 1 _is detected. Based on this value, a correction value _KX = _mK / _m0 is calculated in step 130. At step 135, it is determined whether or not tuning has been completed, and when it has been completed, a tuning completion flag is set.

In this way, the same detection as in the embodiment shown in FIG. 5 can be performed also by program processing.

〔Effect of the invention〕

According to the present invention, RLG, which was a problem in the past,
This solves the problem of a decrease in detection accuracy and a long detection time due to the effects of slot errors, and allows speed detection to be performed at high speed and with high precision.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a speed control device for an electric motor, Figs. 2 to 4 are timing charts for explaining conventional speed detection methods, and Fig. 5 is a speed control system to which the present invention is applied. Block diagrams showing the configuration of one embodiment of the detector, FIGS. 6 and 7
The figures are a timing chart for explaining the operation of the speed detector shown in FIG. 5, FIG. 8 is a block diagram showing the configuration of a speed control device for an electric motor to which the present invention is applied, and FIG. FIG. 8 is a flowchart showing the contents of the measurement execution subroutine executed by the processor 33, and FIG. 10 is a flowchart showing the processing contents of the processor 33 during tuning. 11...Initial value setter, 12, 13, 14...
Counter, 15... Clock generator, 16, 17
...timing pulse generator, 18...memory,
19, 20, 21...Register, 22...Correction initial value setter, 23, 24, 25...Switcher, 2
6, 27, 28, 29...Divider, 31...Current detector, 32...Gate pulse generator (GPG),
33...Processor, 34...Memory, 35...
Interface circuit, 36...Speed detection circuit, 3
7...Forward/reverse detection circuit, 41...Clock pulse generation circuit.

Claims (1)

[Claims] 1. In a speed detection method that detects the speed of a rotating body based on a pulse train signal obtained by detecting slots arranged at equal intervals on the rotating body, the rotational body is rotated at a constant speed. body 1
Measuring the time per rotation, dividing the measured value by the number of slots per rotation to obtain a theoretical interval value per pulse interval of the pulse train signal, and sequentially measuring each pulse interval of the pulse train signal, Tuning is performed to calculate the ratio of each measured value and the theoretical interval value, and to associate it as a correction value for each pulse interval. A speed detection method characterized by performing correction based on a correction value.