JPH0475549B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a synchronization method when microprocessors are operated in parallel, and in particular, to a method for synchronizing a system clock reference frequency signal into relatively low frequencies. This invention relates to a method for synchronizing parallel operation of a microprocessor with a built-in frequency dividing circuit.

(B) Prior art Generally, when normal microprocessors are operated in parallel, it is not necessary to completely synchronize their operations, and data requests or data transfers are performed asynchronously as necessary. It was on. On the other hand, in recent years, microprocessors with a built-in liquid crystal drive circuit that can directly drive a liquid crystal display device using a dynamic drive method and a frequency dividing circuit that creates a frequency for driving the liquid crystal have been developed, and are being used in many fields. be. However, such microprocessors have a limited number of drive pins, so
When driving a liquid crystal display device with a large number of display elements, a plurality of microprocessors must be operated in parallel. In this case, the plurality of common electrodes of the liquid crystal display device are driven by one microprocessor, and the segment electrodes are driven by the driving output terminals of each microprocessor, so that the common electrodes cannot be driven. The frequency and drive signal of the segment electrodes must be perfectly synchronized.

(c) Purpose of the invention The present invention has been made in view of the above points, and when operating microprocessors in parallel,
The present invention provides a method for completely synchronizing the driving frequency of the common electrode of a display device and the driving signal of the segment electrodes.

(d) Structure of the Invention The present invention provides parallel operation of a first microprocessor and a second microprocessor each having a built-in frequency dividing circuit that divides a reference frequency signal for a system clock into a relatively low frequency. In the synchronization method when performing the synchronization, a reference frequency signal outputted from the frequency signal output terminal OSCOUT of the first microprocessor is supplied to the frequency signal input terminal OSCIN of the second microprocessor; When the frequency divider circuit of the second microprocessor divides the reference frequency signal and a carry occurs from the frequency divider circuit, the signal is output from the output terminal CNT1 of the second microprocessor to the first one. The signal indicating the occurrence of carry is applied to the input terminal INT of the microprocessor, and the first microprocessor to which the signal indicating the occurrence of carry is applied receives the frequency signal input of the second microprocessor. The operation of the second microprocessor is stopped by setting the output terminal OUT1 of the first microprocessor connected to the terminal OSCIN to a predetermined level, and then the operation of the first microprocessor is stopped. When a carry occurs from the frequency dividing circuit, the first microprocessor
The frequency input terminal OSCIN of the second microprocessor is released via OUT1 to restart the operation of the second microprocessor, and the operations of the first microprocessor and the second microprocessor are restarted. This is a configuration that synchronizes the

(e) Example A block diagram of a microprocessor used in this example is shown in FIG. 1, and will be briefly described. 1st
The microprocessor shown in the figure is a 4-bit one-chip microprocessor convenient for electronic watches, and the oscillation circuit 1 has a frequency signal input terminal.
By oscillating the frequency determined by the crystal oscillator 2 connected to OSCIN and the frequency signal output terminal OSCOUT, a reference frequency signal of, for example, 32768Hz is output, and this reference frequency signal is transmitted to the first frequency dividing circuit 3. The second frequency dividing circuit 4 divides the frequency into a 1 Hz signal. Furthermore, the clock generator 5 uses the reference frequency signal to create a system clock for operating the microprocessor, and the control circuit 6
to be applied.

The control circuit 6 executes the instructions of the program stored in the ROM 7 to control the input/output circuits 8,
Liquid crystal drive circuit 9, output circuit 10, RAM 11,
It controls the ALU 12, the second frequency dividing circuit 4, the clock generator 5, etc. When the input/output command is executed, the input/output circuit 8 transfers the data applied to the input/output terminal I/O to the data bus 13.
The data bus 13 performs an operation of importing the data into the data bus 13 or outputting the data sent to the data bus 13 to the input/output terminal I/O. In addition, the liquid crystal drive circuit 9 is a well-known 1/2
A 3-bias 1/3 duty dynamic drive system is adopted, and when a display command is executed, the second frequency divider circuit 4 outputs, for example, based on the data sent to the data bus 13.
Create a segment drive signal using the 32Hz or 64Hz divided output and output it to the output terminals seg1 to seg n, and also output the signal to drive the common electrode to the output terminal.
Output to COM1 to COM3. Furthermore, output circuit 1
0 indicates data bus 1 when the output instruction is executed.
3. Take in the data sent to output terminal
The output terminals OUT1 to OUTN are open-drain type output terminals, and the drains are connected to the output terminals OUT1 to OUTN, respectively, and the sources are connected to the power supply _VDD . type MOS transistor 1
4 are provided respectively, and data is output by controlling the gates of the output circuit 10. On the other hand, the second frequency dividing circuit 4 is reset by the control circuit 6 when the reset command is executed.

Furthermore, one of the important functions of the control circuit 6 is a function related to halting and halt release. This function is normally performed by the clock generator 5 by the control circuit 6 when a halt instruction is executed.
is controlled, the generation of the system clock is stopped, that is, the operation of the microprocessor is stopped, but
When restarting the operation, the conditions can be set by a program. That is, the program can set the case where the signal at the interrupt input terminal INT changes or the case where the carry Ca is output from the second frequency dividing circuit 4.
In addition, if the signal change of the interrupt input terminal INT is set only to release the halt state, the interrupt input terminal
Interrupts are disabled when the INT signal changes.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which the first microprocessor 15 (hereinafter referred to as main
CPU) and second microprocessor 1
6 (hereinafter referred to as sub CPU) to drive the liquid crystal display device 17. Main CPU15
The sub CPU 16 is a microprocessor having the configuration shown in FIG.
A crystal oscillator 18 is connected between the frequency signal input terminal OSCIN of 15 and the frequency signal output terminal OSCOUT.
is connected, and the reference frequency signal created by the crystal oscillator 18 is sent to the output terminal of the main CPU 15.
The signal is applied from OSCOUT to the input terminal OSCIN of the sub CPU 16 via the resistor 19, and the main CPU 15 and sub CPU 16 are connected to operate with the same reference frequency signal. Further, the input terminal OSCIN of the sub CPU 16 is connected to the open drain type output terminal OUT1 of the main CPU 15.
That is, when "1" is output to the output terminal OUT1 of the main CPU 15, the P shown in FIG.
Since the channel MOS transistor 14 is turned on, the input terminal OSCIN of the sub CPU 16 is connected to the power supply V _DD
Since the level is raised and fixed, the reference frequency signal is no longer applied and the operation of the sub CPU 16 is stopped. Furthermore, one of the input/output terminals I/O of the sub CPU 16 (called CNT1) and the main
The interrupt input terminal INT of the CPU 15 is connected, and when the carry Ca is output from the second frequency dividing circuit 4 of the sub CPU 16, a signal indicating this is outputted to the input/output terminal CNT1.

The liquid crystal display device 17 is a display device for dynamic driving, and the common electrode is connected to the output terminals COM1 to COM3 of the main CPU 15, and the segment electrodes are connected to the output terminals seg1 to segn of the main CPU 15 and the sub CPU 16, respectively. Ru.

A method of synchronizing the main CPU 15 and sub CPU 16 connected as shown in FIG. 2 will be explained with reference to the flowcharts shown in FIGS. 3a and 3b. Figure 3 a is the main
This is the operation programmed into the CPU 15, and the third
Figure b shows the operations programmed into the sub CPU 16, both of which are executed immediately after power is turned on.

In FIG. 3a, first, the main CPU 15 is
Outputs "0" to the output terminal OUT1, and then executes the halt command by setting the halt state to be released at the rising edge of the signal applied to the interrupt input terminal INT. At this time, the P channel outputs the output terminal OUT1 = “0” of the main CPU 15.
Since the MOS transistor 14 is off, the sub
A reference frequency signal is applied to the input terminal OSCIN of the CPU 16, and the sub CPU 16 is in an operating state.
Therefore, as shown in FIG. 3b, the sub CPU 16 first receives the carrier output from the second frequency dividing circuit 4.
After setting Ca to release the halt, execute the halt command and enter the halt state. However, even in the halt state, the first frequency dividing circuit 3 and the second frequency dividing circuit 4 are in the operating state, and each frequency dividing stage of the second frequency dividing circuit 4 is all "1".
When the state becomes all "0", that is, the reset state is entered, the carry Ca is output and the sub CPU 16 is released from the halt state. The sub CPU 16 has an input/output terminal CNT.
Outputs “1” to CNT1, resets the setting where the halt is released by carry Ca, and then changes the “1” output to input/output terminal CNT1 to “0”.
shall be. Therefore, the input/output terminal CNT1 has a second
When the carry Ca is output from the frequency dividing circuit 4, a pulse that becomes "1" is output.

On the other hand, the main CPU 15, which is in a halt state,
By applying a signal of "1" from the input/output terminal CNT1 of the sub CPU 16 to the interrupt input terminal INT, the halt state is released and the program proceeds. Then, the main CPU 15 outputs "1" to the output terminal OUT1, resets the second frequency divider circuit 4, and then the halt is released by the carry Ca output from the second frequency divider circuit 4. Set it as follows, execute the halt command, and enter the halt state. Here, output terminal OUT1 is “1”
As a result, the input terminal of sub CPU 16
Since OSCIN is fixed at the power supply V _DD level, the sub
All operations of the CPU 16 are stopped. That is,
Since the reset state of the sub CPU 16 does not change after the carry is output from the second frequency dividing circuit 4 of the sub CPU 16 until the operation of the sub CPU 16 is stopped, the reset state is maintained thereafter. .

Then, the second frequency dividing circuit 4 of the main CPU 15
When the Cary Ca is output from the main CPU1
The halt state of No. 5 is released, the program proceeds, outputs "0" to the output terminal OUT1, and resets the setting where the hold is released by carry Ca. At this time, output terminal OUT1 is “0”
As a result, the sub CPU 16 starts operating again, and the second frequency dividing circuit 4 starts from the reset state. On the other hand, the second frequency divider circuit 4 of the main CPU 15 also has all the frequency divider stages at "0" at this time.
That is, since they are in the reset state, the second frequency dividing circuit 4 of the sub CPU 16 that has started operating and the second frequency dividing circuit 4 of the main CPU 15 are in a completely synchronized state.

Therefore, the liquid crystal drive signal created using the divided output of the second frequency dividing circuit 4, that is, the main CPU 1
The signals for driving the common electrodes outputted from the output terminals COM1 to COM3 of the sub CPU 16 and the segment drive signals outputted from the output terminals seg1 to segn of the sub CPU 16 are completely synchronized.

(F) Effects of the Invention As described above, according to the present invention, the first microprocessor and the second microprocessor can be reliably synchronized by a simple program, and This also has the advantage of improving reliability, since almost no external parts are required for this purpose.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprocessor used in an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIGS. 3a and 3b are diagrams of the microprocessor shown in FIG. FIG. 2 is a flow diagram showing the operation of FIG. DESCRIPTION OF SYMBOLS 1... Oscillation circuit, 2, 18... Crystal resonator, 3... First frequency dividing circuit, 4... Second frequency dividing circuit, 5... Clock generator, 6... Control circuit, 7... ROM, 8
...Input/output circuit, 9...Liquid crystal drive circuit, 10...Output circuit, 11...RAM, 12...ALU, 13...Data bus, 14...MOS transistor, 15...Main
CPU, 16...Sub CPU, 17...Liquid crystal display device,
19...Resistance.

Claims (1)

[Scope of Claims] 1. When a first microprocessor and a second microprocessor having a built-in frequency dividing circuit that divides a reference frequency signal for a system clock into a relatively low frequency are operated in parallel. In the synchronization method, a reference frequency signal output from the frequency signal output terminal OSCOUT of the first microprocessor is supplied to the frequency signal input terminal OSCIN of the second microprocessor; When the frequency divider circuit of the processor divides the reference frequency signal and a carry occurs from the frequency divider circuit, the signal is output from the output terminal CNT1 of the second microprocessor to the first microprocessor. input terminal INT
The first microprocessor to which the signal indicating the occurrence of the carry is applied is connected to the frequency signal input terminal OSCIN of the second microprocessor. Output terminal of microprocessor 1
By setting OUT1 to a predetermined level, the operation of the second microprocessor is stopped. After that, when a carry occurs from the frequency dividing circuit of the first microprocessor, the first microprocessor The processor outputs the frequency input terminal of the second microprocessor via the output terminal OUT1.
Parallel operation synchronization of microprocessors, characterized in that OSCIN is released to restart the operation of the second microprocessor, and the operations of the first microprocessor and the second microprocessor are synchronized. method.