JPH0475646B2 - - Google Patents
Info
- Publication number
- JPH0475646B2 JPH0475646B2 JP62002962A JP296287A JPH0475646B2 JP H0475646 B2 JPH0475646 B2 JP H0475646B2 JP 62002962 A JP62002962 A JP 62002962A JP 296287 A JP296287 A JP 296287A JP H0475646 B2 JPH0475646 B2 JP H0475646B2
- Authority
- JP
- Japan
- Prior art keywords
- multilayer ceramic
- ceramic capacitor
- external electrode
- polishing
- container
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】
本発明は積層セラミツクコンデンサに関し、と
くに実装時の接続の信頼度を向上させる構造の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer ceramic capacitor, and more particularly to a method for manufacturing a structure that improves the reliability of connections during mounting.
従来、積層セラミツクコンデンサは、第1図の
斜視図および第2図の一部拡大断面図に示す如
く、例えばセラミツク絶縁基板1の表面に設けら
れた導電性ランド2の上にはんだ付けなどにより
実装されていた。この導電性ランド2の幅は、積
層セラミツクコンデンサ3の外部電極4の幅より
も広い場合もあるが、一般には隣接する他の部品
との間に所定の間隔が必要となり、限られた実装
スペースの問題から第2図に示されるように外部
電極4の幅に対応した幅のランド2が設けられて
いた。 Conventionally, multilayer ceramic capacitors have been mounted, for example, by soldering onto conductive lands 2 provided on the surface of a ceramic insulating substrate 1, as shown in the perspective view of FIG. 1 and the partially enlarged sectional view of FIG. It had been. The width of this conductive land 2 may be wider than the width of the external electrode 4 of the multilayer ceramic capacitor 3, but generally a predetermined distance is required between it and other adjacent components, and the mounting space is limited. Because of this problem, a land 2 having a width corresponding to the width of the external electrode 4 was provided as shown in FIG.
一方、第3図に積層セラミツクコンデンサ3の
一部断面を含む斜視図を示すように内部電極6は
外部電極4の側面に引出されているので外部電極
4の上下面は引出し面の一辺の稜を越えて電気的
に接続されていた。直方体構造においては一辺の
稜やコーナ部の角の接触摩耗が激しく、また機械
的強度も他の個所より弱いため、第4図に一部拡
大断面図として示されるように突出部の外部電極
4は削り取られ、丸みを帯びた部分7で電気的接
続は開放状態になつてしまう欠点があつた。ま
た、開放状態とならずに第1図の如く実装された
部品であつても、第4図の丸みを帯びた部分7の
電極被着層は薄く、したがつて電気抵抗も大きく
なるため接続の信頼度は極めて低いものであつ
た。 On the other hand, as shown in FIG. 3, which is a perspective view including a partial cross section of the multilayer ceramic capacitor 3, the internal electrodes 6 are drawn out to the side surfaces of the external electrodes 4, so that the upper and lower surfaces of the external electrodes 4 are aligned with the edge of one side of the drawn-out surface. was electrically connected across. In a rectangular parallelepiped structure, contact wear is severe at edges and corners of one side, and the mechanical strength is weaker than other parts, so as shown in a partially enlarged sectional view in FIG. There was a drawback that the electrical connection was left open at the rounded part 7, which was removed. Furthermore, even if the component is mounted as shown in Fig. 1 without being in an open state, the electrode adhesion layer at the rounded part 7 in Fig. 4 is thin, and therefore the electrical resistance becomes large, so the connection reliability was extremely low.
本発明の目的は電気的接続の信頼性が高い積層
セラミツクコンデンサの製造方法を提供すること
にある。 An object of the present invention is to provide a method for manufacturing a multilayer ceramic capacitor with high reliability of electrical connection.
本発明によれば、外部電極形成前の積層セラミ
ツクコンデンサに予め丸みを付けた後、外部電極
4を塗布焼付けることを特徴とする積層セラミツ
クコンデンサの製造方法が得られる。とくに本発
明によれば磁器誘電体を構成する組成に含まれる
材料もしくは500℃〜800℃の高温中で磁器誘電体
と化学反応を起こさない材料やその焼結物からな
る最大粒径1.0mm以下の研摩剤を緩衝液と混合し、
その中に外部電極形成前の積層セラミツクコンデ
ンサを投入してその容器を所定時間回転させ研摩
することにより積層セラミツクコンデンサの各稜
およびコーナー部の角を取り丸みを設ける工程を
含むことを特徴とする積層セラミツクコンデンサ
の製造方法が得られる。 According to the present invention, a method for manufacturing a multilayer ceramic capacitor is obtained, which is characterized in that the multilayer ceramic capacitor is rounded in advance before external electrodes are formed, and then the external electrodes 4 are coated and baked. In particular, according to the present invention, particles with a maximum particle size of 1.0 mm or less are made of materials included in the composition of the porcelain dielectric, or materials that do not cause chemical reactions with the porcelain dielectric at high temperatures of 500°C to 800°C, or sintered products thereof. of abrasive mixed with a buffer solution,
The method is characterized by including the step of inserting a laminated ceramic capacitor before forming external electrodes into the container and rotating and polishing the container for a predetermined period of time to round and round each edge and corner of the laminated ceramic capacitor. A method for manufacturing a multilayer ceramic capacitor is obtained.
以下、第5図〜第8図を参照して本発明を詳述
する。第5図a〜dは本発明の実施に際して用い
る研摩剤の外観形状の具体例を示す斜視図であ
る。研摩効果は第1図aに示す三角柱の形状が最
も優れており次に第1図bの立方体、第1図cの
円柱、第1図dの球体の形状の順に劣つていく。
積層セラミツクコンデンサ自体も研摩剤としての
働きがあり第1図bの形状と同程度の効果があ
る。研摩作業中にこれらの研摩剤も削られ、その
削られた粉末が積層セラミツクコンデンサに付着
し、外部電極焼付処理における高温条件下でコン
デンサの特性を低下させることになる。このため
研摩剤の材料としては、後述するように積層セラ
ミツクコンデンサの誘電体磁器を構成する原材料
や、酸化珪素(SiO2)などの磁器誘電体と高温
で反応しない材料もしくはこれらを組合せたもの
が適当であり、これらの粉末または所定の形状に
プレス加工して焼結したものが用いられる。研摩
剤の大きさは積層セラミツクコンデンサの約10倍
の大きさのものまで選定できるが、研摩後のコン
デンサと研摩剤の分離の容易性から、最大粒径を
1.0mm以下にする必要がある。すなわち積層セラ
ミツクコンデンサの最小形状は、1.0×1.25×2.0
mm程度であり、適当なふるいを使用することによ
つて最大粒径1.0mm以下の研摩剤と容易に分離で
きることになる。第6図に研摩処理前の積層セラ
ミツクコンデンサの外観を示しておく。研摩条件
の一例としては、プラスチツク製の円筒状回転ポ
ツトの全内容積に対して、約50%まで第6図の如
き形状の高誘電率系磁器コンデンサを入れ、その
上に約10〜20%容積比の酸化珪素(SiO2)など
の研摩剤を投入する。次に緩衝液として純水を加
え、全内容積の80〜90%まで満たして、蓋を閉め
回転速度30〜60rpmで1時間〜5時間回転させた
後取り出す。 Hereinafter, the present invention will be explained in detail with reference to FIGS. 5 to 8. 5A to 5D are perspective views showing specific examples of the external shape of the abrasive used in the practice of the present invention. The polishing effect is most excellent in the triangular prism shape shown in FIG. 1a, followed by the cubic shape in FIG. 1b, the cylindrical shape in FIG. 1c, and the spherical shape in FIG. 1d.
The laminated ceramic capacitor itself also acts as an abrasive and has the same effect as the shape shown in FIG. 1b. During the polishing process, these abrasives are also ground away, and the ground powder adheres to the laminated ceramic capacitor, degrading the capacitor's properties under the high temperature conditions of the external electrode baking process. For this reason, the material for the abrasive is the raw material that makes up the dielectric ceramic of the multilayer ceramic capacitor, a material that does not react with the ceramic dielectric at high temperatures, such as silicon oxide (SiO 2 ), or a combination of these materials, as described below. Any suitable material may be used, such as a powder thereof or a product pressed into a predetermined shape and sintered. The size of the abrasive can be selected up to approximately 10 times the size of the laminated ceramic capacitor, but the maximum particle size should be selected for ease of separation between the capacitor and the abrasive after polishing.
Must be 1.0mm or less. In other words, the minimum shape of a multilayer ceramic capacitor is 1.0 x 1.25 x 2.0
mm, and by using an appropriate sieve, it can be easily separated from abrasives with a maximum particle size of 1.0 mm or less. Figure 6 shows the appearance of a multilayer ceramic capacitor before polishing. As an example of the polishing conditions, a high dielectric constant ceramic capacitor having a shape as shown in Fig. 6 is filled to approximately 50% of the total internal volume of a plastic cylindrical rotary pot, and then approximately 10 to 20% of the total internal volume is filled. Add an abrasive such as silicon oxide (SiO 2 ) by volume. Next, pure water is added as a buffer solution to fill the container to 80-90% of the total internal volume, the lid is closed, and the container is rotated at a rotation speed of 30-60 rpm for 1 to 5 hours, and then taken out.
こうして得られた第7図の斜視図に示す如く、
丸みを帯びた積層セラミツクコンデンサの端部に
外部電極を塗布し、焼付けを行なえば第8図に実
装状態の一部断面に示すように外部電極4の全面
にわたり均等な厚さの電極が形成でき、ランド2
との電極接続の信頼度は著しく向上する。 As shown in the perspective view of FIG. 7 obtained in this way,
By applying an external electrode to the rounded end of a multilayer ceramic capacitor and baking it, an electrode with a uniform thickness can be formed over the entire surface of the external electrode 4, as shown in the partial cross section of the mounted state in Figure 8. , Land 2
The reliability of the electrode connection with the electrode is significantly improved.
ここに外部電極の焼付処理は、温度500℃〜800
℃の高温中で行なわれるので、積層セラミツクコ
ンデンサの表面および内部電極引出し部からの侵
入部に付着している研摩剤の微粉末が磁器誘電体
と化学反応を起こすと、磁器誘電体の組成が変化
し、所望の特性が損なわれるのみならず、積層セ
ラミツクコンデンサの信頼度が著しく低下する。
このため、研摩剤の材料としては、磁器誘電体を
構成する組成に含まれる材料粉末かその焼結物が
最も良く、その他の材料については、試作評価の
結果少なくとも500℃乃至800℃の高温中で磁器誘
電体と化学的反応を起こさない材料、例えば酸化
珪素(SiO2)、酸化ジルコニウム(ZrO2)、アル
ミナ(Al2O3)などを選定することによつて、良
好な特性の得られることが判つた。上記の他にも
酸化チタン、チタン酸バリウム、炭酸バリウムな
ども研摩材料として使えよう。 Here, the baking process of the external electrode is performed at a temperature of 500°C to 800°C.
Since the process is carried out at a high temperature of °C, if the fine abrasive powder adhering to the surface of the multilayer ceramic capacitor and the part penetrated from the internal electrode lead-out part causes a chemical reaction with the porcelain dielectric material, the composition of the porcelain dielectric material changes. This not only impairs the desired characteristics but also significantly reduces the reliability of the multilayer ceramic capacitor.
For this reason, the best material for the abrasive is a material powder included in the composition of the porcelain dielectric or its sintered product, and as a result of prototype evaluation, other materials can be used at high temperatures of at least 500°C to 800°C. Good properties can be obtained by selecting materials that do not chemically react with the porcelain dielectric, such as silicon oxide (SiO 2 ), zirconium oxide (ZrO 2 ), and alumina (Al 2 O 3 ). It turned out that. In addition to the above, titanium oxide, barium titanate, barium carbonate, etc. may also be used as polishing materials.
以上説明したとおり、本発明によれば外部電極
形成前の積層セラミツクコンデンサに対して量産
可能な比較的簡単な研摩処理で角および稜部に丸
みを付け、その後外部電極を形成させることによ
り、電気的接続の信頼度が高い積層セラミツクコ
ンデンサが達成される。研摩による曲率半径とし
ては、もとの直方体の最小辺の長さの1/5〜1/10
以上にすれば本願の目的が達成されよう。 As explained above, according to the present invention, corners and edges are rounded by a relatively simple polishing process that can be mass-produced on a multilayer ceramic capacitor before external electrodes are formed, and then external electrodes are formed. A multilayer ceramic capacitor with highly reliable physical connections is achieved. The radius of curvature due to polishing is 1/5 to 1/10 of the length of the minimum side of the original rectangular parallelepiped.
By doing the above, the purpose of the present application will be achieved.
第1図および第2図は従来の積層セラミツクコ
ンデンサの実施例を示す斜視図および一部拡大断
面図。第3図は内部電極の状態を示すための部分
的断面を含む従来のコンデンサの斜視図。第4図
は従来のコンデンサの外部電極部の拡大断面図。
第5図a〜dは本発明の実施例である。研摩材形
状の具体例を示す斜視図。第6図は外部電極形成
前の積層セラミツクコンデンサを示す斜視図。第
7図は第6図の本発明による研摩後の外観を示す
斜視図。第8図は本発明の一実施例を示す実装部
の拡大断面図。
1…セラミツク絶縁基板、2…導電性ランド、
3…積層セラミツクコンデンサ、4…外部電極、
5…はんだ、6…内部電極、7…丸みを帯びた部
分。
1 and 2 are a perspective view and a partially enlarged sectional view showing an example of a conventional multilayer ceramic capacitor. FIG. 3 is a perspective view of a conventional capacitor including a partial cross section to show the state of the internal electrodes. FIG. 4 is an enlarged sectional view of the external electrode portion of a conventional capacitor.
5a to 5d show embodiments of the present invention. FIG. 3 is a perspective view showing a specific example of the shape of the abrasive material. FIG. 6 is a perspective view showing a multilayer ceramic capacitor before external electrodes are formed. FIG. 7 is a perspective view showing the appearance of FIG. 6 after polishing according to the present invention. FIG. 8 is an enlarged sectional view of a mounting section showing an embodiment of the present invention. 1... Ceramic insulating substrate, 2... Conductive land,
3... Multilayer ceramic capacitor, 4... External electrode,
5...Solder, 6...Internal electrode, 7...Rounded part.
Claims (1)
つの端面と4つの側面とを有する角柱状の積層セ
ラミツク体に外部電極を塗布焼付けする積層セラ
ミツクコンデンサの製造方法において、前記磁器
誘電体を構成する組成に含まれる材料もしくは
500℃〜800℃の高温中で磁器誘電体と化学反応を
起こさない材料やその焼結物からなる研摩剤を緩
衝液と混合した容器の中に外部電極形成前の前記
積層セラミツク体を投入して前記容器を所定時間
回転させ研摩することにより前記積層セラミツク
体の各稜およびコーナー部の角を取り丸みを設け
る工程と、前記丸みを介して前記各端面と前記側
面の該各端面近傍領域とを共通に覆うように前記
外部電極を全面にわたり均等な厚さに形成する工
程とを含むことを特徴とする積層セラミツクコン
デンサの製造方法。1. A plurality of internal electrode layers are encapsulated in a ceramic dielectric material, and 2.
A method for manufacturing a multilayer ceramic capacitor in which an external electrode is coated and baked on a prismatic multilayer ceramic body having two end faces and four side faces, the material contained in the composition constituting the ceramic dielectric or
The laminated ceramic body before external electrode formation is placed in a container in which an abrasive agent made of a material that does not cause a chemical reaction with the porcelain dielectric material or a sintered product thereof at high temperatures of 500°C to 800°C is mixed with a buffer solution. a step of rounding and rounding the edges and corners of the laminated ceramic body by rotating and polishing the container for a predetermined period of time; A method for manufacturing a multilayer ceramic capacitor, comprising the step of forming the external electrode to have a uniform thickness over the entire surface so as to commonly cover the external electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP296287A JPS6312120A (en) | 1987-01-09 | 1987-01-09 | Manufacture of laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP296287A JPS6312120A (en) | 1987-01-09 | 1987-01-09 | Manufacture of laminated ceramic capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6312120A JPS6312120A (en) | 1988-01-19 |
| JPH0475646B2 true JPH0475646B2 (en) | 1992-12-01 |
Family
ID=11543993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP296287A Granted JPS6312120A (en) | 1987-01-09 | 1987-01-09 | Manufacture of laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6312120A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0719134Y2 (en) * | 1989-09-20 | 1995-05-01 | ティーディーケイ株式会社 | Ceramic electronic components |
| JP6442881B2 (en) * | 2014-06-17 | 2018-12-26 | 株式会社村田製作所 | Manufacturing method of ceramic electronic component |
| JP6405327B2 (en) * | 2016-02-26 | 2018-10-17 | 太陽誘電株式会社 | Multilayer ceramic capacitor |
| JP6587727B2 (en) * | 2018-09-14 | 2019-10-09 | 太陽誘電株式会社 | Multilayer ceramic capacitor and multilayer ceramic capacitor mounted circuit board |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5634086B2 (en) * | 1974-12-26 | 1981-08-07 | ||
| JPS5734761Y2 (en) * | 1975-08-06 | 1982-07-31 | ||
| JPS5721312Y2 (en) * | 1975-08-06 | 1982-05-08 | ||
| JPS5243970A (en) * | 1975-10-04 | 1977-04-06 | Taiyo Yuden Kk | Method of manufacturing cylindrical ceramic capacitor |
-
1987
- 1987-01-09 JP JP296287A patent/JPS6312120A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6312120A (en) | 1988-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5866196A (en) | Electronic component and method for fabricating the same | |
| JP3531543B2 (en) | Manufacturing method of multilayer ceramic electronic component and multilayer ceramic electronic component | |
| JP7331320B2 (en) | multilayer capacitor | |
| JPS59144116A (en) | Reduced reoxidized semiconductor porcelain condenser | |
| JPH11340089A (en) | Manufacture of multilayer ceramic electronic component multilayer ceramic electronic component | |
| JPH0475646B2 (en) | ||
| JPS6237525B2 (en) | ||
| JPH11343171A (en) | Piezoelectric ceramic, its production and piezoelectric oscillator | |
| JP2872838B2 (en) | Multilayer ceramic capacitor and method of manufacturing the same | |
| EP0104257B1 (en) | High dielectric constant porcelain composition | |
| CN111584234B (en) | Dielectric composition and multilayer capacitor comprising the same | |
| JP2001284157A (en) | Laminated ceramic electronic component | |
| JP2996052B2 (en) | Manufacturing method of ceramic electronic components | |
| JPH0547510A (en) | Chip varistor | |
| JPH08181029A (en) | Manufacture of electronic component | |
| JPH0536501A (en) | Laminated positive characteristic thermistor | |
| US4353106A (en) | Trimmer capacitor | |
| JPH0322883Y2 (en) | ||
| JPH0652718A (en) | Dielectric porcelain and porcelain capacitor | |
| JPH08236306A (en) | Chip type thermistor and manufacturing method thereof | |
| JP4479089B2 (en) | Piezoelectric ceramic composition and piezoelectric ceramic element using the same | |
| JP2996057B2 (en) | Manufacturing method of ceramic parts | |
| JP2679065B2 (en) | Semiconductor porcelain material | |
| JPS6226565B2 (en) | ||
| JP2996060B2 (en) | Manufacturing method of ceramic parts |