JPH0475669B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high current transistor having a new operating mechanism, exhibiting current saturation characteristics, and having a high gain constant.

Conventionally, as a high power transistor,
A static induction transistor (SIT) as shown in Figure 1 has been developed. That is, in the figure, 1 is a substrate made of, for example, an n-type high resistivity semiconductor,
Here, a drain 2 is a high impurity concentration region having the same conductivity type as the substrate 1, a gate 3 is a high impurity concentration region having a conductivity type different from that of the substrate 1 (p type), and a gate 3 having the same conductivity type as the substrate 1. A source 4 as a high impurity concentration region is provided. Further, 5 is an insulating layer, and 6, 7, and 8 are a source electrode, a gate electrode, and a drain electrode made of metal, respectively. Incidentally, FIG. 1b is a diagram showing abbreviations representing this electrostatic induction type transistor.

In the above configuration, first, if a negative voltage V _DS is applied between the drain 2 and the source 4, and a negative voltage V _GS is applied between the gate 3 and the source 4, the non-conformity shown in FIG. 2a will occur. Saturation current characteristics can be obtained. On the other hand, a positive voltage is applied between drain 2 and source 4.
When V _DS is applied and a positive voltage V _GS is applied between the gate 3 and the source 4, saturation current characteristics are obtained as shown in FIG. 2b.

However, in any of the above cases, the voltage that can be applied is limited to the range of V _GS < V _DS < O in the former case, and V _DS > V _GS > O in the latter case, so that arbitrary operations cannot be performed. It is difficult to construct a circuit. Additionally, since it has a vertical structure, when configuring an integrated circuit, it is generally necessary to take out the drain terminal independently to the source terminal side, except for a common drain circuit. This has disadvantages in that it increases and complicates the manufacturing process and also increases the area occupied by the device.

The present invention has been made in view of the above circumstances, and its purpose is to have a current saturation characteristic,
Another object of the present invention is to provide an insulated gate transistor that has a wide operating voltage range, has a horizontal structure, and is easy to configure as an integrated circuit.

In order to achieve such an objective, the present invention
An active layer made of a semiconductor of a first conductivity type, a cathode region made of a high impurity concentration semiconductor of the first conductivity type, and an anode region made of a high impurity concentration semiconductor of the second conductivity type are provided on both ends of the active layer on the insulating layer, and A gate electrode is provided on the active layer via an insulating film at a predetermined distance so as not to overlap with the anode region, and at least in a part under the gate electrode, the thickness of the active layer is The Debye length is less than π/2 times the Debye length specific to the semiconductor constituting the semiconductor. Hereinafter, the present invention will be explained in detail using Examples.

FIG. 3a is a sectional view showing an embodiment of the present invention;
Figure b is a diagram showing the abbreviations. In the figure a, an insulating layer 10 is provided on a semiconductor substrate 9, an active layer 11 made of an n-type semiconductor is provided on this insulating layer 10, and an n-type high impurity concentration is provided at one end of this active layer 11. An anode region 13 having a p-type high impurity concentration is formed at the other end of the cathode region. Further, a gate insulating film 1 is provided on the active layer 11.
A gate electrode 15 made of, for example, a semiconductor is provided via the cathode region 12,
A cathode electrode 16 and an anode electrode 17 are provided on the anode region 13, respectively.

Here, the thickness tc of the active layer 11 is
It has a value less than π/2 times the Debye length _LDE , which is specific to the n-type semiconductor constituting 1. The Debye length L _DE in this case is the so-called extrinsic Debye length, It is expressed as Here, ε _S is the dielectric constant of the semiconductor, which in the case of silicon is 11.7×8.85×
10 ^-14 (F/cm), K is Boltzmann's constant, 1.38×
10 ^-23 (J/K), T is the absolute temperature (K), q is the unit charge of 1.6×10 ^-19 (C), N _D is the carrier concentration of the semiconductor containing impurities, which is near room temperature (300K). It has a value approximately equal to the concentration.

An insulated gate transistor with a similar structure was previously proposed by the applicant (Showa
1955 Patent Application No. 129067). However, in that case, the gate electrode 15 is disposed over almost the entire surface of the gate insulating film 14 on the active layer 11, and the range exhibiting current saturation characteristics is limited under very special conditions. was limited to.

On the other hand, in the present invention, as is clear from FIG.
4 so as not to overlap with the anode region 13, and has an offset distance D (>O) between the anode region 13 and the anode region 13. This offset distance D needs to be longer than the diffusion length of the minority carriers within the active layer 11.
By doing so, almost all of the minority carriers can be recombined within the offset region, and at the same time, majority carrier control by the gate electrode can be stabilized. As a result, current saturation characteristics can more generally be obtained over a wide operating voltage range. Note that there may or may not be an offset between the gate electrode 15 and the cathode region 12.

Next, the operation of the insulated gate transistor having the above structure will be explained.

First, as shown in FIG. 4a, when the gate-cathode voltage V _GK is made negative, the inside of the active layer 11 is depleted. In this case, V _GK is set to a value within a range in which an inversion layer due to holes is not formed at the interface between the active layer 11 and the gate insulating film 14 .

Under such conditions, almost no current flows even if a positive voltage is applied between the anode and cathode. This is because the active layer 11 near the cathode 12
This is because the electrons that should be recombined with the holes injected from the anode 13 into the active layer 11 are hardly injected from the cathode 12 into the active layer 11 because the active layer 11 is depleted.

On the other hand, when V _GK is positive as shown in FIG.
excessively accumulates inside.

Under such conditions, when a positive voltage V _AK is applied between the anode and cathode, holes injected from the anode 13 into the active layer 11 are replaced by electrons accumulated in the active layer 11 near the cathode 12. and the necessary electrons can be recombined with the cathode 12
Since the current is injected one after another from the anode to the cathode, a current _IAK flows between the anode and cathode. In this case, as shown in Figure 5, while V _AK is relatively small, the anode-cathode current I _AK increases in a non-saturated manner like the forward current of a pn junction, but as V _AK increases, , the potential of the part of the interface between the active layer 11 and the gate insulating film 14 directly below the anode side end of the gate electrode 15
Since V _C becomes larger than V _GK and the depletion layer spreads from this part, I _AK becomes saturated. The saturation value of _IAK is determined by the resistance value of the active layer 11 near the cathode 12, and this resistance value is determined by the total amount of electrons accumulated inside the active layer 11 near the cathode 12. Therefore, when V _GK is increased in the positive direction, the amount of electrons increases, the resistance value decreases, and the saturation value of I _AK increases as shown in FIG. In other words, in Figure 5, A, B, and C are the corresponding values when V _GK is positive.
This is a graph showing the dependence of I _AK on V _AK using the value of V _GK as a parameter. The value of V _GK is the largest in A, and decreases in the order of B and C. In addition, in the same figure, D is
It is a graph showing the dependence of I _AK on V _AK when V _GK = O(V). Further, V ₁ indicates the built-in voltage of the anode junction, and V ₂ indicates the withstand voltage between the anode and cathode.

It has already been mentioned that in the above operation, the offset distance D needs to be longer than the minority carrier diffusion length in the active layer. By doing so, it is possible to prevent minority carriers from entering the active layer region under the gate electrode. When minority carriers invade the active layer under the gate electrode, minority carrier recombination occurs within the active layer, which deteriorates the efficiency of majority carrier control by the gate electrode. In this state, the characteristics shown in FIG. 5 cannot be expected, but the characteristics shown in FIG. 6 are obtained. For this reason, the meaning of the offset and its distance in the semiconductor device of the present invention is very large.

On the other hand, the thickness tc of the active layer 11 is the Debye length
Even when there is a relationship such that tc≫(π/2)L _DE with respect to L _DE , when both V _AK and V _GK are made positive, as shown in Figure 6, due to the same effect as described above, Saturation current characteristics can be obtained. In the same figure, as in the case of FIG. 5, the value of V _GK is the largest in A, and decreases in the order of B and C thereafter. Also, D is V _GK = O(V)
The case is shown below.

However, in the case of tc≫(π/2)L _DE , the electron accumulation layer cannot completely cover the entire thickness of the active layer 11, so the current cannot be controlled by the gate voltage V _GK . flows.

That is, in the above configuration, the depth of the majority carrier (electron in this case) region controlled by the gate electric field is approximately (π/2) L _DE . Therefore,
As shown in FIG. 7, the gate electrode 15 of the active layer 11
When the thickness tc of the lower region I is tc(π/2)L _DE , the control of the gate electric field extends to the entire region I (in the figure, the shaded area is controlled by the gate electric field. The number of electrons passing through this region, that is, the number of electrons recombining with holes injected from the anode 13, is determined by the gate electric field. That is, current _IAK is strongly controlled by gate voltage _VGK . In this case, the thickness of the region below the portion of the active layer 11 where the gate electrode 15 is not provided is not particularly limited. However, the length D (offset distance) of the region needs to be longer than the diffusion length of minority carriers within the same region. In contrast, tc
≫ In the case of (π/2) L _DE , as shown in FIG. 8, the region deeper than (π/2) L _DE in the region immediately below the gate electrode 15 of the active layer 11 is dominated by the gate electric field. I don't receive it. Therefore, in this case, the operation of the device is the same as when there is no gate (p ⁺ −n−n ⁺
diode), and I _AK increases monotonically as V _AK increases. However, in this case as well, V _AK
When becomes large enough, I _AK saturates, which means that
Firstly, it is due to the resistance of the above region and the region where the gate electrode 15 is not present, and secondly, it is due to the resistance of the region where there is no gate electrode 15.
This is due to the depletion layer expanding from the point portion. However, the influence of the gate electric field is
Since it extends only to a _part of the active layer 11 below, the proportion of the current that can be controlled by the gate voltage V _GK in the total current is smaller than in the case of FIG. It will be difficult to get GM.

Further, in the case of the present invention, as previously explained with reference to FIG. 4a, when the region shown in FIG. 7 is depleted, no electrons are injected from the cathode 12, so no current flows. In other words, by appropriately selecting the value of V _GK , an off state as shown by D in FIG. 5 can be achieved without fail. On the other hand, in the case of FIG. 8, such an off state may not necessarily be realized depending on the value of tc.

As is clear from the above description, according to the embodiment shown in FIG. Therefore, it is possible to control the gate voltage and obtain a large GM over a wide range of gate voltages. In addition, since it uses the forward current of the pn junction, it is easy to achieve large currents, and therefore,
Easy to get big GM. Incidentally, in an example using single crystal silicon, the active layer thickness tc is 0.11 μm, the gate oxide film thickness is 50 nm, the gate length is 5 μm, the gate width is 30 μm, and the offset distance D between the anode diffusion region and the gate electrode is For 10 μm, V _GK = V _AK =
At 10 (V), I _AK = 20 mA and gm = 2 mS, whereas a surface channel type with the same dimensions and no offset had I _DS = 6 mA and gm = 0.6 mS at the same voltage. It was confirmed that the insulated gate transistor according to the present invention has excellent current value and gm value.

In addition, in the above-mentioned embodiment, only the case where the thickness of the active layer 11 is uniform and tc<(π/2)L _DE was explained, but the present invention is not limited to this, and the active layer 11 The thickness of at least a portion below the gate electrode 15 is tc<
In the case of (π/2) L _DE , the control by the gate electric field extends to the bottom of the active layer 11 in that part, so that the same effect as described above can be obtained.

As described above, according to the present invention, it is possible to realize a large current transistor that exhibits current saturation characteristics and has a high gain constant.

[Brief explanation of the drawing]

Figures 1a and b are cross-sectional views and schematic diagrams showing conventional static induction type transistors, and Figure 2 is a
Figures 3a and 3b are cross-sectional views and schematic symbols illustrating an embodiment of the present invention, and Figures 4a and 4b illustrate the operating principle thereof. FIG. 5 shows an example of its operating characteristics, FIG. 6 shows an example of the operating characteristics of a transistor similar to the present invention, and FIGS. 7 and 8 show examples of the present invention and transistors similar to the present invention. It is a figure which comparatively explains an operating principle. 10... Insulator layer, 11... Active layer, 12...
Cathode region, 13... Anode region, 14...
Gate insulating film, 15...gate electrode, 16...cathode electrode, 17...anode electrode.

Claims (1)

[Claims] 1 an active layer made of a semiconductor having a first conductivity type formed on an insulating layer; a cathode region made of a high impurity concentration semiconductor having a first conductivity type formed at one end of the active layer; an anode region made of a highly impurity-concentrated semiconductor having a second conductivity type formed at the other end of the layer; a gate insulating film formed on the active layer; a gate electrode formed at a predetermined distance so as not to overlap the anode region; a cathode electrode formed on the cathode region; and an anode electrode formed on the anode region; An insulated gate transistor characterized in that the thickness of the active layer is less than π/2 times the Debye length inherent to the semiconductor constituting the active layer, at least in a portion under the gate electrode.