JPH047611B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an error correction circuit for encoding range bits specified in the basic transmission specifications of the PCM subcarrier system in satellite broadcasting.

BACKGROUND TECHNOLOGY In the A mode of satellite broadcast audio transmission, 14-bit level input is divided into 5 levels depending on the size.
Quasi-instantaneous compression is performed in stages within 1 ms.
Set to 10 bits. Therefore, information on which of the five levels the maximum level of the sample value collected within 1 ms falls is sent as a range bit (3 bits). However, it is sent as 8 bits with 4 error correction bits and 1 empty bit. In B mode, quasi-instantaneous compression is not performed, but for error protection,
Information on the maximum value of audio sample values within 1 ms is similarly sent as a range bit. Hereinafter, the range bit with the error correction bit removed will be referred to as a range code to distinguish it from the range bit. The range code arrangement is shown in FIG. 1 for A mode. Code transmission speed is 2048Mb/S
Therefore, in 1 ms, there are 2048 bits, which is considered as one frame, and one frame is the matrix display shown in Figure 1a, and 32 blocks are sent out, with 63 bits as one block. The range code has 8 bits as shown in FIG. 1b, and each bit is assigned to the LSB of the block. In other words, range codes are provided in the column direction. Therefore, the range code is
BCH as 1 bit in block code of data
BCH SEC DED by SEC DED (63, 56) code and as a 7-bit range code
The (7, 3) code undergoes two error corrections.
Here, the BCH SEC DED code is a single error correction
This is a double error detection BCH code, but it will simply be abbreviated as BCH code below. No special circuit is found as an error correction circuit for range codes. In principle, a well-known BCH decoding circuit can be used, but in the case of a range code, the BCH (63, 56) code only corrects one bit, whereas the BCH (7, 3) code Therefore, an efficient error correction circuit is desirable because of the special characteristics of having a small number of information bits and a large number of check bits.

DISCLOSURE OF THE INVENTION An object of the present invention is to provide an efficient range bit error correction circuit in view of the above-mentioned special characteristics of range codes for satellite broadcasting.

The range bit correction circuit of the present invention performs error correction twice. In other words, the first stage of correction consists of a syndrome calculation circuit that receives a block code group of audio/independent data that includes one bit of the range code, and outputs the syndrome as a polynomial expression; a pattern filter that detects a match between the polynomial representation corresponding to the Galois field element of the exponential representation at the position of the polynomial representation of the syndrome; and, when there is a match, one bit correction of the range code in each block code. A means for correcting the bit shall be provided. The second stage of correction includes a serial-to-parallel conversion circuit that outputs the bits obtained by the above means as a parallel range code, and a read-only storage device that is addressed by the range code, and the contents of the storage device are is formed so that all the range bits are written into the address of the range code that is within the Hamming distance of 1 from the range code that includes a specific range bit, and when this is addressed, Outputs corrected and decoded range bits.

In the first stage correction using the BCH (63, 56) code of the range bit correction circuit according to the present invention, there is only one bit to be corrected, and since its position is specified, the original equivalent at this position is This is an extremely simple means of preparing a pattern of polynomial representation of the syndrome, comparing the match with the polynomial representation of the syndrome, determining whether the bit is erroneous, and inverting the bit. Since the syndrome is always calculated when correcting the block code of audio/independent data, it can be used. Next, since the second-stage BCH (7, 3) code has single error correction capability, the range code with Hamming distance 1 is corrected around the range code containing range bits.
Since the number of bits is small, the number of range codes with a Hamming distance of 1 is also small. Therefore, it is actually possible to store the corresponding range bit in advance as the contents of the read-only storage device at an address having the range code of the Hamming distance 1. Since the address of the storage device is a range code, by addressing it and reading its output, the range bit can be immediately decoded and obtained. Taking advantage of this small number of bits, the second stage correction does not require any special operations and can be performed in an extremely short time required for reading data from the storage device.

As described above, by utilizing the unique properties of range codes in BCH (63, 56) and BCH (7, 3) codes, a simple and efficient bit correction circuit can be obtained.

BEST MODE FOR CARRYING OUT THE INVENTION Next, examples of the present invention will be described. FIG. 2 is a block diagram of the total correction circuit of the embodiment, which includes a syndrome calculation circuit 1, a pattern filter 2, a bit extraction circuit 3, an exclusive OR circuit 4, and a first stage BCH (63, 56) code. A correction circuit includes a shift register 5 and a read-only storage device (hereinafter referred to as
(abbreviated as ROM) 6 to second stage BCH (7,3)
A code correction circuit is formed.

First, the first stage correction circuit will be explained.
The generator polynomial for BCH (63, 56) code is G(X)=X ⁷ +X ⁶ +X ² +1 (1) Transforming equation (1), G(X)=(X+1)(X ⁶ +X+1) (1) ' Therefore, the primitive polynomial F(X) becomes F(X)=X ⁶ +X+1 (2). If the root of equation (2) is α, then the Galois field GF
The elements of (2 ⁶ ) can be expressed in exponential expression as 0, 1, α, α ² , ..., α ^26-2 . Also, GF(2 ⁶ ) is F
It can also be expressed as a sign polynomial modulo (X).
Here, the parity check matrix H is H = 1 1 1 ... 1 a a ² ... 1 α ⁶⁰ 1 α ⁶¹ 1 α ⁶² (3) On the transmitting side, the input data is divided into 56 bits A ₆₂ to _{A 7} ,
Assuming that the test bits are 7 bits A ₆ to _{A 0} , 1 1 1 … 1 a a ² … 1 α ⁶⁰ 1 α ⁶¹ 1 α ⁶² A ₀ A ₁ 〓 A ₆ … A ₇ 〓 A ₆₂ = 0 0 (4) A ₀ to ₆ bits are added and transmitted.

On the receiving side, the bit strings containing errors A^ ₆₂ , A^ ₆₁ ,
...Receive A^ ₂ , A^ ₁ , A^ ₀ and find syndromes S ₀ and S ₁ .

S ₀ =A^ ₀ +A^ ₁ +...+A^ ₆₀ +A^ ₆₁ +A^ 62 S ₁ =A^ ₀ +αA^ ₁ +...+α ⁶² A^ ₆₂ Therefore, in the case of a 1 _- bit error, the error bit A^ _i =
Since A _i +1, S ₀ = 1, S ₁ = α ⁱ・1 = α ⁱ (7) Since the exponent of the exponential expression indicates the error position, the correction can be made by inverting the bit at that position. It becomes possible. In addition, in the case of a 2-bit error, A^ _i , A^ _j
If it is an error bit, then S ₀ =0, S ₁ =α ⁱ +α ^j ≠0 (8), and although correction is not possible, error detection is possible.

By the way, satellite broadcasting uses a block code bit structure as shown in Figure 1a.
The bit is always located in the LSB. In equation (4), _A62 is assigned to this bit position. The syndrome calculation circuit 1 uses the primitive polynomial F(X) shown in FIG.
This is an arithmetic circuit that reads the block code from the higher-order A ₆₂ and outputs the block code from each delay element D ₀ to _{D 5 .}
Syndrome _S1 is output as a 6-bit polynomial expression to the outside. Here, the circuit of the delay element D is a circuit for determining the syndrome S ₀ , and the syndrome S ₁ is output only when S ₀ =1. As mentioned above, it is sufficient for the first stage correction circuit to examine whether the bit position of _A62 shown in equation (7) is the position indicated by syndrome _S1 .

In other words, if there is a 1-bit error in A ₆₂ , S ₁ = α ⁶² , but it is only necessary to convert α ⁶² into a polynomial representation of GF (2 ⁶ ) and compare this with the polynomial representation obtained from syndrome calculation circuit 1. . α ⁶² is expressed as a polynomial,
It is expanded as 1 + α ⁵ and becomes (100001). Therefore, a pattern filter 2 (100001) is prepared and compared with the output of the syndrome calculation circuit 1. If they match, a logic "1" is output, and the bit extraction circuit 3 synchronizes from the 63-bit block code. The extracted and output LSB bit is added to the exclusive OR circuit 4 for correction.

Next, the second stage correction circuit will be explained. In the first stage, the LSB of each block code is corrected and input to the shift register 5. When the bits corrected here become 7 bits, they are output in parallel as 7 bits. Since the 8th bit is empty, serial/parallel conversion is performed using 7 bits. 7 bits is
A BCH (7,3) code is formed, and the ROM 6 is addressed using these 7 bits as an address. As shown in FIG. 4, the range bits are encoded as a specific range code for each range. Therefore, a code that is at a Hamming distance of 1 from this particular range code may be corrected to have that range bit due to the nature of the BCH code. For example, (0000111)
If the code comes, range 2 (0100111)
and the distance is 1. Therefore, in ROM6 (0000111)
Write the bit (010) in range 2 as the contents of the address. If the contents of all addresses addressed by a code within a Hamming distance of 1 from a particular range code are written in the range bits in this way, the correct range bits will be immediately output from the ROM 6 by the 7-bit output of the shift register 5. Although BCH codes cannot perform double error correction, they can perform error detection. Therefore, if an appropriate bit, for example (111), is written as the contents of the ROM 6 that is addressed by the code with the double error, an error flag output can be obtained.

[Brief explanation of drawings]

Figure 1 shows the frame structure of the PCM subcarrier system (A
FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram showing an example of a syndrome calculation diagram, and FIG. 4 is a diagram showing the configuration of a range code. It is. DESCRIPTION OF SYMBOLS 1...Syndrome operation circuit, 2...Pattern filter, 3...Bit extraction circuit, 4...Exclusive OR circuit, 5...Shift register, 6...ROM.

Claims (1)

[Claims] 1 Single error correction/double error detection for error control of range bits for satellite broadcasting using PCM subcarrier system
In a system that performs error correction twice using a BCH code, the audio signal containing one bit of the range code is
A syndrome arithmetic circuit receives a block code group of independent data and outputs the syndrome as a polynomial expression, and a polynomial expression corresponding to the Galois field element of the exponential expression at the 1-bit position of the range code in the block code and the syndrome. a pattern filter for detecting a match with a polynomial expression, a means for correcting one bit of a range code in each block code when there is a match, and a bit obtained by the means as a parallel range code. A serial-to-parallel conversion circuit for output and a read-only storage device addressed by the range code are provided, and the contents of the storage device are stored at addresses of the range code within a Hamming distance of 1 from the range code containing the specific range bit. On the other hand, a range bit correction circuit for satellite broadcasting is characterized in that it is formed so that all the relevant range bits are written in, and outputs corrected and decoded range bits when these range bits are addressed. .