JPH0476141B2 - - Google Patents

Description

[Detailed description of the invention] 〔overview〕 The outline of the present invention is as follows.

In a duplex device which outputs a signal indicating the validity of data when data is held in an output buffer and outputs the data when a clock is applied next, a first gate means is provided, the first gate means is The gate means outputs a high level when the output of a signal indicating data validity is low level in both devices, and second gate means are provided corresponding to both devices, and the second gate means: When the output of the first gate means or the signal indicating the validity of the data of the device itself is at a high level, the clock for the device is passed through and applied to the device itself, so that the timing of the out data of both devices is matched. be able to.

[Industrial application field]

The present invention relates to a circuit for matching the timing of out data, and particularly in a duplex character pattern generating device, etc., by applying a clock pulse to both devices when the output signals from both devices match. This invention relates to an out data timing matching circuit that matches the timing of out data.

In order to increase the reliability of character pattern generators, etc., these are sometimes used in duplicate and the occurrence of errors is verified by matching the out data.In this case, the timing of the out data in both character pattern generators is must always match.

[Conventional technology]

Conventionally, character pattern generators using mask ROM etc. have rarely been used in duplicate.
Therefore, no consideration was given to matching the timing of the out data.

[Problem that the invention seeks to solve]

FIG. 4 shows a character pattern generating device to which the present invention is applied. In the figure, an address decoder 1 decodes an externally applied address signal and supplies it to a cell array 2 storing character patterns. At this time, the timing circuit 3
depends on the external output enable signal AE,
A timing signal for decoding is supplied to the address decoder 1. Character pattern data read from cell array 2 is latched in data latch 4 in response to a timing signal from timing circuit 3, and its output is further held in output buffer 5. The timing circuit 6 generates a data valid signal DV indicating that the decoder in the output buffer 5 is enabled in response to the timing signal of the timing circuit 3, and furthermore, when this signal is generated, an external clock signal CLK is generated.
gives an output clock to the output buffer 5 according to the
This causes data to be output from the output buffer.

When such character pattern generators are duplicated, even if the same address is given, the operation timing of both devices is different, so the timing of the data valid signal is different, and even if the same clock is given, the output data may not match. I had a certain problem.

The object of the present invention is to
It is an object of the present invention to provide an out-data timing matching circuit for avoiding mismatches in output data when a duplex configuration is implemented due to causes such as variations in characteristics (etc.). That is, in order to synchronize the outputs of both storage sections, the clock pulses supplied to both storage sections are adjusted depending on the state of the output signal (active low) of the pattern storage section (mask ROM, etc.).

[Means for solving problems]

In a duplex device that outputs a signal indicating the validity of data when data is held in the output buffer and then outputs the data when a clock is applied, each means shown in the principle configuration of FIG. 1 is used. will be established.

Reference numeral 101 is a first gate means, which generates an output when both of the above devices generate a signal indicating data validity.

102 and 103 are second gate means,
It is provided corresponding to each device, and when the output of the first gate means 101 is generated or the signal indicating the validity of data is generated from the own device,
It passes through the clock and outputs to its own device.

[Effect]

When one device generates a signal indicating data validity and the other device does not,
The device generating the signal is not clocked and therefore cannot output data. When a signal indicating data validity is generated from both devices, a clock is applied to both devices at the same time and the data is output, so the timing of out data coincides.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention, and 11
is Noah gate, 12 and 13 are and gate, 1
4 and 15 are OR gates, and 16 and 17 are first and second character pattern generating devices, respectively.

Further, FIG. 3 shows the timing of each part signal in the circuit of FIG. 2, and explains the operation of the circuit of the present invention. In the figure, DV1 and DV2 are data valid signals of character pattern generators 16 and 17, respectively, and when they become low level, the output data of the respective character pattern generators becomes active. CLK1 and CLK2 are external clocks supplied to the character pattern generators 16 and 17, respectively, and data is output from the respective output buffers in accordance with their pulse widths.

As shown in FIG. 3a, when the data valid signal DV2 of the second character pattern generator 17 becomes active at point A before the data valid signal DV1 of the first character pattern generator 16 becomes active. is Noah Gate 11,
The output of the OR gate 15 is at a low level, so the AND gate 13 is closed and the clock CLK2 to the character pattern generator 17 is not supplied. On the other hand, the output of the OR gate 14 is at a high level, so the AND gate 12 is open and the clock to the character pattern generator 16 is
CLK1 is supplied at point A. The clock CLK2 is supplied to the character pattern generator 17 at point B when both the data valid signals DV1 and DV2 become active. Data is output.

As shown in FIG. 3b, when the data valid signals DV1 and DV2 of both character pattern generators become active at the same timing, the outputs of the NOR gate 11 and the OR gates 14 and 15 are at a high level, and the AND gate 12 , 13 are open, and at point B the character pattern generator 16,
17 are supplied with clocks CLK1 and CLK2, respectively, and from this point on both character pattern generators 1
From 6 and 17, data with matching timing is output.

As shown in FIG. 3c, when the data valid signal DV2 of the character pattern generator 17 becomes active after the data valid signal DV1 of the character pattern generator 16 becomes active, the data valid signal DV1 becomes active. In terms of points, Noah Gate 11, Or Gate 14
The output of is at a low level, the AND gate 12 is closed, and the clock CLK1 to the character pattern generator 16 is not supplied. On the other hand, or gate 1
5 is at a high level, the AND circuit 13 is open, and the clock CLK2 to the character pattern generator 17 is supplied. The clock CLK1 is supplied to the character pattern generator 16 at point C when both the data valid signals DV1 and DV2 become active. Data is output.

In this way, in the circuit of the present invention, when data valid signals are not generated simultaneously in both character pattern generators, a clock for reading the output buffer is supplied to the character pattern generator to which the data valid signal is output. Instead, the clock is supplied to both devices only when the data valid signals of both devices are aligned, and the timing of data output from both devices coincides.

〔Effect of the invention〕

As explained above, according to the present invention, data is simultaneously output from both devices only when both devices generate a signal indicating that data is valid, so it is possible to match the timing of out data of both devices. I can do it.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the present invention, Fig. 3 is a time chart showing various signals in the circuit of Fig. 2, and Fig. 4 is a diagram showing the configuration of an embodiment of the present invention. 1 is a diagram showing a character pattern generator. 11...Noah Gate, 12,13...And Gate, 14,15...Or Gate, 16,17...
...Character pattern generator.

Claims (1)

[Claims] 1. In a duplex device that outputs a signal indicating the validity of data when data is held in an output buffer and then outputs the data when a clock is applied, A first gate means 101 is provided which outputs a high level signal when both devices are at a low level, and when the output of the first gate means 101 or the signal indicating the validity of the data of the device is at a high level. Second gate means 102 and 103 for passing the clock to the device are provided corresponding to each device, and in the duplicated pattern storage section, the clock pulses to be supplied to the pattern storage section are controlled depending on the state of the respective output signals. An out data timing matching circuit characterized by adjusting the timing of output data from a pattern storage section.