JPH0476153B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention provides a logical simulation device equipped with a plurality of processors that perform logical simulations, a dedicated memory having a scrolling function and storing simulation results, and a dedicated memory for storing simulation results. When the results are recorded in the storage area, they are recorded in the auxiliary storage device when the scrolling is stopped and when the results need to be saved while scrolling, and are overwritten and recorded in the dedicated memory when the results do not need to be saved while scrolling. Aim for high-speed processing.

[Industrial application field]

The present invention relates to a recording method for a logical simulation device that logically simulates a simulated device.

Recently, with the advancement of technology, devices and circuits manufactured have become more complex, and it is time consuming, inefficient, and economical to prepare these devices or circuits, configure a system, and check the operating status of the system. From the standpoint that it would be too expensive, a simulation device is used to logically simulate the device or circuit.

[Conventional technology]

Conventionally, a logic simulation device is configured as shown in FIG. That is, the logical simulation device includes a plurality of processors 1-1 to 1-1 that logically simulate the simulated device.
It is composed of 1-n. The simulation results of the respective processors 1-1 to 1-n are sent to the host computer 6 via the ultra-high speed bus 3.

The host computer 6 buffers the sent simulation results to the main storage device 4, and
This result is stored in the auxiliary storage device (DASD) 5. Therefore, recording of simulation results depends on the performance of the ultrahigh-speed bus 3 and the host computer 6.

[Problem that the invention seeks to solve]

The conventional logic simulation device mentioned above is
Since it relies on an ultra-high-speed bus and a host computer, there was a problem in that it required a high-performance host computer system that could keep up with the performance of the simulation device.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional situation, it is an object of the present invention to provide a recording method for a logical simulation device that is suitable for storing a large amount of simulation results without being burdened by a host computer.

[Means for solving problems]

In the present invention, as shown in the principle diagram of FIG. 1, a logic simulation device 1 is provided with a dedicated memory 2 that has a scroll function and records simulation results, and also has a dedicated memory 2 and each processor 1-1 to 1-1. n and an ultrahigh-speed bus 3 that connects them.

[Effect]

The simulation results from the processors 1-1 to 1-n are transferred to the dedicated memory 2 via the ultra-high-speed bus 3.
When the results are recorded in the entire area of the dedicated memory 2, the external storage device 5 is used when the scrolling function of the dedicated memory 2 is stopped or when the scrolling function of the dedicated memory 2 is operating and the results need to be saved. When the scroll function is in operation and there is no need to save the results, the unnecessary results in the dedicated memory are overwritten and recorded regardless of the performance of the host computer 6.

Here, the scroll function is the following function.

When data is stored in the dedicated memory 2, the addresses are counted up and stored sequentially from the first address of the storage area, and when the last address is stored, if it is "slow rolling", the address returns to the first address. The current data will be sequentially overwritten on the existing data. Therefore, the dedicated memory 2 stores the latest data corresponding to the capacity of the storage area.

When the "scroll function is stopped", only data up to the final address of the storage area is stored.

With this scrolling function, when abnormal data occurs in the simulation results, one storage area's worth of data can be secured as the data leading to that state. Additionally, if a period for importing simulation results into the host computer is programmed in advance, one storage area's worth of data from before that period can be secured, so even if abnormal data occurs before the scheduled period, the situation will still be affected. can be secured.

〔Example〕

FIG. 2 is a block diagram of an embodiment to which the present invention is applied. The same symbols are used for the same parts as before. The processors 1-1 to 1-n input the simulation results to the dedicated memory 2 via the communication mechanism 7 and the ultra-high speed bus 3. The explanation will be given below with reference to the flowchart shown in FIG. Note that when explaining FIG. 3, numbers in parentheses are used.

The output control section 8 manages output of simulation results by the processors 1-1 to 1-n. When the processor performs output, the output control unit 8
determines that there is an output (1), and counts up the current count value of the write address counter 9, that is, adds the counter addition by the sent result (2). At the same time as the addition, the address of the write address counter 9 is input to the comparator 11 via the selector 10 (the connection will be described later) until it reaches the end address of the dedicated memory 2 held in the end address register 12 ( 3), write control is performed, and (4) the simulation result is written to the dedicated memory 2.

The above process is repeated, and when the write address counter 9 in the comparator 11 matches the last address (3), that is, when the storage area of the dedicated memory 2 is full of results, the contents of the status register 13 are transferred to the decoder 14. It is then determined whether or not to decode and save the simulation results. At this time, the necessity of scrolling and the necessity of saving results are set in advance as output control data.

If there is no need to save, the unnecessary results in the scroll area of dedicated memory 2 are overwritten (4).

When the scroll function is stopped (5) or when it is necessary to save the result (6), the status register 13 is decoded by the decoder 14, the selector 10 is connected to the readout side (7), and the result is stored in the dedicated memory. 2 is read, the counter of the read address counter 15 is added (8), and the send signal is output to the host calculator 6 until the end address is reached in the comparator 11 (9).
(10) Output the simulation results (data) in the dedicated memory 2 to the auxiliary storage device 5 via the main storage device 4.

When the read address of the read address counter 15 becomes the last address in the comparator 11 (9), the comparator 11 reads the status register 13 and sets the read end, and the decoder 14 decodes this end and sends it to the selector 10. Connect to write(11).

The above steps are repeated. In the item described later in step (2) above, the selector 10 is connected to the writing side.

〔effect〕

As is clear from the above description, a large amount of simulation results are recorded in a dedicated memory, which is independent of the performance of the host computer, which is extremely effective in recording a large amount of simulation results efficiently and at high speed.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment to which the present invention is applied, Fig. 3 is a flowchart of an embodiment of the invention, and Fig. 4 is a diagram of a conventional logic simulation device. It is a configuration block diagram. In the figure, 1 is a logic simulation device;
2 is a dedicated memory, 3 is an ultra-high speed bus, 4 is a main storage device, 5 is an auxiliary storage device, and 6 is a host computer.

Claims (1)

[Claims] 1. A logical simulation device 1 comprising a plurality of processors 1-1 to 1-n for logically simulating a device to be simulated is provided with a dedicated memory 2 having a scrolling function and for recording simulation results. When the simulation results have been recorded in the entire storage area of 2, when the dedicated memory 2 is scrolling, if it is necessary to save the simulation results while scrolling is stopped or scrolling, the simulation results are output to and recorded in the auxiliary storage device and are also scrolled. A recording device for a logic simulation device, characterized in that if the results do not need to be saved, the unnecessary results in the dedicated memory 2 are overwritten.