JPH0476213B2 - - Google Patents
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- Publication number
- JPH0476213B2 JPH0476213B2 JP59034263A JP3426384A JPH0476213B2 JP H0476213 B2 JPH0476213 B2 JP H0476213B2 JP 59034263 A JP59034263 A JP 59034263A JP 3426384 A JP3426384 A JP 3426384A JP H0476213 B2 JPH0476213 B2 JP H0476213B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- power supply
- potential power
- terminal
- outside
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
（発明の技術分野）
本発明は、高利得，高周波の増幅を行う半導体
ICに関するものである。[Detailed Description of the Invention] (Technical Field of the Invention) The present invention relates to a semiconductor device that performs high gain and high frequency amplification.
It is about IC.
（従来の技術分野）
第１図は従来例であつて、１はICチツプ外の
高電位電源供給端子、２はICチツプ外の低電位
電源供給端子、３はICチツプ内の入力信号端子、
４はICチツプ内の出力信号端子、５はICチツプ
内の高電位電源供給端子、６はICチツプ内の低
電位電源供給端子、７，８はICチツプ内外を結
ぶボンデイングワイヤおよびIC外部での電源供
給用ラインの寄生インダクタンス、９はICチツ
プの内と外の境界を示す破線、A1〜AoはICチツ
プ内で構成される受動素子または能動素子により
なる増幅回路網である。このような回路網の高電
位電源ラインおよび低電位電源ラインをICチツ
プ内の電源供給端子５，６に一括し、寄生インダ
クタンス７，８の要因であるICチツプ外のボン
デイングワイヤおよび電源供給用ラインを介して
電源を供給する従来の手法では、寄生インダクタ
ンス７，８により交流接地が不完全となり、出力
段の回路（例えばAo）の信号成分がICチツプ内
の電源ラインを介して入力段の回路（例えばA1）
にまわり込み、発振等の不安定動作を生じ易い。(Prior art technical field) Figure 1 shows a conventional example, in which 1 is a high potential power supply terminal outside the IC chip, 2 is a low potential power supply terminal outside the IC chip, 3 is an input signal terminal inside the IC chip,
4 is an output signal terminal inside the IC chip, 5 is a high potential power supply terminal inside the IC chip, 6 is a low potential power supply terminal inside the IC chip, 7 and 8 are bonding wires that connect the inside and outside of the IC chip, and Parasitic inductance of the power supply line, 9 is a broken line indicating the boundary between the inside and outside of the IC chip, and A 1 to A o are amplifier circuit networks made up of passive elements or active elements configured within the IC chip. The high-potential power line and low-potential power line of such a circuit network are integrated into the power supply terminals 5 and 6 inside the IC chip, and bonding wires and power supply lines outside the IC chip, which are the causes of parasitic inductance 7 and 8, are connected to the power supply terminals 5 and 6 inside the IC chip. In the conventional method of supplying power via a circuit (e.g. A 1 )
This tends to cause unstable operation such as oscillation.
第２図は、さらに具体的な従来例であつて、第
１図で説明した記号の他、１０，１１，１４は抵
抗R1，R2，RE、１２，１３はトランジスタであ
る。第１図の構成に基づくこのような従来のIC
チツプ内部への電源供給法では、例えば出力信号
端子４の不整合等により、出力信号端子４に信号
が入力したとするとトランジスタ１３はベース接
地動作となり、記載インダクタンス７が負荷とな
り、端子５に利得を生じ、ICチツプ内の電源ラ
インを介して抵抗１０，１１により分圧され、入
力信号端子３に帰還されたり、端子４からの信号
が抵抗１４、ICチツプ内の電源ライン、抵抗１
１を介して帰還がかかり、発振等の不安定動作を
生じ易くなる。 FIG. 2 shows a more specific conventional example, in which, in addition to the symbols explained in FIG. 1, 10, 11, and 14 are resistors R 1 , R 2 , and R E , and 12 and 13 are transistors. Such a conventional IC based on the configuration shown in Figure 1
In the method of supplying power to the inside of the chip, if a signal is input to the output signal terminal 4 due to, for example, a mismatch between the output signal terminals 4, the transistor 13 operates with the base grounded, the described inductance 7 acts as a load, and a gain is applied to the terminal 5. The voltage is divided by resistors 10 and 11 via the power supply line inside the IC chip, and is fed back to input signal terminal 3, and the signal from terminal 4 is passed through resistor 14, the power supply line inside the IC chip, and resistor 1.
1, and unstable operation such as oscillation is likely to occur.
特にマイクロ波帯に及び高利得，高周波増幅回
路ICでは、僅か数nHのインダクタンスで回路動
作が不安定となり、発振を生じてしまうという問
題があつた。 Particularly in high-gain, high-frequency amplifier circuit ICs that operate in the microwave band, there is a problem in that an inductance of just a few nH makes the circuit operation unstable and causes oscillation.
これを解決するには、端子５，６をμFオーダ
以上の大容量で交流接地すれば良いが、ICチツ
プ内では数十pF程度の小容量値の実現が限界で
あることや、ICチツプ外では、チツプ近傍に外
容量を配置し、交流接地を図ることが考えられる
が、チツプと容量との接続をボンデイングワイヤ
等で行う必要があるため、数nH程度の寄生イン
ダクタンスが付加してしまい、容量とインダクタ
ンスの共振により特性が劣化してしまう等問題が
あつた。 To solve this problem, terminals 5 and 6 should be grounded to AC ground with a large capacitance of μF order or more, but there is a limit to achieving a small capacitance value of several tens of pF inside an IC chip, and In this case, it is possible to place an external capacitor near the chip and attempt AC grounding, but since it is necessary to connect the chip and the capacitor with a bonding wire, etc., a parasitic inductance of about several nH is added. There were problems such as deterioration of characteristics due to resonance between capacitance and inductance.
（発明の目的）
本発明は、この欠点を除去するため、増幅回路
ICの全体回路の電源ラインをいくつかに分割し、
各々についてICチツプ内の電源ラインパタンを
構成し、別個にボンデイングワイヤやラインを介
して電源を供給できるようにして、高利得，高周
波増幅回路ICの発振に対する安定化を図ること
のできる半導体増幅装置を提供するものである。(Object of the Invention) In order to eliminate this drawback, the present invention provides an amplifier circuit
Divide the power line of the entire IC circuit into several parts,
A semiconductor amplifier device that can stabilize the high gain, high frequency amplifier circuit IC against oscillation by configuring the power line pattern in the IC chip for each and supplying power separately via bonding wires and lines. It provides:
（発明の構成および作用） 以下本発明を詳細に説明する。(Structure and operation of the invention) The present invention will be explained in detail below.
第３図は本発明の実施例であつて、１はICチ
ツプ外の高電位電源供給端子、２はICチツプ外
の低電位電源供給用端子、３はICチツプ内の入
力信号端子、４はICチツプ内の出力信号端子、
５−１〜５−ｎはICチツプ内の高電位電源供給
端子、６−１〜６−ｎはICチツプ内の低電位電
源供給端子、７−１〜７−ｎ，８−１〜８−ｎは
ICチツプ内外を結ぶボンデイングワイヤおよび
電源供給用ラインでの寄生インダクタンス、９は
ICチツプの内と外の境界を示す破線、A1〜Aoは
ICチツプ内で構成される受動素子または能動素
子より成る増幅回路網である。 FIG. 3 shows an embodiment of the present invention, in which 1 is a high-potential power supply terminal outside the IC chip, 2 is a low-potential power supply terminal outside the IC chip, 3 is an input signal terminal inside the IC chip, and 4 is a high-potential power supply terminal outside the IC chip. Output signal terminal in IC chip,
5-1 to 5-n are high potential power supply terminals in the IC chip, 6-1 to 6-n are low potential power supply terminals in the IC chip, 7-1 to 7-n, 8-1 to 8- n is
Parasitic inductance in bonding wires and power supply lines connecting the inside and outside of the IC chip, 9 is
The dashed lines A 1 to A o indicate the boundaries between the inside and outside of the IC chip.
It is an amplifier circuit network consisting of passive elements or active elements constructed within an IC chip.
本発明は、増幅回路ICを構成する回路につい
て、回路構成，利得特性，帯域特性，電源供給用
ラインの寄生インダクタンス，ICチツプ内の端
子数を考慮して、適当にA1〜Aoの部分回路に分
割し、A1〜Ao各々について、ICチツプ内の高電
位電源供給端子５−１〜５−ｎおよびICチツプ
内の低電位電源供給端子６−１〜６−ｎを設け、
各々、別個にボンデイングワイヤおよび電源供給
用ラインを介し、ICチツプ外の電源供給用端子
１，２により、電源を加え、動作せしめるもので
ある。このため、ICチツプ外の端子１，２では、
容易に大容量で交流接地を完全に取ることができ
るので、第１図の従来例で示したような、ICチ
ツプ内の電源ラインパタンを介しての部分回路間
の結合がなくなり、信号の電源ラインを介するま
わり込みによる発振等の不安定を改善することが
できる。なお、分解部分でも高利得なほどその部
分回路内での電源ラインパタンを介しての廻り込
みが大きくなるので、本発明では各分割部分の利
得が相等しくなるようにしている。 The present invention appropriately adjusts the portions A 1 to A o of the circuits constituting the amplifier circuit IC, taking into account the circuit configuration, gain characteristics, band characteristics, parasitic inductance of the power supply line, and the number of terminals in the IC chip. The circuit is divided into circuits, and high potential power supply terminals 5-1 to 5-n in the IC chip and low potential power supply terminals 6-1 to 6-n in the IC chip are provided for each of A1 to Ao ,
Power is applied to each of them via power supply terminals 1 and 2 outside the IC chip through separate bonding wires and power supply lines to operate them. Therefore, at terminals 1 and 2 outside the IC chip,
Since it is easy to completely connect AC grounding with a large capacity, the coupling between partial circuits via the power line pattern inside the IC chip, as shown in the conventional example in Figure 1, is eliminated, and the signal power supply can be completely grounded. It is possible to improve instability such as oscillation caused by wraparound via the line. It should be noted that the higher the gain of the decomposed part, the greater the looping through the power supply line pattern within that partial circuit, so in the present invention, the gains of each divided part are made equal to each other.
第４図は、さらに具体的な本発明の実施例であ
つて、第３図で説明した他に１０，１１，１４は
抵抗R1，R2，RE、１２，１３はトランジスタで
ある。本発明の場合、例えば出力信号端子４での
不整合により、端子４から入力すると、トランジ
スタ１３はベース接地として動作し、インダクタ
ンス７−ｎを負荷として、端子５−ｎに利得を生
じる。しかし、ICチツプ内の電源供給用端子５
−１，……５−ｎが分割してあり、ICチツプ外
の端子１，２は容易に大容量で交流接地をとるこ
とができるので、第２図で示した従来の手法のよ
うに、ICチツプ内の電源ラインを介しての入力
部分へ廻り込みがなくなり、信号の電源ラインを
介しての廻り込みによる発振等の不安定を改善す
ることができる。 FIG. 4 shows a more specific embodiment of the present invention, in which, in addition to those described in FIG. 3, 10, 11, and 14 are resistors R 1 , R 2 , and R E , and 12 and 13 are transistors. In the case of the present invention, for example, due to a mismatch at the output signal terminal 4, when an input signal is input from the terminal 4, the transistor 13 operates as a grounded base, and a gain is generated at the terminal 5-n with the inductance 7-n as a load. However, the power supply terminal 5 inside the IC chip
-1,...5-n are divided, and the terminals 1 and 2 outside the IC chip can easily be grounded with a large capacity, so as in the conventional method shown in Fig. 2, This eliminates the looping of signals to the input section via the power supply line in the IC chip, and it is possible to improve instability such as oscillation caused by signals passing through the power supply line.
本発明は、単に寄生インダクタンスの提言を図
ることよりも、ICチツプへの電源供給用ライン
が完全に分離されているため改善効果が大きく、
例えば、寄生インダクタンスを５分の１にするよ
りも５分割したほうが、発振等に対する安定性の
改善を図ることができる。 The present invention has a greater improvement effect than simply proposing parasitic inductance because the power supply line to the IC chip is completely separated.
For example, stability against oscillation can be improved by dividing the parasitic inductance into five parts rather than reducing it to one-fifth.
第５図は伝送利得S21＝66dB帯域1.5GHzを有
する広帯域増幅回路を想定したときのICチツプ
内の電源ラインパタンの５分割時と比分割時にお
ける発振に対する絶対安定性の評価指数である安
定指数（Stability factor）Ｋの周波数特性の比
較を示したものである。これにより、Ｌ＝1nHの
時非分割時においてはで示すようにＫ＜１の領
域が存在し、Ｋ＞１の絶対安定性を確保すること
ができないが、ICチツプ内の電源ラインパタン
を５分割することにより、のように絶対安定を
確保でき、Ｌの値を1/10（Ｌ＝0.1nH）にした非
分割時の特性と比較してもさらに安定であり、
ICチツプ内の電源ラインパタン分割の効果が大
きいことがわかる。 Figure 5 shows the stability, which is an evaluation index of the absolute stability against oscillation when the power line pattern in the IC chip is divided into 5 and when it is ratio divided, assuming a broadband amplifier circuit with a transmission gain S 21 = 66 dB and a band of 1.5 GHz. A comparison of frequency characteristics of index (stability factor) K is shown. As a result, when L=1nH and non-time division, there exists a region where K<1 as shown in , and absolute stability of K>1 cannot be ensured, but the power line pattern inside the IC chip is By dividing, it is possible to ensure absolute stability as shown in the figure, and it is even more stable compared to the characteristics when the value of L is reduced to 1/10 (L = 0.1nH) without dividing.
It can be seen that the effect of dividing the power line pattern within the IC chip is significant.
（発明の効果）
以上説明したように、本発明は増幅回路ICに
おいて全体回路の電源ラインを各分割部分の利得
が相等しくなるように分割し、ICチツプ内の電
源供給用ラインパタンを分割部ごとに構成して個
別に電源を供給することにより、従来のような
ICチツプ外の電源供給用ボンデイングワイヤ，
ラインの寄生インダクタンスの影響で、信号が
ICチツプ内の電源ラインパタンを介してまわり
込むことがなくなり、発振などの不安定動作に対
して改善を図ることができる。特に、発振の生じ
易い高利得，高周波増幅回路ICでは、電源を分
割して供給することにより、大きく安定性を確保
することができる。(Effects of the Invention) As explained above, the present invention divides the power supply line of the entire circuit in an amplifier circuit IC so that the gain of each divided part is equal, and the power supply line pattern in the IC chip is changed between the divided parts. By configuring and supplying power separately for each
Bonding wire for power supply outside the IC chip,
Due to the parasitic inductance of the line, the signal
This eliminates the possibility of looping through the power line pattern inside the IC chip, making it possible to improve unstable operations such as oscillation. Particularly in high-gain, high-frequency amplifier circuit ICs that are prone to oscillation, stability can be greatly ensured by dividing and supplying the power supply.
第１図，第２図は従来の増幅回路ICの電源供
給例を示す回路図、第３図，第４図は本発明の半
導体増幅装置ICの実施例を示す回路図、第５図
は本発明実施例の効果を示す特性図である。
１……ICチツプ外の高電位電源供給端子、２
……ICチツプ外の低電位電源供給用端子、３…
…ICチツプ内の入力信号端子、４……ICチツプ
内の出力信号端子、５（５−１〜５−ｎ）……
ICチツプ内の高電位電源供給端子、６（６−１
〜６−ｎ）……ICチツプ内の低電位電源供給端
子、７（７−１〜７−ｎ），８（８−１〜８−ｎ）
……ICチツプの内外を結ぶボンデイングワイヤ
およびIC外部の電源供給用ラインの寄生インダ
クタンス、９……ICチツプの内と外の境界を示
す破線、１０，１１，１４……抵抗、１２，１３
……トランジスタ、A1〜A11……増幅回路網。
1 and 2 are circuit diagrams showing an example of power supply to a conventional amplifier circuit IC, FIGS. 3 and 4 are circuit diagrams showing an embodiment of the semiconductor amplifier IC of the present invention, and FIG. It is a characteristic diagram showing the effect of the invention example. 1...High potential power supply terminal outside the IC chip, 2
...Low potential power supply terminal outside the IC chip, 3...
...Input signal terminal in IC chip, 4...Output signal terminal in IC chip, 5 (5-1 to 5-n)...
High potential power supply terminal in IC chip, 6 (6-1
~6-n)...Low potential power supply terminal in IC chip, 7 (7-1 to 7-n), 8 (8-1 to 8-n)
... Parasitic inductance of the bonding wire connecting the inside and outside of the IC chip and the power supply line outside the IC, 9 ... Broken line indicating the boundary between the inside and outside of the IC chip, 10, 11, 14 ... Resistance, 12, 13
...Transistor, A1 to A11 ...Amplification circuit network.
Claims (1)
において、ICチツプ内部は複数の高電位電源端
子および複数の低電位電源端子を備えて複数の増
幅器部分に分割され、該複数の高電位電源端子は
当該各端子ごとに引き出されたボンデイングワイ
ヤまたはラインを介してICチツプ外の高電位電
源端子に接続され、前記複数の低電位電源端子は
当該各端子ごとに引き出されたボンデイングワイ
ヤまたはラインを介してICチツプ外の低電位電
源端子に接続され、さらに前記複数の増幅器部分
はほぼ相等しい増幅利得を有するように構成され
たことを特徴とする半導体増幅装置。1. In a semiconductor amplifier device that performs high-gain, high-frequency amplification, the inside of an IC chip is divided into a plurality of amplifier parts each having a plurality of high-potential power supply terminals and a plurality of low-potential power supply terminals, and the plurality of high-potential power supply terminals are Each terminal is connected to a high potential power supply terminal outside the IC chip via a bonding wire or line drawn out for each terminal, and the plurality of low potential power supply terminals are connected to a high potential power supply terminal outside the IC chip via a bonding wire or line drawn out for each terminal. 1. A semiconductor amplifier device connected to a low potential power supply terminal outside an IC chip, and further comprising a plurality of amplifier sections configured to have substantially equal amplification gains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3426384A JPS60178657A (en) | 1984-02-27 | 1984-02-27 | Semiconductor amplifying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3426384A JPS60178657A (en) | 1984-02-27 | 1984-02-27 | Semiconductor amplifying device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60178657A JPS60178657A (en) | 1985-09-12 |
| JPH0476213B2 true JPH0476213B2 (en) | 1992-12-03 |
Family
ID=12409281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3426384A Granted JPS60178657A (en) | 1984-02-27 | 1984-02-27 | Semiconductor amplifying device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60178657A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4223614A1 (en) | 2022-01-20 | 2023-08-09 | Kabushiki Kaisha Toshiba | Rail track branch detection apparatus and program |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02113565A (en) * | 1988-10-22 | 1990-04-25 | Nec Corp | semiconductor integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57129530A (en) * | 1981-02-05 | 1982-08-11 | Nec Corp | Integrated circuit |
-
1984
- 1984-02-27 JP JP3426384A patent/JPS60178657A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4223614A1 (en) | 2022-01-20 | 2023-08-09 | Kabushiki Kaisha Toshiba | Rail track branch detection apparatus and program |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60178657A (en) | 1985-09-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |