JPH0476219B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a conductivity modulation type semiconductor device,
In particular, it relates to improving its fracture resistance.

[Prior art]

An example of a power MOS FET having a configuration similar to a conventional semiconductor device of this type is shown below.
Figure 1 shows a part of a cross section of a power MOS FET. In the figure, 1 is a semiconductor substrate of the first conductivity type, that is, a low concentration drain region of the first conductivity type, 1' is a high concentration drain region of the first conductivity type, and 2 is a semiconductor substrate formed on the surface of the semiconductor substrate 1. 2 is a convex portion thereof; 3 is a source region of a first conductivity type formed in the second conductivity type semiconductor region 2 (first conductivity type semiconductor region 2); 4 is an insulating film, 5 is a gate electrode, 6 is a source electrode insulated from the gate electrode 5 by the insulating film 4, 7 is a channel forming region, and 8 is a drain electrode.

Although not shown in FIG. 1, the second
For example, an alloy layer of silicon and aluminum is formed between the surfaces of the first conductivity type semiconductor regions 2 and 3 and the source electrode 6.
When heated to about 430° C. in the sintering step of formation, the silicon of the semiconductor regions 2 and 3 and the aluminum of the source electrode 6 are alloyed by the heating. This functions to eliminate the current barrier between silicon and aluminum.

A power MOS FET has a structure in which a large number of such basic units are connected in parallel.

In the power MOS FET having the above configuration, when a drain voltage is applied between the drain electrode 8 and the source electrode 6 and a gate voltage is applied between the gate electrode 5 and the source electrode 6, a channel is formed in the channel forming region 7. Therefore, a drain current flows between the drain electrode 8 and the source electrode 6. At this time, by controlling the gate voltage applied between the gate electrode 5 and the source electrode 6, the drain electrode 8
The drain current flowing between the electrode 6 and the source electrode 6 can be controlled. Note that the short circuit between the region 2 and the source region 3 due to the source electrode 6 is caused by the channel forming region 7.
is essential for fixing the potential of

Power MOS FET uses minority carrier injection,
Since accumulation is basically not a problem, it has the advantage of being able to operate at high speed, but it does not have a mechanism like bipolar transistors and thyristors in which conductivity modulation by minority carriers lowers the ON resistance in the high resistance region. , the ON resistance is larger than that of bipolar elements. For this reason, the power
In MOS FETs, increasing the peripheral length of the active region and thinning the high resistance region 1 are concerns in order to increase current capacity. Therefore, it can be said that an effective design is to make the high resistance region 1 as thin as the breakdown voltage characteristics of the element allow.

Nevertheless, the reason why the convex portion 2' as shown in the figure exists in the second conductivity type semiconductor region 2 is as follows.

Figure 2 shows the output characteristics of the power MOS FET. In Figure 1, if there is no convex portion 2', when a breakdown current flows, this power MOS
FETs tend to destroy instantly. This destruction mode will be explained below. Figure 3a shows the convex portion 2'
FIG. 3b shows the equivalent circuit of this part. Now, the voltage applied between the source and drain is increased, and when the voltage reaches the breakdown voltage value between drain region 1 and region 2, a breakdown current shown by the arrow in FIG. 3a flows.

At both ends of the source region 3, there are substantially bipolar transistors as shown in FIG. 3b.
It has a structure in which Tr is parasitic. For this reason,
The current Jc flowing under the source region 3 is the resistance Ra
It flows out from the source electrode 6 through the equation,
When condition (1) is satisfied, a state appears in which the parasitic transistor Tr becomes conductive.

0.6(v)＜Jc＊Ra...(1) This phenomenon first occurs in a small area of the power MOS FET, and even after the parasitic transistor becomes conductive, it cannot remain in a stable state and enters a blocking oscillation state. . In such a situation, the semiconductor element will be destroyed in a short time.

This mode of destruction can be achieved by forming a convex portion 2'.
Breakdown occurs only in the center of region 2, and the breakdown current under the source region can be reduced, and the resistance Ra under the source region can be reduced, resulting in a significant improvement.

In this way, even this conventional structure can cope with the breakdown phenomenon between the source and drain, that is, the generally-called primary breakdown phenomenon of semiconductor devices. Generally speaking, MOS FETs are said to be free from secondary breakdown phenomena, which is a serious problem with bipolar transistors, but the vertical power MOS FETs that are the subject of this invention have parasitic transistors, so A destructive phenomenon occurs.

This phenomenon is likely to occur in high-voltage, high-speed switching operations, but if the voltage and current applied to the switching element are out of phase, as in a normal switching regulator, there is no problem at all, and the current This phenomenon only occurs in an operating mode where high voltage is applied while the current is flowing.

For example, when high-speed switching is performed in the inverter circuit shown in FIG. 4, this secondary destruction easily occurs. In order to control the current flowing to the load L in this circuit, power MOS transistors placed diagonally
The pair of FETs A, D or B, C may be turned ON and OFF at an arbitrary ratio (time ratio).
Since the current flowing through load L takes a continuous value, if power MOS FETs A and D are turned OFF and B and C are turned ON and OFF, B and C are OFF.
When , the current flowing through the load L is the power MOS FET
It returns to the power supply Vcc through freewheeling diodes A1 and D1 connected in antiparallel to A and D.

This freewheeling diode needs to be for high speed, so a separate element A1 from power MOS FETs A to D is used.
~D1 is connected, but as shown in Figure 3, the power MOS FET has a structure in which a diode D is built inside, so that part of the freewheeling current that should flow through the freewheeling diode is will flow through the power MOS FET chip.

Following this state, the power MOS in the OFF state
A after the ON signal is input to FET B and C,
The voltage Vd waveform of the D side freewheeling diodes A1 and D1,
Figure 5 shows an example of the waveform of the current Im flowing through power MOS FETs B and C. This is especially true for power MOS
This is the waveform when the FET switching speed is not limited, and is the waveform for power MOS FETs B and C.
When ON, the freewheeling diode A1 on the A and D side
The recovery current of D1 increases almost linearly. This rate of increase is determined by the ratio Vcc/Lo between the power supply voltage Vcc and the wiring inductance Lo. While not recovering, the freewheeling diode assumes a very low impedance value, and the power MOS
FETs B and C hold the power supply voltage. That is, the power MOS FETs B and C are exposed to a state in which a large current flows while the power supply voltage is applied. This state is generally called a short circuit state. A,
Voltage starts to be applied to the C-side element abruptly in the middle of the recovery period, and takes an excessive peak value when the recovery current attenuates.

Such a short-circuit condition may occur if the recovery characteristics of the freewheeling diode are poor, especially in high-frequency operation.
It causes significant power loss and power MOS
It may cause destruction of FET. This mode of destruction is typically caused mainly by temperature rise due to heat generation, and is not a secondary destruction phenomenon.

The secondary destruction that is a problem with power MOS FETs is
This occurs in the A and C side MOS FETs explained above. A,
The necessary conditions for the C side MOS FET to be destroyed are:
It is as follows.

(1) Freewheeling current flows through the MOS FET.

(Connect a diode in series with the MOS FET,
If the freewheeling current is made to flow exclusively through the freewheeling diode, no damage will occur. ) (2) The recovery time of freewheeling current is longer for MOS FETs than for freewheeling diodes.

(If a normal type free wheel diode is used instead of a high speed type, no damage will occur.) (3) The rise of the voltage applied during recovery operation must be steep.

(Destruction does not occur if a snubber is installed to suppress the voltage rise.) All of these are basically the same secondary destruction phenomena that occur when bipolar transistors are used in inverters. The secondary fracture phenomenon of this mode can be explained as follows.

Consider a case where even a small amount of current flows through the power MOS FET during freewheeling, and the junction within the MOS FET is not fully recovered before a steep voltage is subsequently applied during recovery. At this time, the minority carriers remaining in the high resistance region 1 of the drain are accelerated by the electric field at the same time as a voltage is applied, and move to the region 2 on the source side. If the rise of the high voltage is extremely steep, by the time all remaining minority carriers reach region 2,
The avalanche multiplication phenomenon of minority carriers caused by the electric field may become impossible to ignore. The minority carriers moving to region 2 correspond to a base current being supplied to the parasitic transistors Tr formed at both ends of the source region. In other words, if the avalanche multiplication phenomenon of minority carriers satisfies the condition shown in equation (1), then
The parasitic transistor becomes conductive. When the parasitic transistor becomes conductive, new carriers are supplied to the high resistance region of the drain, and a positive feedback loop can be established in which these carriers are again injected into the base region of the parasitic transistor due to the avalanche multiplication phenomenon.

The conditions for the existence of this positive feedback loop basically depend on the electric field strength in the high resistance region of the drain and the emitter-base resistance value Ra and hFE value of the parasitic transistor. In other words, the electric field strength is strong and the resistance value Ra
When hFE and hFE are large, this positive feedback can easily occur. Once the positive feedback state is entered, conduction in this region will not stop unless the power supply voltage decreases and the electric field strength decreases. In this situation, a local region of the element operates at a high current density while a high voltage is applied, and sooner or later the element will be destroyed due to a direct temperature rise due to heat generation.

In the case of bipolar transistors,
It has the advantage of not operating at as high a frequency as a MOS FET, but by applying a sufficient reverse bias between the emitter and base, the current flowing through the transistor during freewheeling can be cut off, preventing secondary breakdown in this mode. can escape. However, power MOS FETs do not have the ability to actively cut off current during freewheeling like bipolar transistors. For this reason, conventional vertical power MOS
It must be said that FETs have serious deficiencies as general-purpose power devices.

I have explained the power MOSFET above, but
Insulated gate bipolar transistor (hereinafter referred to as
When trying to solve the problem of thyristor operation, which is the biggest problem with IGBTs, the key is to suppress the operation of the part that corresponds to the parasitic transistor of the power MOSFET. this
The IGBT is one in which the first conductivity type high concentration drain region of the power MOSFET shown in FIG. 1 is replaced with a second conductivity type high concentration semiconductor region. For example, FIG. 7 shows a conventional IGBT, in which reference numeral 20 is a semiconductor substrate of a first conductivity type, and reference numeral 21 is a high concentration semiconductor layer of a second conductivity type, which is bonded to the semiconductor substrate 20. 22 is an emitter layer as a first conductivity type semiconductor region, 23 is an emitter electrode as a second electrode, and 24 is a collector electrode as a first electrode.

[Purpose of the invention]

This invention was made in view of the problems of the conventional devices as described above, and provides a conductivity modulation type semiconductor device that can improve secondary breakdown resistance by reducing the emitter-base resistance and hFE of a parasitic transistor. It is intended to.

[Means to solve the problem]

A conductivity modulated semiconductor device of the present invention includes a plurality of semiconductor regions of a second conductivity type arranged on the surface of a semiconductor substrate of a first conductivity type, and a center portion is opened in the surface region of each of the semiconductor regions of the second conductivity type. a first conductivity type semiconductor region is disposed, and an electrode electrically connected to the first conductivity type semiconductor region and the second conductivity type semiconductor region is disposed on a surface of a central portion of the first conductivity type semiconductor region. A gate electrode is disposed on the surface of the second conductivity type semiconductor region between the first conductivity type semiconductor region and the semiconductor substrate via an insulating film, and a gate electrode is provided in the central part of the first conductivity type semiconductor region. An alloy layer made of the semiconductor material of the semiconductor substrate and a metal is provided in the region where the alloy layer is made of the semiconductor material of the semiconductor substrate and has a thickness equal to or more than the thickness of the first conductivity type semiconductor region and not exceeding the thickness of the second conductivity type semiconductor region. It is something.

[Effect]

In the conductivity-modulated semiconductor device configured as described above, by providing an alloy layer, the width of the emitter region is narrowed, the resistance value of the emitter-base resistance of the parasitic transistor is reduced, and the density of recombination centers is also reduced. Since the high alloy layer is located near the emitter region, hFE is also reduced, making it difficult for parasitic transistor operation to occur.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 shows a cross section of a main part of an embodiment of the invention of the present application. In the figure, parts that are the same as or corresponding to those in FIG. 7 are designated by the same reference numerals.

The difference between this embodiment and the conventional one is as follows:
The point is that the alloy layer 9 is present at the location where the emitter electrode 23 is joined to the semiconductor regions 2 and 22. This alloy layer 9 is formed deeper than the emitter region 22, and the PN junction in the electrode junction region is broken.
By forming this alloy layer 9 deeply, the emitter region 22, which was initially formed to have the same width as in the case of FIG. 7, has become narrower than that in the case of FIG. Since the resistance value Ra is small and the alloy layer 9 with high density of recombination centers is nearby, hFE is also reduced and the structure is such that parasitic transistor operation is difficult to occur.

The formation of a deep alloy layer can be achieved, for example, by increasing the temperature of the sintering process after forming the emitter electrode to a temperature higher than the conventional 430°C. If sufficient accuracy cannot be obtained by temperature control alone, sufficient accuracy can be obtained by uniformly damaging the surface within the emitter electrode formation area using a method such as plasma or ion implantation before forming the emitter electrode 23. , and good reproducibility can be obtained.

Moreover, unlike FIG. 6, when the depth of the alloy layer 9 is shallower than the emitter region 22, there is no effect of reducing the resistance value Ra compared to the conventional example, but there is an effect of reducing the hFE of the parasitic transistor. can be expected.

Note that although the central convex portion 2' is not shown in FIG. 6, it is clear that providing this convex portion 2' would provide an even greater effect. However, FIG. 6 shows that when the improvement effect of the present invention alone is sufficient for practical use, such as in particular for low voltage applications, the convex portion 2' may be removed and the drain high resistance region 1 may be increased by that amount. This is shown as an example of how the ON resistance can be improved by reducing the thickness.

As described above, in the embodiment of the present invention, the alloy layer of semiconductor material and metal is formed deeper than in the conventional case in the contact hole of the emitter electrode, so that the depth of this alloy layer is increased. If it is shallower than source region 3, the parasitic transistor
If hFE can be lowered and the depth of this alloy layer is deeper than the emitter region 22, the resistance value Ra can be lowered by reducing hFE and narrowing the effective width of the emitter region. Thereby, the secondary breakdown resistance of the IGBT can be improved.

〔Effect of the invention〕

Since the present invention is configured as described above, the thickness of the region corresponding to the center of the first conductivity type semiconductor region provided in the second conductivity type semiconductor region is approximately the same as that of the first conductivity type semiconductor region. By forming an alloy layer made of the semiconductor material of the semiconductor substrate and metal and having a thickness not exceeding the thickness of the second conductivity type semiconductor region, the base-emitter resistance value of the parasitic transistor is This has the effect of reducing hFE and improving secondary fracture resistance.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional power MOS FET.
Figure 2 is a diagram showing the output characteristics of a conventional power MOS FET, Figure 3a is a sectional view of the basic constituent unit of a power MOS FET when there is no convex portion 2' in the second conductivity type region, Figure 3b is a diagram showing the equivalent circuit of Figure 3a, Figure 4 is a circuit diagram of an inverter using power MOS FETs, and Figure 5 is a diagram showing the voltage waveform of the freewheeling diode and the current waveform flowing through the power MOS FET in Figure 4. FIG. 6 is a sectional view of an IGBT according to an embodiment of the present invention, and FIG. 7 is a sectional view of a conventional IGBT. In the figure, 2 is a second conductivity type semiconductor region, 4 is an insulating film, 5 is a gate electrode, 9 is an alloy layer, 20 is a first conductivity type semiconductor substrate, 21 is a second conductivity type semiconductor layer,
22 is a first conductivity type semiconductor region, 23 is an emitter electrode, and 24 is a collector electrode. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A semiconductor substrate having a first electrode closely connected to one main surface of the semiconductor substrate through a second conductivity type semiconductor layer, and a plurality of electrodes arranged on the other main surface of the semiconductor substrate. a first conductivity type semiconductor region disposed in a surface region of each second conductivity type semiconductor region with an opening in the center thereof; A second conductivity type semiconductor region disposed on the surface of the central portion and electrically connected to the first conductivity type semiconductor region and the second conductivity type semiconductor region.
a gate electrode disposed on the surface of the second conductivity type semiconductor region between the first conductivity type semiconductor region and the semiconductor substrate with an insulating film interposed therebetween; The semiconductor of the semiconductor substrate has a thickness that is approximately the same or more than the thickness of the first conductivity type semiconductor region and does not exceed the thickness of the second conductivity type semiconductor region, which is disposed in a region corresponding to the central portion. A conductivity modulated semiconductor device comprising: an alloy layer made of a material and a metal;