JPH0476537B2 - - Google Patents
Info
- Publication number
- JPH0476537B2 JPH0476537B2 JP60233439A JP23343985A JPH0476537B2 JP H0476537 B2 JPH0476537 B2 JP H0476537B2 JP 60233439 A JP60233439 A JP 60233439A JP 23343985 A JP23343985 A JP 23343985A JP H0476537 B2 JPH0476537 B2 JP H0476537B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- current
- output
- base
- npn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
- H03K17/615—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors in a Darlington configuration
Landscapes
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、入力信号に応じて出力トランジスタ
の導通、しや断を制御するスイツチング回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switching circuit that controls conduction and disconnection of an output transistor according to an input signal.
［従来の技術］
従来のスイツチング回路の一例を第３図に示
す。ここで、定電流源CSを制御する入力トラン
ジスタＱ１は、その入力信号Vinの大きさに応じ
て、出力トランジスタＱ２の開放を制御してい
る。今、入力信号Vinがローレベルであるとする
と、出力トランジスタＱ２は導通し、出力電流I0
が流れている。[Prior Art] An example of a conventional switching circuit is shown in FIG. Here, the input transistor Q1 that controls the constant current source CS controls the opening of the output transistor Q2 according to the magnitude of the input signal Vin. Now, assuming that the input signal Vin is at a low level, the output transistor Q2 is conductive, and the output current I 0
is flowing.
一般に、トランジスタのコレクタ電流Icが大き
くなると、第３図に示すように、コレクタ・エミ
ツタ間の飽和電圧VCE(sat)を増えていく。従つて、
第３図の回路において、出力電流I0が小さいとき
には、出力トランジスタＱ２のコレクタに現われ
る出力電圧V0は低く、トランジスタＱ３のみが
導通して、トランジスタＱ４はしや断状態にあ
る。従つて、この時の出力トランジスタＱ２のベ
ース電流IBは、定電流源CSから取り出され、ト
ランジスタＱ３より供給される電流I1だけとな
る。 Generally, as the collector current Ic of a transistor increases, as shown in FIG. 3, the saturation voltage V CE (sat) between the collector and emitter increases. Therefore,
In the circuit of FIG. 3, when the output current I 0 is small, the output voltage V 0 appearing at the collector of the output transistor Q2 is low, only the transistor Q3 is conductive, and the transistor Q4 is in a weak state. Therefore, the base current I B of the output transistor Q2 at this time is only the current I 1 taken out from the constant current source CS and supplied from the transistor Q3.
次に、出力電流I0が大きくなつてくると、トラ
ンジスタＱ２の電流増幅率には制限があるため、
ベース電流IBが定電流I1だけでは出力電流I0を流
し切れなくなつている。その時、出力電圧V0は
上昇してくるので、トランジスタＱ４が導通し、
ベース電流IBがトランジスタＱ４からも供給さ
れ、出力電流I0に対して適当なベース電流となつ
たところで出力電圧V0は一定値に落ち着く。 Next, as the output current I 0 increases, there is a limit to the current amplification factor of transistor Q2, so
The base current I B is no longer able to flow the output current I 0 with only the constant current I 1 . At that time, the output voltage V 0 increases, so transistor Q4 becomes conductive.
The base current I B is also supplied from the transistor Q4, and when the base current becomes appropriate for the output current I 0 , the output voltage V 0 settles to a constant value.
以上の動作を、出力電圧I0に対する回路の消費
電流Icc関係で示すと、第５図のようになる。す
なわち、このスイツチング回路は、出力電流が小
さい時には、無駄な消費電流を省き、出力電流が
大きくなつて行くにつれて消費電流を増やして行
こうとするものであつた。 The above operation is shown in FIG. 5 in terms of the relationship between the circuit's current consumption Icc and the output voltage I0 . That is, this switching circuit attempts to eliminate unnecessary current consumption when the output current is small, and increases the current consumption as the output current increases.
ところが、このスイツチング回路においては、
第５図に示すように、出力電流I0が増加するのに
つれて消費電流Iccも増加してしまい、したがつ
て、低消費電流化に相反するという欠点があつ
た。 However, in this switching circuit,
As shown in FIG. 5, as the output current I0 increases, the current consumption Icc also increases, which is disadvantageous in that it is contrary to the goal of lowering the current consumption.
［発明が解決しようとする問題点］
そこで、本発明の目的は、上述の欠点を除去
し、出力電流が増加しても消費電流は増加するこ
となく略々一定に保たれるように構成したスイツ
チング回路を提供することにある。[Problems to be Solved by the Invention] Therefore, it is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a system in which the current consumption does not increase and remains approximately constant even when the output current increases. The purpose of the present invention is to provide a switching circuit.
［問題点を解決するための手段］
上記目的を達成するために、本発明は、定電流
源を制御するNPNトランジスタと、NPN出力ト
ランジスタと、エミツタは該NPN出力トランジ
スタのコレクタに接続し、コレクタは該NPN出
力トランジスタのベースに接続するPNPトラン
ジスタと、ベースは前記定電流電源に接続し、エ
ミツタは前記NPN出力トランジスタのベースに
接続し、コレクタは前記PNPトランジスタのベ
ースに接続するNPNトランジスタとを具備した
ことを特徴とする。[Means for Solving the Problems] In order to achieve the above object, the present invention includes an NPN transistor that controls a constant current source, an NPN output transistor, an emitter connected to the collector of the NPN output transistor, and a collector connected to the NPN output transistor. is a PNP transistor connected to the base of the NPN output transistor, and an NPN transistor whose base is connected to the constant current power supply, whose emitter is connected to the base of the NPN output transistor, and whose collector is connected to the base of the PNP transistor. It is characterized by the following:
［作用］
本発明では、入力トランジスタと出力トランジ
スタの間にNPNトランジスタを接続して出力ト
ランジスタのベース電流を出力電流から供給させ
るように構成したので、出力電圧V0の飽和電圧
を低く抑えることができ、また低い電源電圧にも
有効に適用できる。[Function] In the present invention, since the NPN transistor is connected between the input transistor and the output transistor and the base current of the output transistor is supplied from the output current, it is possible to suppress the saturation voltage of the output voltage V 0 to a low level. It can also be effectively applied to low power supply voltages.
従つて、本発明によれば、出力電流の大きさが
変化しても消費電流は略一定に保たれ、以て出力
電流が増大しても低消費電力化を達成できる。 Therefore, according to the present invention, even if the magnitude of the output current changes, the current consumption is kept substantially constant, and therefore, even if the output current increases, low power consumption can be achieved.
［実施例］
以下、図面を参照して本発明を詳細に説明す
る。[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.
本発明の一実施例を第１図に示す。ここで、第
３図示の従来回路と同様の機能部分については同
一の記号を付してある。第１図の回路における第
３図の回路との相違点は、トランジスタＱ３およ
びＱ４を取り除き、NPNトランジスタＱ５と
NPNトランジスタＱ６を設けた点である。すな
わち、トランジスタＱ５のエミツタを出力トラン
ジスタＱ２のコレクタに、同ベースをトランジス
タＱ６のコレクタにおよび同コレクタを出力トラ
ンジスタＱ２のベースに接続し、トランジスタＱ
６のベースを入力トランジスアＱ１のコレクタ
に、同エミツタを出力トランジスタＱ２のベース
に接続する。 An embodiment of the present invention is shown in FIG. Here, functional parts similar to those of the conventional circuit shown in FIG. 3 are given the same symbols. The difference between the circuit in Figure 1 and the circuit in Figure 3 is that transistors Q3 and Q4 are removed and the NPN transistor Q5 is replaced.
The point is that an NPN transistor Q6 is provided. That is, the emitter of the transistor Q5 is connected to the collector of the output transistor Q2, the base of the transistor Q5 is connected to the collector of the transistor Q6, and the collector is connected to the base of the output transistor Q2.
6 is connected to the collector of the input transistor Q1, and its emitter is connected to the base of the output transistor Q2.
次に、第１図の回路の動作原理について説明す
る。 Next, the principle of operation of the circuit shown in FIG. 1 will be explained.
出力電流I0が小さいときには、トランジスタＱ
６のベースに定電流源CSからの定電流I1が流れ、
これにより出力トランジスタＱ２に対してベース
電流IBを供給することになる。一方、出力電流I0
が大きくなつてくると、出力トランジスタＱ２の
飽和電圧が上昇し、トランジスタＱ５が導通する
ことになる。 When the output current I 0 is small, the transistor Q
A constant current I1 from a constant current source CS flows through the base of 6,
This supplies base current I B to output transistor Q2. On the other hand, the output current I 0
As becomes larger, the saturation voltage of the output transistor Q2 increases and the transistor Q5 becomes conductive.
従つて、この第１図示のスイツチング回路にお
いては、出力電流I0が大きくなつたときには、出
力トランジスタＱ２に対するベース電流が、導通
状態のトランジスタＱ５により負荷電流I0からも
供給されるので、第２図に示すように、消費電流
Iccは略一定であり、出力電流I0の大きさに拘わ
らず一定となり、以て低消費電流化を達成でき
る。 Therefore, in the switching circuit shown in the first diagram, when the output current I 0 becomes large, the base current to the output transistor Q2 is also supplied from the load current I 0 by the conductive transistor Q5. As shown in the figure, the current consumption
Icc is approximately constant and remains constant regardless of the magnitude of the output current I0 , thereby achieving low current consumption.
［発明の効果］
以上説明したように、本発明によれば、入力ト
ランジスタと出力トランジスタの間にNPNトラ
ンジスタを接続して出力トランジスタのベース電
流を出力電流から供給させるように構成したの
で、出力電圧V0の飽和電圧を低く抑えることが
でき、また低い電源電圧にも有効に適用できる。[Effects of the Invention] As explained above, according to the present invention, since the NPN transistor is connected between the input transistor and the output transistor and the base current of the output transistor is supplied from the output current, the output voltage The saturation voltage of V 0 can be kept low, and it can also be effectively applied to low power supply voltages.
従つて、本発明によれば、出力電流の大きさが
変化しても消費電流は略一定に保たれ、以て出力
電流が増大しても低消費電力化を達成できる。 Therefore, according to the present invention, even if the magnitude of the output current changes, the current consumption is kept substantially constant, and therefore, even if the output current increases, low power consumption can be achieved.
第１図は本発明の一実施例を示す回路図、第２
図はその出力電流特性図、第３図は従来のスイツ
チング回路の一例を示す回路図、第４図はトラン
ジスタのIc−VCE(sat)特性図、第５図は従来の出力
電流特性図である。
Ｑ１……入力トランジスタ、Ｑ２……出力トラ
ンジスタ、Ｑ５……PNPトランジスタ、Ｑ６…
…NPNトランジスタ、CS……定電流源。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
Figure 3 is a circuit diagram showing an example of a conventional switching circuit, Figure 4 is a transistor Ic-V CE(sat) characteristic diagram, and Figure 5 is a conventional output current characteristic diagram. be. Q1...Input transistor, Q2...Output transistor, Q5...PNP transistor, Q6...
...NPN transistor, CS...constant current source.
Claims (1)
タに接続し、コレクタは該NPN出力トランジス
タのベースに接続するPNPトランジスタと、 ベースは前記定電流電源に接続し、エミツタは
前記NPN出力トランジスタのベースに接続し、
コレクタは前記PNPトランジスタのベースに接
続するNPNトランジスタと を具備したことを特徴とするスイツチング回路。[Claims] 1: an NPN transistor that controls a constant current source; an NPN output transistor; a PNP transistor whose emitter is connected to the collector of the NPN output transistor; and whose collector is connected to the base of the NPN output transistor; is connected to the constant current power supply, the emitter is connected to the base of the NPN output transistor,
A switching circuit characterized in that the collector comprises an NPN transistor connected to the base of the PNP transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60233439A JPS6294019A (en) | 1985-10-21 | 1985-10-21 | Switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60233439A JPS6294019A (en) | 1985-10-21 | 1985-10-21 | Switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6294019A JPS6294019A (en) | 1987-04-30 |
| JPH0476537B2 true JPH0476537B2 (en) | 1992-12-03 |
Family
ID=16955058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60233439A Granted JPS6294019A (en) | 1985-10-21 | 1985-10-21 | Switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6294019A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3123667C2 (en) * | 1981-06-15 | 1985-04-18 | Robert Bosch Gmbh, 7000 Stuttgart | Darlington transistor circuit |
-
1985
- 1985-10-21 JP JP60233439A patent/JPS6294019A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6294019A (en) | 1987-04-30 |
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