JPH0477342B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory interface circuit, and particularly to a memory interface circuit suitable for data transfer between a memory device configured with a plurality of banks and a central processing unit.

[Background of the invention]

Conventionally, there are two types of methods for configuring an interface circuit between a memory device having multiple banks and a central processing unit (CPU). The first configuration method has a control circuit corresponding to the bank of the memory device, and therefore has a request line, a request line, and a control circuit corresponding to each bank.
This configuration has an accept line and an end line.The second configuration method uses one set of control circuits, and the data transfer with the memory waits for the completion of one access before issuing the next access request. . However, in the first configuration method, since a control circuit is provided corresponding to each bank of the memory device, the amount of hardware increases, and the number of interface lines between the memory device and the memory interface circuit increases. The dot was hot. In addition, in the second configuration method, the problem with the first configuration method is solved because there is only one set of control circuits, but since memory access is serialized, the CPU and memory device are There was a problem that the data transfer throughput between the two was reduced.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and is capable of transferring data between a memory device and a CPU using a small amount of hardware and a small number of interface lines without reducing the throughput of data transfer between the memory device and the CPU. The purpose of the present invention is to provide a memory interface circuit that controls the interface of the memory interface.

[Summary of the invention]

The gist of the present invention is to include a request stack that stores a plurality of counted values of response signals from a memory device in response to one request for each request, and a counting means that counts the response signals from the memory device. The completion of the request is detected by detecting that the count value previously entered into the request stack matches the count value of the response signal from the memory device.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing a connection configuration between a CPU and a memory device according to the present invention. In the figure, a CPU 1 is connected to a memory 4 in bank 0 and a memory 5 in bank 1 via an address and write data common bus 2 and a read data bus 3. The interface between CPU1 and memory device is
It is controlled by a memory interface circuit 6 provided within the CPU 1.

FIG. 2 is a block diagram showing details of the memory interface circuit 6 provided in the CPU 1, including a request control circuit 8 that generates a control signal in response to a request signal on a memory request request line 7, and a request control circuit 8 that holds the request type. It consists of a request stack 9, an end counter 10 that counts response signals (end signals) from the memory, and a comparator 11 that compares the outputs of the request stack 9 and the end counter 10.

The types of memory access from CPU 1 are, for example, 4, 8, 12, 16 byte instruction fetch, 4,
8-byte operand fetch. Consists of 4 and 8 byte operand writes.

Furthermore, the memory 4 of bank 0 and the memory 5 of bank 1 are interleaved in units of K bytes as shown in FIG. 3, and requests are accepted in correspondence with the banks. When reading, 4 to 16 consecutive bytes of data are transferred 4 bytes at a time to the request source.
At that time, response signals are returned for the number of transfers. When writing, consecutive 4 to 8 bytes of data are written to the memory.

FIG. 4 is a diagram showing an example of the configuration of the request stack 9, and shows an example of a four-stage stack. The request stack is divided into upper and lower parts, with the upper part a storing the number of response signals (ent signals) to be returned from the memory, and the lower part b storing information indicating the destination of read data and the like.

FIG. 5 is a diagram for explaining the stack-in operation of the request stack 9, and shows as an example a case where requests for 4-byte read → 8-byte read → 16-byte read are successively performed. first 4
In the byte read request, as shown in Figure a, the number of response signals "1" and the fetch data register FDR, which is the set destination of the read data sent in synchronization with this acceptance signal, are stored. .
When an 8-byte read request comes next, the number of response signals "2" and the data set destination fetch data register FDR are stored after the previous 4-byte read request, as shown in Figure b. .
Similarly, in the case of the next 16-byte read request, the number of response signals "4" and the instruction buffer register IBR to which the data is set are stored.

FIG. 6 is a diagram for explaining stack-in and stack-out operations of the request stack 9 in FIG. 5, and a in FIG. 6 shows an initial state.
With one response signal (END) from memory,
The data transferred by the first 4-byte read is set at the transfer destination and stacked out (see b in the same figure). Similarly, with two response signals and four response signals, the data transferred by 8-byte read and 16-byte read is set at the data transfer destination and stacked out.

The operation of the interface circuit shown in FIG. 2 will be described below, taking as an example the case where an 8-byte instruction fetch and an 8-byte operand fetch are consecutive. When an 8-byte instruction fetch request for the memory 4 of bank 0 is on the request line 7, the request control circuit 8 sets the request line 16A to "1" and sets the request type line 17 to 8-byte read. When the acceptance signal line 15 becomes "1" due to the acceptance signal from the memory 4 of bank 0, the request request line 16A is set to "0" and the instruction fetch bit is set to "1" in the request stack 9.
(data set destination), count value = "2" (number of response signals), and stacking is performed via the data line 14 and the stack instruction line 13. Next, when an 8-byte operand fetch request for the memory 5 of bank 1 is input to the request control circuit 8, the request control circuit 8 sets the request request line 16B to "1" and sets the request type line 17 to 8-byte read. do. When the acceptance signal 15 becomes "1" due to the acceptance signal from the memory 5 of bank 1, the request request line 16B is set to "0" and the instruction fetch bit is set to "0" in the request stack 9.
(data set destination), count value = “2” (number of response signals), data line 14, stack instruction line 13
Stack through. Next, when the response signal line 12 becomes "1" in response to a response signal from the memory, the data on the read data bus 3 is set in a command buffer (not shown), and the end counter 10 counts the number of responses.

When the end counter 10 reaches "2", the comparator 11 matches the response signal number "2" of the request stack 9, detects that the 8-byte read of the previously input instruction is completed, and also outputs a request completion signal. 18, the request in the request stack 9 is stacked out, and the end counter 10 is reset. Subsequently, when the response signal becomes "1", the data on the read data bus 3 is set in an operand read register (not shown), and the end counter 10 counts the value of the responder, and when the count value becomes "2", Similarly to the above, the comparator 11 detects that the next 8-byte operand read has been completed, and
The request request in the request stack is stacked out by the request completion signal 18,
And the end counter 10 is reset.

FIG. 7 is a timing chart on the data bus in the operation example described above, in which the address of the 8-byte instruction fetch is transferred to the address bus 2 in the A0 cycle, the address of the 8-byte operand fetch is transferred to the address bus 2 in the A1 cycle, and the read address is transferred to the address bus 2 in the A1 cycle. Data is transferred by the read data bus 3 by 4 bytes in cycles D00 and D01 for instruction fetches and in cycles D10 and D11 for operand fetches. Response signals from the memory are output to the response signal line 12 corresponding to the above D00, D01, D10, and D11.

In this embodiment, the number of banks of the memory device is 2, and the address and data lines 2 and 3 are bus lines. However, if the number of banks of the memory device is 2 or more, and the address and data lines are independent lines. The same applies whether there is one or all are shared.

Further, a write operation is stacked on the request stack 9 when waiting for a response signal, but is not stacked on the request stack 9 when not waiting for a response signal.

〔Effect of the invention〕

As explained above, according to the present invention, without storing the bank of the request destination memory device,
Furthermore, since memory access can be performed continuously without waiting for the completion of request operations to the memory device, there is an excellent effect that data transfer throughput can be reduced with a small amount of hardware and a small number of interface lines.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the connection configuration between the CPU and memory device, Figure 2 is a block diagram showing details of the memory interface circuit 6, Figure 3 is a diagram explaining memory interleaving, and Figure 4 is a request star. 5 and 6 are diagrams showing request stack stack-in and stack-out, and FIG. 7 is a timing chart explaining the operation of FIG. 2. 1...CPU, 2...Address and write data shared bus, 3...Read data bus, 4, 5
...Memory device, 6...Interface circuit, 8
...Request control circuit, 9...Request stack, 10...End counter, 11...Comparator.

Claims (1)

[Claims] 1. In a memory interface circuit that controls an interface between a memory device composed of a plurality of banks and a central processing unit, in response to a request from the central processing unit to the memory device, request stack means for storing at least the number of response signals to be returned from the memory device for each request; and when the number of response signals from the memory device corresponding to one request reaches the stored number of response signals, A memory interface circuit comprising means for stacking out the number of response signals corresponding to the request from the stacking means.