JPH0477925B2 - - Google Patents
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- Publication number
- JPH0477925B2 JPH0477925B2 JP62045862A JP4586287A JPH0477925B2 JP H0477925 B2 JPH0477925 B2 JP H0477925B2 JP 62045862 A JP62045862 A JP 62045862A JP 4586287 A JP4586287 A JP 4586287A JP H0477925 B2 JPH0477925 B2 JP H0477925B2
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- Prior art keywords
- power
- power supply
- battery
- circuit
- electronic device
- Prior art date
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Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は、電子機器の電源回路に係わり、特に
電池で同電子機器を駆動する場合、電力消費を抑
えるため、電源スイツチオンのままで一定時間不
使用状態が続いたら、電源ラインを断つオートパ
ワーオフと称する機能を備えた同電源回路に関す
る。[Detailed Description of the Invention] (a) Industrial Application Field The present invention relates to a power supply circuit for electronic equipment, and in particular, when the electronic equipment is driven by a battery, the power supply switch remains on at a constant level in order to reduce power consumption. This power supply circuit has a function called auto power-off, which cuts off the power supply line if the power supply line is not used for a certain period of time.
(ロ) 従来の技術
一般に小型の電子機器において、駆動電源とし
て乾電池又は充電可能な２次電池としてのニツカ
ド電池が用いられ、屋内では前記乾電池の消耗を
抑えるために、また前記ニツカド電池を充電する
ため、ACアダプタにより、交流電源から整流し
た直流電圧を前記乾電池の代りに利用し、一方前
記ニツカド電池の場合は、該ニツカド電池を充電
すると共に負荷に電源を供給する所謂フローテイ
ング可能な回路構成が多用されている。(B) Prior art In general, small electronic devices use dry cells or NiCd batteries as rechargeable secondary batteries as a driving power source, and in order to suppress the consumption of the dry cells indoors, the NiCd batteries are charged. Therefore, an AC adapter uses a DC voltage rectified from an AC power source in place of the dry cell battery, while in the case of the NiCd battery, a so-called floating circuit configuration is used to charge the NiCd battery and supply power to the load. is frequently used.
更に前述の乾電池又は２次電池を使用して、負
荷を駆動しているとき、例えば電卓、電子辞書等
のように使用中にかなりの時間中断する場合、表
示素子及びそのドライブ段の回路に対する電源を
断つオートパワーオフ（以下APOと称する）と
呼ばれる電源制御回路が採用され始めた。 Furthermore, when the above-mentioned dry cell or secondary battery is used to drive a load, such as a calculator, electronic dictionary, etc., when the use is interrupted for a considerable period of time, the power supply for the display element and its drive stage circuit is A power control circuit called Auto Power Off (hereinafter referred to as APO), which cuts off power, has begun to be adopted.
この場合該電子機器内にタイマ回路を設け、負
荷の電源を断つ（オフにする）構成で、その一例
として特公昭54−37937号公報があげられ、所定
時間幅の計算機不使用状態を検出して該所定時間
幅の不使用状態が経過したとき表示器への電源の
供給を断つ制御手段の作動を電源切換手段により
外部電源使用時に強制的に不作動にする構成が示
されている。 In this case, a timer circuit is installed in the electronic device to cut off (turn off) the power to the load. An example of this is disclosed in Japanese Patent Publication No. 54-37937, which detects when the computer is not in use for a predetermined period of time. A configuration is shown in which the control means for cutting off the power supply to the display device when the predetermined period of non-use has elapsed is forcibly deactivated by the power supply switching means when an external power source is used.
(ハ) 発明が解決しようとする問題点
従来の電子機器の電源回路は、内蔵電池によつ
て前記制御回路により、所謂オートパワーオフ
（APO）を作動させて、所定時間幅の計算機不使
用状態が検出されると、表示器への電源の供給を
断つだけであり、逆に前記電池による駆動時で
も、例えば計算機、電子辞書において前記所定時
間幅が短か過ぎるという要望もある。というのは
前記APOがオンになつていると、前述の所定時
間幅を越えて更に表示内容を検討、又は読取りた
い場合に前記不使用状態の検出により、前記制御
回路が作動して電源が断たれてしまい、データを
キーインし直さなければならない欠点があつた。(c) Problems to be Solved by the Invention In the conventional power supply circuit of an electronic device, the so-called auto power off (APO) is activated by the control circuit using a built-in battery, and the computer is not used for a predetermined period of time. When detected, the power supply to the display device is simply cut off.On the other hand, there is also a demand that the predetermined time width is too short in computers and electronic dictionaries, for example, even when the display device is driven by the battery. This is because if the APO is turned on and you want to further examine or read the displayed content beyond the predetermined time period, the control circuit will be activated and the power will be cut off when the non-use condition is detected. There was a drawback that the data sagged and the data had to be re-keyed.
そこで本発明は前記欠点を除去した新規な電子
機器の電源回路を提案する。 Therefore, the present invention proposes a new power supply circuit for electronic equipment that eliminates the above-mentioned drawbacks.
(ニ) 問題点を解決するための手段
本発明は、電池又はACアダブタの出力側に接
続された直流電源ラインの電圧によつて駆動され
る複数の負荷回路と、前記直流電源ラインに直列
に接続された電源スイツチと、該電源スイツチ閉
成状態で前記負荷の一部に対して電源供給を断つ
電源制御手段を備えた電子機器の電源回路におい
て、前記電子機器の本体に対して外部からカート
リツジを結合し、該カートリツジに格納されたデ
ータに基づき前記電源制御手段における前記所定
時間を設定する構成である。(d) Means for Solving the Problems The present invention provides a plurality of load circuits driven by the voltage of a DC power line connected to the output side of a battery or an AC adapter, and a plurality of load circuits connected in series with the DC power line. In a power supply circuit of an electronic device, which includes a connected power switch and a power control means that cuts off power supply to a part of the load when the power switch is closed, a cartridge is inserted into the main body of the electronic device from the outside. and sets the predetermined time in the power supply control means based on the data stored in the cartridge.
(ホ) 作用
本発明の電子機器の電源回路では、電子機器本
体に電源制御手段を設け、ROMカード等の外部
からのカートリツジ結合により、前記電源制御手
段におけるAPOの時間設定を種々選択できるの
で、複数のカートリツジを個々に前記本体に結合
した場合、最適時間に設定できる。(e) Effect In the power supply circuit for an electronic device of the present invention, a power control means is provided in the main body of the electronic device, and various APO time settings in the power control means can be selected by coupling an external cartridge such as a ROM card. If a plurality of cartridges are individually coupled to the body, the optimal time can be set.
(ヘ) 実施例
図面に従つて本発明を説明すると、第１図は本
発明の電子機器の電源回路の構成図、第２図は同
電源回路を説明するためのフローチヤートを示
す。(F) Embodiments The present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a power supply circuit of an electronic device according to the present invention, and FIG. 2 is a flowchart for explaining the power supply circuit.
図面において、１は電子機器本体、２は電池、
３は電池用スイツチ、４は電源スイツチ、５は
ACアダプタ６接続用の電源端子、７は電源ライ
ン、８，９は各々前記電源ラインに直接接続され
た電源制御手段としてのフリツプフロツプ及び電
源検出安定回路で前記電源ラインに対する負荷と
なつている。１０はキーボード等のデータを入力
する入力部、１１は中央情報処理手段としての
CPU、１２はラツチ回路、１３は前記電子機器
本体に外部から結合されるROM等データが格納
されたカートリツジとしてのカード、１４は前記
電源検出安定回路からの出力に応じて、前記
CPU及びラツチ回路に電源を供給する電源用発
振及び出力回路、１５は前記フリツプフロツプに
よつて前記電源用発振及び出力回路の動作を制御
する電源制御を電源制御スイツチ、１６は電源検
出信号ラインを示す。 In the drawing, 1 is an electronic device body, 2 is a battery,
3 is a battery switch, 4 is a power switch, 5 is a
A power supply terminal for connecting an AC adapter 6, 7 a power line, and 8 and 9 a flip-flop and a power supply detection stabilizing circuit as power control means each directly connected to the power line and serving as a load to the power line. 10 is an input unit for inputting data such as a keyboard, and 11 is a central information processing means.
12 is a latch circuit; 13 is a card as a cartridge in which data such as ROM is coupled to the main body of the electronic device from the outside;
A power supply oscillation and output circuit supplies power to the CPU and latch circuit; 15 is a power supply control switch for controlling the operation of the power supply oscillation and output circuit by the flip-flop; 16 is a power supply detection signal line; .
次に本発明の電源回路の動作について、ACア
ダプタを使用する場合と、内部の電池を使用する
場合とについて各々説明する。 Next, the operation of the power supply circuit according to the present invention will be explained with respect to the case where an AC adapter is used and the case where an internal battery is used.
先ずACアダプタ６を電源端子５に接続した場
合について説明すると、前記接続により内部の電
池２が乾電池の如く１次電池の場合には電池用ス
イツチ３はオフにし、一方ニツカド電池の如く２
次電池の場合には前記電池用スイツチ３はオンに
保つておく。 First, we will explain the case where the AC adapter 6 is connected to the power supply terminal 5. With this connection, if the internal battery 2 is a primary battery such as a dry battery, the battery switch 3 is turned off, while the battery switch 3 is turned off when the internal battery 2 is a primary battery such as a NiCad battery.
In the case of the next battery, the battery switch 3 is kept on.
このとき電源スイツチ４をオンにしてフリツプ
フロツプ８、電源検出安定回路９に前記ACアダ
プタ６の出力が電源ライン７を通して加わる。こ
こで電源検出安定回路９は前記ACアダプタ６か
らの出力に現われるリツプル分を検出してオート
パワーオフ（APO）の機能を停止するように
CPU１１に電源検出ライン１６の信号により指
示し、前記CPU１１に設けたタイマー１７は不
動作にしておく。即ちフリツプフロツプ８のＱ出
力はロー（Ｌ）で、前記電源制御スイツチ１５は
オンの状態を保つ。 At this time, the power switch 4 is turned on and the output of the AC adapter 6 is applied to the flip-flop 8 and the power detection stabilizing circuit 9 through the power line 7. Here, the power supply detection stabilization circuit 9 detects the ripple appearing in the output from the AC adapter 6 and stops the auto power off (APO) function.
The CPU 11 is instructed by a signal on the power supply detection line 16, and the timer 17 provided in the CPU 11 is kept inactive. That is, the Q output of the flip-flop 8 is low (L), and the power supply control switch 15 remains on.
従つて電源制御スイツチ１５は、前記電源スイ
ツチ４がオンの期間はオンとなつて電源用発振及
び出力回路１４からCPU１１及び表示素子１８
等の負荷に常時電源は供給される。 Therefore, the power control switch 15 is turned on while the power switch 4 is on, and the power supply oscillation and output circuit 14 is turned on to control the CPU 11 and the display element 18.
Power is constantly supplied to loads such as
次にACアダプタ６と電子機器本体１との結合
を解いたとき、電池用スイツチ３がオンになり、
更に電源スイツチ４をオンにすると、電源ライン
７を通してフリツプフロツプ８及び電源検出安定
回路９に直流電圧が加わり、該電源ライン７にリ
ツプルが含まれないので、前記電源検出安定回路
９の検出出力が前記電源検出ライン１６の信号に
よりCPU１１に加わり、タイマー１７が作動す
る。 Next, when the AC adapter 6 and the electronic device body 1 are disconnected, the battery switch 3 is turned on.
Furthermore, when the power switch 4 is turned on, a DC voltage is applied to the flip-flop 8 and the power supply detection stabilizing circuit 9 through the power supply line 7, and since the power supply line 7 does not contain ripples, the detection output of the power supply detection stabilizing circuit 9 becomes A signal from the power supply detection line 16 is applied to the CPU 11, and a timer 17 is activated.
このとき電源用発振及び出力回路１４から前述
と同様にCPU１１及びラツチ回路１２にその出
力が加わる。 At this time, the output from the power supply oscillation and output circuit 14 is applied to the CPU 11 and latch circuit 12 in the same manner as described above.
そこで前記タイマー１７は、入力部１０からの
入力操作が停止又は中断され始めたタイミングで
カウンタを開始し、カウントダウンする。タイマ
ー時間はＴ。（分）としておくと、T0分後CPU１
１からオフ信号が出力され、ラツチ回路１２を介
してフリツプフロツプ８はセツトされ、Ｑ出力か
らAPO動作用の制御出力ハイ（Ｈ）が現われ、
電源制御スイツチ１５がオフになり、電源用発振
及び出力回路１４の作動が停止し、特に電力消費
の大きい表示素子１８がオフとなり、電池の消耗
を防ぐ。 Therefore, the timer 17 starts a counter at the timing when the input operation from the input unit 10 starts to be stopped or interrupted, and counts down. The timer time is T. (minutes), T 0 minutes later CPU1
1 outputs an off signal, the flip-flop 8 is set via the latch circuit 12, and the control output high (H) for APO operation appears from the Q output.
The power control switch 15 is turned off, the operation of the power supply oscillation and output circuit 14 is stopped, and the display element 18, which consumes particularly large amount of power, is turned off, thereby preventing battery consumption.
次に前記電池２を使用している時、前述と同様
に電源スイツチ４をオンにした状態で、前記電子
機器本体１に対し、メモリ拡張等の機能アツプ又
は電子辞書のように種々の辞書を電子化即ち
ROM化したメモリを有するカード１３を外部か
ら挿入結合したとき、前記カード１３に予め個々
にAPOのタイマー時間をＴとして前記本体にお
けるT0とは相違する時間に設定する構成となり、
前記T0を例えば５分とすると、Ｔを３分又は10
分の如く前記カード１３の内容に応じたデータに
基づき、CPU１１から読込んでタイマー１７に
前記時間Ｔを設定し、入力部１０からの入力操作
が停止又は中断したとき所定時間Ｔ後APOが作
動し、ラツチ回路１２を介してフリツプフロツプ
８にセツト出力が加わり、電源制御スイツチ１５
をオフにし、電源用発振及び出力回路１４が不動
作となり、表示素子１８への電源は断たれ、電池
の消耗は極滅される。 Next, while using the battery 2, with the power switch 4 turned on in the same way as described above, you can add functions such as memory expansion or add various dictionaries such as an electronic dictionary to the electronic device main body 1. Electronicization i.e.
When a card 13 having a ROMized memory is inserted and coupled from the outside, the APO timer time T is set individually in the card 13 to a time different from T 0 in the main body,
For example, if T 0 is 5 minutes, then T is 3 minutes or 10 minutes.
The time T is read from the CPU 11 and set in the timer 17 based on the data corresponding to the contents of the card 13, and when the input operation from the input section 10 is stopped or interrupted, the APO is activated after a predetermined time T. , the set output is applied to the flip-flop 8 via the latch circuit 12, and the power control switch 15
is turned off, the power supply oscillation and output circuit 14 becomes inoperable, the power supply to the display element 18 is cut off, and battery consumption is completely eliminated.
なお前記APOオン（作動）後は改めて電源ス
イツチ４をオフにして再びオンにすると、イニシ
ヤル状態としてタイマー１７はリセツトする構成
にしてあり、タイマー１７は再スタートする。 After the APO is turned on (activated), when the power switch 4 is turned off and then turned on again, the timer 17 is reset to the initial state, and the timer 17 is restarted.
これらをフローチヤートにまとめると、オート
パワーオフ（APO）の機能については第２図の
如く、AC（ACアダプタ６使用時）がDC（電池２
使用時）かの判定及びカード１３か本体（電子機
器本体）１から判定の各ループによりAPOのオ
ン、オフが定まり、前記電子機器本体１のみの作
動ではタイマー時間はT0、カード１３の場合は
Ｔでカード側のプログラムでAPOの設定を行う。
場合によつてはDC（電池２使用時）でも特に電子
辞書における百科辞典用のカードを利用している
ときにはAPO機能が不要にしたい要望もあり、
予めカード側のプログラムにAPOをオフにして
おくことも可能である。 To summarize these into a flowchart, as shown in Figure 2, the auto power off (APO) function changes from AC (when using AC adapter 6) to DC (when using battery 2).
The on/off state of APO is determined by each loop of judgment from the card 13 or main body (electronic device main body) 1 (when in use), and when only the electronic device main body 1 operates, the timer time is T 0 , and in the case of card 13 Set APO using the card-side program at T.
In some cases, there is a desire to eliminate the need for the APO function even with DC (when using 2 batteries), especially when using an encyclopedia card in an electronic dictionary.
It is also possible to turn off APO in the card's program in advance.
従つてAPOオンの場合APOフラグのオンに伴
い、タイマー１７内の時間カウント用のカウンタ
をデクリメント（カウントダウン）し、APOが
実行されて前述のように一部の負荷、例えば表示
素子１８等への電源が断たれる。 Therefore, when APO is on, when the APO flag is turned on, the time counter in the timer 17 is decremented (counted down), APO is executed, and as described above, some loads, such as the display element 18, etc. Power is cut off.
(ト) 発明の効果
本発明の電子機器の電源回路によれば、電子機
器本体に自動パワーオフ（APO）機能を備え、
オプシヨン機能用のROM等各種のデータを格納
したカートリツジを外部から前記電子機器本体に
結合した場合、前記カートリツジ内のデータ（プ
ログラム）に基づき、所望のタイマー時間が設定
でき、電池駆動の同電子機器にとつて本発明の使
用による効果は極めて大である。(g) Effects of the invention According to the power supply circuit for an electronic device of the present invention, the electronic device body is equipped with an automatic power off (APO) function,
When a cartridge storing various data such as ROM for optional functions is connected to the electronic device from the outside, a desired timer time can be set based on the data (program) in the cartridge, and the battery-powered electronic device The effects of using the present invention are extremely large.
第１図は本発明の電子機器の電源回路を示す回
路図、第２図は同回路のフローチヤートを示す。
１……電子機器本体、２……電池、３……電池
用スイツチ、４……電源スイツチ、５……電源端
子、６……ACアダプタ、７……電源ライン、８
……フリツプフロツプ、９……電源検出安定回
路、１１……CPU、１３……カード、１４……
発源用発振及び出力回路、１５……電源制御スイ
ツチ、１７……タイマー。
FIG. 1 is a circuit diagram showing a power supply circuit for an electronic device according to the present invention, and FIG. 2 is a flowchart of the same circuit. 1...Electronic device body, 2...Battery, 3...Battery switch, 4...Power switch, 5...Power terminal, 6...AC adapter, 7...Power line, 8
...Flip-flop, 9...Power detection stabilization circuit, 11...CPU, 13...Card, 14...
Source oscillation and output circuit, 15...power control switch, 17...timer.
Claims (1)
直流電源ラインの電圧によつて駆動される負荷回
路と、前記直流電源ラインに直列に接続された電
源スイツチと、該電源スイツチ閉成状態で前記負
荷回路の不使用時間が所定時間を越えた際に電源
供給を断つ電源制御を備えた電子機器の電源回路
において、前記電子機器の本体に対して外部から
タイマー時間が予め設定されたカートリツジを着
脱自在となし、前記電池によつて前記負荷回路を
駆動し、前記カートリツジを前記電子機器の本体
に結合時、当該カートリツジによるタイマー時間
を読み出し、前記電源制御手段に設定された所定
のタイマー時間を前記カートリツジに設定された
時間に置換えることを特徴とした電子機器の電源
回路。1 A load circuit driven by the voltage of a DC power line connected to the output side of a battery or an AC adapter, a power switch connected in series to the DC power line, and a load circuit driven by the voltage of a DC power line connected to the output side of a battery or AC adapter, a power switch connected in series to the DC power line, and a In a power supply circuit of an electronic device that is equipped with a power control that cuts off the power supply when the circuit is not used for a predetermined period of time, a cartridge with a preset timer time can be freely attached to and removed from the main body of the electronic device. When the load circuit is driven by the battery and the cartridge is connected to the main body of the electronic device, a timer time set by the cartridge is read out, and a predetermined timer time set in the power supply control means is set to the cartridge. A power supply circuit for electronic equipment that is characterized by replacing the power at a set time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62045862A JPS63211415A (en) | 1987-02-27 | 1987-02-27 | Power source circuit for electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62045862A JPS63211415A (en) | 1987-02-27 | 1987-02-27 | Power source circuit for electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63211415A JPS63211415A (en) | 1988-09-02 |
| JPH0477925B2 true JPH0477925B2 (en) | 1992-12-09 |
Family
ID=12731022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62045862A Granted JPS63211415A (en) | 1987-02-27 | 1987-02-27 | Power source circuit for electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63211415A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6957320B2 (en) | 1992-09-29 | 2005-10-18 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
| US7000097B2 (en) | 1992-09-29 | 2006-02-14 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5437937A (en) * | 1977-08-31 | 1979-03-20 | Hitachi Heating Appliance Co Ltd | High frequency heater |
| JPS58179124A (en) * | 1982-04-12 | 1983-10-20 | 日本電信電話株式会社 | No-break power supply system |
| JPH0739193B2 (en) * | 1984-05-07 | 1995-05-01 | キヤノン株式会社 | Print control method |
| JPS61256420A (en) * | 1985-05-09 | 1986-11-14 | Panafacom Ltd | Automatic power supply cut-off control system |
-
1987
- 1987-02-27 JP JP62045862A patent/JPS63211415A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6957320B2 (en) | 1992-09-29 | 2005-10-18 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
| US6965987B2 (en) | 1992-09-29 | 2005-11-15 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
| US7000097B2 (en) | 1992-09-29 | 2006-02-14 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
| US7447876B2 (en) | 1992-09-29 | 2008-11-04 | Seiko Epson Corporation | System and method for handling load and/or store operations in a superscalar microprocessor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63211415A (en) | 1988-09-02 |
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