JPH0479175B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor relay circuit in which input and output are isolated using an optical coupling method.

[Prior Art] FIG. 3 is a circuit diagram of a conventional optically coupled semiconductor relay circuit. In this circuit, a photodiode array 1 receives an optical signal emitted by a light emitting diode 6 connected between input terminals, generates a photovoltaic force, and outputs this photovoltaic force via a resistor 3. This voltage is applied between the gate and source of the MOSFET 4a. The drain and source of a control transistor 2, which is a depletion type MOSFET, are connected to the gate and source of the output MOSFET 4a, respectively.
The gate and source of are connected to both ends of the resistor 3.

When an input signal is applied to the light emitting diode 6 and a photovoltaic force is generated in the photodiode array 1, a photocurrent flows between the drain and source of the depletion type control transistor 2 and through the resistor 3, and the voltage across the resistor 3 increases. A voltage is generated. This voltage biases the transistor 2 to a high resistance state, so that the photovoltaic force of the photodiode array 1 is applied between the gate and source of the output MOSFET 4a, turning on the output MOSFET 4a.

When the input signal to the light emitting diode 6 is cut off, the photovoltaic force of the photodiode array 1 disappears, and the voltage across the resistor 3 disappears, so the depletion type control transistor 2 returns to the on state and the output Since the accumulated charge between the gate and source of MOSFET4a is discharged, the output MOSFET4a
is off.

In the circuits shown in Figures 3 and 4, an enhancement type MOSFET 4a is used as the output MOSFET 4a, and a so-called 1a type relay (the output terminals are open when no input is input, and the output terminals are open when a signal is input). The output terminals are shorted 1
output type relay) is configured.

In addition, in the circuit shown in Figure 4, an enhancement type circuit with a common gate and drain is used.
A MOSFET 5 is connected in parallel to a resistor 3 to prevent the potential difference generated across the resistor 3 from rising above a predetermined voltage (threshold voltage of the MOSFET 5).

On the other hand, in the circuit shown in Figure 5, the output
A depletion type MOSFET 4b is used, which is a so-called 1b type relay (a 1-output type relay in which the output terminals are shorted when there is no input and the output terminals are open when a signal is input).
is configured.

[Problems to be Solved by the Invention] In the case of a 1c type relay that includes both the 1a type and 1b type relays described above, conventionally, the 1a type relay and the 1b type relay were simply configured in separate circuits. , are only housed in one package, so the timing of turning from on to off is determined separately by each individual circuit. Therefore, one is turned off before the other is turned on, so-called BBM (Break Before).
It was difficult to perform the Make operation.

The present invention has been made in view of these points, and an object thereof is to provide a semiconductor relay circuit capable of BBM operation.

[Means for Solving the Problems] In the present invention, in order to solve the above problems, as shown in FIG. 1, an enhancement type first output MOSFET 4a and a depletion type second output MOSFET The first output MOSFET 4b is connected in anti-series with the first output MOSFET 4b using a common source.
The other end of the first photodiode array 1a whose one end is connected to the gate of the first photodiode array 1a is connected to the source of the first output MOSFET 4a via the first resistor 3a, and the other end of the first photodiode array 1a is connected to the source of the first output MOSFET 4a through the first resistor 3a. The other end of the second photodiode array 1b is connected to the gate of the second output MOSFET 4b via the second resistor 3b, and the drain and source are connected to the gate and source of the first output MOSFET 4a. The first depletion type with the source connected
a depletion-type second control transistor whose gate is connected to the other end of the first photodiode array 1a, and whose drain and source are connected to the source and gate of the second output MOSFET 4b; 2b is connected to the other end of the second photodiode array 1b, and the gate of the first and second photodiode arrays 1
A light emitting element 6 optically coupled to MOSFETs a and 1b is connected between the input terminals, and the drain and source of each output MOSFET 4a and 4b are connected to the output terminal.

[Function] According to the present invention, as described above, the gate of the enhancement type first output MOSFET 4a
A depletion type first control transistor 2a is connected between the sources, and a depletion type second control transistor 2a is connected between the sources.
A depletion type second control transistor 2b is connected between the gate and source of the output MOSFET 4b.
is connected to the first resistor 3a for applying an off-bias to the first control transistor 2a.
Since the configuration is such that current flows in opposite directions through the first control transistor 2a and the second control transistor 2b, the second control transistor 2a
b is made high impedance and used for the second output.
After the MOSFET 4b is turned off, the impedance of the first control transistor 2a is made high and the first output MOSFET 4a is turned on, thereby enabling BBM operation.

[Embodiment] FIG. 1 is a circuit diagram of an embodiment of the present invention. The first output MOSFET 4a is an enhancement type, and its drain and source are normally open output terminals.
Connected to O ₁ and common output terminal O ₂ . Second
The output MOSFET 4b is a depletion type, and its drain and source are normally closed output terminal O ₃
and connected to the common output terminal O ₂ . The gate of the first output MOSFET 4a is connected to the positive electrode of the first photodiode array 1a, and the source is connected to the negative electrode of the first photodiode array 1a via the first resistor 3a. Second
The source of the output MOSFET 4b is connected to the first resistor 3
a to the positive electrode of the second photodiode array 1b, and its gate is connected to the negative electrode of the second photodiode array 1b via the second resistor 3b. The first and second control transistors 2a and 2b are both depletion type.
Consists of MOSFET. The drain and source of the first control transistor 2a are for the first output.
Connected to the gate and source of MOSFET4a,
The gate is connected to the negative electrode of the first photodiode array 1a. The drain and source of the second control transistor 2b are for the second output.
Connected to the source and gate of MOSFET4b,
The gate is connected to the negative electrode of the second photodiode array 1b. A light emitting element 6, such as a light emitting diode, is optically coupled to the first and second photodiode arrays 1a, 1b, and this light emitting element 6 is connected to input terminals _I1 , _I2 .

When there is no input signal between input terminals I ₁ and I ₂ ,
Since the light emitting element 6 does not generate an optical signal, the first and second photodiode arrays 1a, 1b do not generate a photovoltaic force. Therefore, the depletion type first and second control transistors 2a and 2b
Both are not biased and have low impedance between their drains and sources. In addition, the gates of the first and second output MOSFETs 4a and 4b are
No voltage is applied between the source and drain of the enhancement type first output MOSFET4a.
High impedance exists between the sources, and low impedance exists between the drain and source of the depletion type second output MOSFET 4b.

Next, when an input signal is applied between the input terminals I ₁ and I ₂ , the light emitting element 6 generates an optical signal, and the first and second photodiode arrays 1 a and 1 b generate photovoltaic force. First photodiode array 1
The photoelectromotive force generated at a flows as a photocurrent on a path from the positive electrode of the first photodiode array 1a to the negative electrode of the first photodiode array 1a via the first control transistor 2a and the resistor 3a. . In addition, a second photodiode array 1
The photovoltaic force generated at b is emitted in a path from the positive electrode of the second photodiode array 1b to the negative electrode of the second photodiode array 1b via the resistor 3a, the second control transistor 2b, and the resistor 3b. Flows as an electric current. Therefore, since current flows in opposite directions to the resistor 3a, no current flows substantially, and the voltage across the resistor 3a does not rise. On the other hand, since current flows through the resistor 3b in only one direction, the voltage across the resistor 3b increases, biasing the second control transistor 2b to a high impedance state. Therefore, from the positive electrode of the first photodiode array 1a to the drain and source of the first control transistor 2a, to the second output transistor
The source and gate of MOSFET 4b are connected to the second photodiode array 1b via the second resistor 3b.
Current flows through the path returning to the negative terminal of the
Since the gate-source voltage of the MOSFET 4b increases, the drain-source of the second output MOSFET 4b enters a high impedance state. In addition, since the second control transistor 2b enters a high impedance state, current flows through the resistor 3a substantially only in one direction, so the voltage across the resistor 3a increases, and the first control transistor 2b becomes a high impedance state. Transistor 2a enters a high impedance state. Therefore, a current flows from the positive electrode of the first photodiode array 1b through the gate and source of the first output MOSFET 4a, the first resistor 3a, and back to the negative electrode of the first photodiode array 1a. , since the gate-source voltage of the first output MOSFET 4a increases, the first output MOSFET 4a increases.
The drain and source of the MOSFET 4a are in a low impedance state. Therefore, when an input signal is applied, the area between the normally closed output terminal O ₃ and the common output terminal O ₂ is turned off first, and then the area between the normally open output terminal O ₁ and the common output terminal O ₂ is turned on. The so-called BBM operation is realized.

FIG. 2 is a circuit diagram of another embodiment of the present invention.
In this embodiment, an enhancement type MOSFET 5a having a common gate and drain is connected in parallel to a resistor 3a, and an enhancement type MOSFET 5b having the same configuration is connected in parallel to a resistor 3b. The potential difference generated across the MOSFETs 5a and 5b is prevented from rising above a predetermined voltage (threshold voltage of MOSFETs 5a and 5b). This kind of enhancement type MOSFET
By connecting MOSFETs 5a and 5b, after the control transistors 2a and 2b enter a high impedance state, the gates of the output MOSFETs 4a and 4b are connected.
This allows the inter-source capacitance to be charged rapidly and improves the switching speed.

Note that a Zener diode may be connected in place of the MOSFETs 5a and 5b having the above configuration.

[Effects of the Invention] As described above, in the present invention, the gates of the normally open output MOSFET and the normally closed output MOSFET are biased by the outputs of the first and second photodiode arrays, respectively. Depression type first and second control transistors are connected between the sources, and a bias voltage is applied to the first resistor for off-biasing the first control transistor through the second control transistor. Since the structure is configured such that a current flows to erase the bias voltage of the first resistor, when an input signal is generated, the second control transistor is first turned off, thereby reducing the current that erases the bias voltage of the first resistor. Since the first control transistor is turned off, the normally closed output MOSFET is turned off and then the normally open output MOSFET is turned on, ensuring that BBM operation is achieved. It has the effect of

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is a circuit diagram of another embodiment of the invention, Fig. 3 is a circuit diagram of a conventional example, and Fig. 4 is a circuit diagram of another conventional example. , FIG. 5 is a circuit diagram of still another conventional example. 1a, 1b are photodiode arrays, 2a,
2b is a control transistor, 3a and 3b are resistors,
4a and 4b are output MOSFETs, 5a and 5b are
MOSFET 6 is a light emitting element.

Claims (1)

[Claims] 1 For the first output of enhancement type
For MOSFET and depletion type second output
MOSFETs are connected in reverse series with a common source, and one end of the photodiode array is connected to the gate of the first output MOSFET, and the other end is connected to the first output MOSFET through a first resistor. the other end of the second photodiode array, which has one end connected to the other end of the first photodiode array, is connected to the source of the first photodiode array for a second output via a second resistor.
Connected to the gate of MOSFET for the first output
The gate of a depletion type first control transistor whose drain and source are connected to the gate and source of the MOSFET is connected to the other end of the first photodiode array, and the second output transistor is connected to the other end of the first photodiode array.
The gate of a depletion-type second control transistor whose drain and source are connected to the source and gate of the MOSFET is connected to the other end of the second photodiode array, and light is transmitted to the first and second photodiode arrays. 1. A semiconductor relay circuit comprising: coupled light emitting elements connected between input terminals; drain and source of each output MOSFET connected to an output terminal.