JPH0480534B2 - - Google Patents
Info
- Publication number
- JPH0480534B2 JPH0480534B2 JP58047949A JP4794983A JPH0480534B2 JP H0480534 B2 JPH0480534 B2 JP H0480534B2 JP 58047949 A JP58047949 A JP 58047949A JP 4794983 A JP4794983 A JP 4794983A JP H0480534 B2 JPH0480534 B2 JP H0480534B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- wiring
- power
- lsi
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
Landscapes
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
発明の技術分野
本発明は、半導体装置に関し、特に大規模集積
回路（LSI）の電源配線の配置に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to the arrangement of power supply wiring in a large-scale integrated circuit (LSI).
技術の背景
近年、LSIの回路が大規模化するに従つて、一
チツプ当りの消費電力が増大する場合がある。こ
のとき、LSIの電源配線においては電流密度が大
きくなり、また電流分布の不均一により供給電圧
に差が生じるおそれがある。例えば、ECL形の
ゲートアレイLSIを例にとると従来第１図に示さ
れるような電源の配置が行われている。第１図に
おいて、VCCは電源の高電位側であり、VEEは低
電位側である。このような配置においては、給電
端子からの位置によりLSI内部において電源電圧
に差が生じることになる。Background of the Technology In recent years, as LSI circuits have become larger in scale, the power consumption per chip may increase. At this time, the current density increases in the power supply wiring of the LSI, and there is a possibility that a difference may occur in the supply voltage due to non-uniform current distribution. For example, if we take an ECL type gate array LSI as an example, the power supply is conventionally arranged as shown in FIG. In FIG. 1, V CC is the high potential side of the power supply and V EE is the low potential side. In such an arrangement, a difference occurs in the power supply voltage inside the LSI depending on the position from the power supply terminal.
発明の目的
本発明の目的は、消費電力が増大したLSIにお
いて電源端子の配置を工夫することにより、電源
配線の電流密度を低下させ、LSI内部の電源電圧
の差を少なくすることにある。Purpose of the Invention An object of the present invention is to reduce the current density of the power supply wiring and reduce the difference in power supply voltage inside the LSI by devising the arrangement of power supply terminals in an LSI with increased power consumption.
発明の構成
本発明においては、半導体チツプ周辺に設けら
れた電源供給パツドと、内部回路群を包囲する様
に配置された電源配線と、該電源配線から該内部
回路群に動作電圧を供給するための枝配線とを備
え、該電源供給パツドが該電源配線にほぼ等間隔
に複数個接続され、各電源供給パツド当りの電流
分担が均等化されるように構成されていることを
特徴とする半導体装置が提供される。Structure of the Invention The present invention includes a power supply pad provided around a semiconductor chip, a power supply wiring arranged to surround an internal circuit group, and a circuit for supplying an operating voltage from the power supply wiring to the internal circuit group. branch wiring, and a plurality of the power supply pads are connected to the power supply wiring at approximately equal intervals, and the semiconductor is configured such that the current share for each power supply pad is equalized. Equipment is provided.
発明の実施例
本発明の一実施例としてのLSIの電源配置方法
が第２図に示される。第２図には、LSIの一つの
チツプの平面図を示す。第１図のLSIチツプにお
いては、高電位側電源線VCCと低電位側電源線
VEEが２層の配線層内に配置される。上部の配線
層が実線で示され、下部の配線層は破線で示され
る。VCC電源は、チツプの周辺に設けられたVCC
電源パツド１から供電され、チツプの周辺部分に
おいて上部配線層内に設けられたVCC電源主配線
２および、チツプ内部に平行に配置されたVCC電
源枝配線３により、内部回路（図示せず）に供給
される。また、VEE電源は、同様にチツプ周辺に
設けられたVEE電源パツド４から供電され、下部
配線層内および上部配線層内に設けられたVEE電
源主配線５，６，７、および、チツプ内部に平行
に配置されたVEE電源枝配線８により、内部回路
に供給される。Embodiment of the Invention A method for arranging power supplies in an LSI as an embodiment of the present invention is shown in FIG. Figure 2 shows a plan view of one LSI chip. In the LSI chip shown in Figure 1, the high potential side power line V CC and the low potential side power line
V EE is arranged within two wiring layers. The upper wiring layer is shown with a solid line, and the lower wiring layer is shown with a broken line. The V CC power supply is the V CC power supply provided around the chip.
Power is supplied from the power supply pad 1, and the internal circuit (not shown) is connected to the V CC power supply main wiring 2, which is provided in the upper wiring layer in the peripheral area of the chip, and the V CC power supply branch wiring 3, which is arranged in parallel inside the chip. ). Further, the V EE power supply is similarly supplied from the V EE power supply pad 4 provided around the chip, and the V EE power supply main wirings 5, 6, 7 provided in the lower wiring layer and the upper wiring layer, and The V EE power supply branch wiring 8 arranged in parallel inside the chip supplies power to the internal circuits.
第２図に示されるように、本発明によるLSIの
電源配置においては、VCC電源およびVEE電源の
電源パツド（端子）は、チツプの周辺にほぼ等間
隔に配置される。従つて、電源配線の電流密度が
平均化され、それにより全体として電流密度が減
少され、チツプ内での電源電圧の差が小さくな
る。また、それにより、電源配線の幅を細くする
ことができ、チツプの面積を小さくすることが可
能になる。 As shown in FIG. 2, in the LSI power supply arrangement according to the present invention, the power supply pads (terminals) of the V CC power supply and the V EE power supply are arranged at approximately equal intervals around the periphery of the chip. Therefore, the current density of the power supply wiring is averaged, thereby reducing the current density as a whole and reducing the difference in power supply voltage within the chip. Furthermore, this allows the width of the power supply wiring to be made narrower, thereby making it possible to reduce the area of the chip.
発明の効果
本発明によれば、消費電力の増大したLSIにお
いて、電源配線内の電流密度を低下させることが
でき、チツプ内での電源電圧の差を小さくするこ
とができる。Effects of the Invention According to the present invention, in an LSI with increased power consumption, the current density in the power supply wiring can be lowered, and the difference in power supply voltage within the chip can be reduced.
第１図は、従来の電源配線の配置を用いたLSI
の平面図、第２図は、本発明による電源配線の配
置を用いたLSIの平面図である。
（符号の説明）、１：VCC電源パツド、２：VCC
電源主配線、３：VCC電源枝配線、４：VEE電源
パツド、５，６，７：VEE電源主配線、８：VEE
電源枝配線。
Figure 1 shows an LSI using the conventional power supply wiring layout.
FIG. 2 is a plan view of an LSI using the power supply wiring arrangement according to the present invention. (Explanation of symbols), 1: V CC power supply pad, 2: V CC
Main power wiring, 3: V CC power supply branch wiring, 4: V EE power pad, 5, 6, 7: V EE main power wiring, 8: V EE
Power branch wiring.
Claims (1)
れぞれ同一の電位を供給する複数の電源供給パツ
ドと、内部回路群を包囲する様に配置された電源
配線と、該電源配線から該内部回路群に動作電圧
を供給するための枝配線とを備え、 ４辺に設けられた複数の該電源供給パツドが、
該電源配線のそれぞれの辺に対してほぼ等間隔に
複数個接続され、各電源供給パツド当たりの電流
分担が均等化される様に構成されており、該電源
供給パツドは該電源配線に対し、該電源配線の各
辺の中心点に関してほぼ左右対称の位置に接続さ
れてなることを特徴とする半導体装置。[Scope of Claims] 1. A plurality of power supply pads provided on each of the four sides of a semiconductor chip and supplying the same potential, a power supply wiring arranged so as to surround an internal circuit group, and a plurality of power supply pads provided on each of the four sides of a semiconductor chip, and a power supply wiring arranged to surround an internal circuit group, and and branch wiring for supplying operating voltage to the internal circuit group, and the plurality of power supply pads provided on four sides,
A plurality of pads are connected to each side of the power wiring at approximately equal intervals, and the power supply pads are configured to equalize the current share for each power supply pad. A semiconductor device characterized in that the power supply wiring is connected at substantially symmetrical positions with respect to the center point of each side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58047949A JPS59175148A (en) | 1983-03-24 | 1983-03-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58047949A JPS59175148A (en) | 1983-03-24 | 1983-03-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59175148A JPS59175148A (en) | 1984-10-03 |
| JPH0480534B2 true JPH0480534B2 (en) | 1992-12-18 |
Family
ID=12789609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58047949A Granted JPS59175148A (en) | 1983-03-24 | 1983-03-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59175148A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5165086A (en) * | 1985-02-20 | 1992-11-17 | Hitachi, Ltd. | Microprocessor chip using two-level metal lines technology |
| US5280450A (en) * | 1990-05-14 | 1994-01-18 | Hitachi, Ltd. | High-speed semicondustor memory integrated circuit arrangement having power and signal lines with reduced resistance |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420680A (en) * | 1977-07-18 | 1979-02-16 | Hitachi Ltd | Large scale integrated circuit |
-
1983
- 1983-03-24 JP JP58047949A patent/JPS59175148A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59175148A (en) | 1984-10-03 |
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