JPH0480637B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital field pole position detection device, and more particularly to a digital field pole position detection device that digitally detects the position of a field pole of a synchronous motor. .

[Conventional technology]

When a current is passed through the armature of a synchronous motor, a field φa is generated due to the armature's reaction. armature current
Ia, the field is φ, the phase difference between the field φ and the field φa is r,
If the induced electromotive force is Eemf, and the phase difference between the induced electromotive force Eemf and the armature current Ia is ψ, then the generated torque τ is: τ=K・φ・Ia・cos(ψ) ψ+r=90° …(1) , τ=K1・φ・Ia・sin(r)...(2) However, K1 is expressed as a proportionality constant.

Conventionally, vector control of a synchronous motor detects the position of the field pole using a field pole position detector, generates a sinusoidal current command with a phase synchronized with the field pole, and controls the current amplitude with this current command to generate torque. This is done through control.

In other words, vector control of a synchronous motor detects the position of the field pole, matches the phase of armature current Ia with the phase of induced electromotive force Eemf, and sets ψ=0° in equation (1) above. . Therefore, if φ is constant, the generated torque τ′ of a vector-controlled synchronous motor is: τ′=K1・φ・Ia・sin(r) =K2・Ia …(3) However, K2 is proportional Since it is expressed as a constant, the generated torque τ′ is equal to the armature current
Proportional to Ia. Furthermore, the field φa due to the reaction of the armature does not act on the field φ and does not cause mutual interference, so the generated torque τ' also becomes maximum.

Note that the field pole position detector requires a resolver with the same number of poles as that of the synchronous motor.

[Problem to be solved by the invention]

However, in the conventional field pole position detector described above, the signal processing circuit of the resolver is composed of an analog circuit, so the detection signal of the field pole position detector is distorted due to the influence of temperature drift and offset. As a result, waveform distortion also occurs in the current command, causing torque ripple, and there is a problem that highly accurate vector control cannot be performed.

Furthermore, since the number of poles of the resolver and the number of poles of the synchronous motor must match, there is a problem in that many types of resolvers must be used depending on the type of number of poles of the synchronous motor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital field pole position detection device that can improve the accuracy of vector control and reduce the number of resolver types.

[Means to solve the problem]

The digital field pole position detection device of the present invention includes a two-pole resolver that detects the position of a field pole of a synchronous motor, and a pulse signal that generates a pulse signal having a pulse width proportional to the phase difference between the excitation voltage of the resolver and the detected voltage. a clock pulse generating means for generating a clock pulse; a gate means for performing a logical product of the pulse signal and the clock pulse to generate a clock having a number of clock pulses proportional to the pulse width of the pulse signal; a sine wave waveform that outputs a sine wave waveform signal with a period corresponding to the number of field poles of the synchronous motor when the count number of the counting means increases by one; generating means.

Here, the clock pulse generating means is a variable clock pulse generating means for generating a clock pulse having a period corresponding to the number of field poles of the synchronous motor, and the sine wave waveform generating means is addressed by the output signal of the counting means. The memory may include a memory in which one cycle of a sine wave waveform signal having a predetermined cycle is stored, and a digital-to-analog conversion means for converting the output signal of the memory into an analog signal.

Further, the clock pulse generating means is a fixed clock pulse generating means for generating a clock pulse of a predetermined cycle, and the sine wave waveform generating means is a field pole number of the synchronous motor that is addressed by the output signal of the counting means. It may include a memory in which a plurality of sine wave waveform signals each having a cycle corresponding to the period are stored, and a digital-to-analog conversion means for converting the output signal of the memory into an analog signal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1a and 1b are diagrams for explaining vector control of a synchronous motor using an embodiment of the digital field pole position detection device of the present invention, respectively.

An inverter 10 is placed between the synchronous motor 11 and the power source. A two-pole resolver 12 connected to the synchronous motor 11 is excited by a resolver excitation circuit 15 . The first multiplier 16a receives a β-phase signal from a signal processing circuit 14 (described later) and a torque command signal t0 from a torque command signal output device (not shown).
, and outputs the first armature command signal S1. Further, the second multiplier 16b multiplies the α-phase signal from the signal processing circuit 14 by the torque command signal t0, and outputs the second armature command signal S2. The current control circuit 17 inputs the first and second armature command signals S1 and S2, respectively, and
Outputs phase armature current command signal. Pulse width modulation and drive circuit (PWM and base driver) 18
inputs the three-phase armature current command signals, respectively, and outputs a drive signal group to the inverter 10.

FIG. 1b shows the induced electromotive force Eemf for one phase of the synchronous motor 11 and the detection signal of the resolver 12.
It is a graph showing the phase relationship between the armature current reference signal waveform (θ phase) corresponding to the rotor position of the synchronous motor 11 and the first armature command signal S1.

The amplitude of the first armature command signal S1 changes according to the torque command signal t0, as shown in FIG. Second armature command signal S2
The same is true.

The resolver position detection circuit 13 and the signal processing circuit 14 constitute a digital field pole position detection device 20 according to the present invention.

As shown in FIG. 2, the resolver position detection circuit 13 includes a first waveform shaping circuit W that converts one excitation voltage Vα of the resolver 12 into a first rectangular wave Sα.
1, a second waveform shaping circuit W2 that converts the detected voltage Vθ of the resolver 12 into a second rectangular wave Sθ, the first rectangular wave Sα is input to the latch input terminal, and the second rectangular wave Sθ is cleared. input to the input terminal,
It consists of one latch circuit LA1 that generates a pulse signal Pθ having a pulse width proportional to the phase difference θ between the excitation voltage Vα and the detection voltage Vθ. Here, the phase difference θ
When the resolver 12 has two poles, the angle corresponds to the mechanical angle.

The signal processing circuit 14 includes a clock pulse generator CPA that generates a clock pulse CP with a period corresponding to the number of field poles of the synchronous motor 11, and a pulse signal Pθ.
A gate circuit GT that takes the AND of the clock pulses CP and CP and generates a clock sg with a number of clock pulses proportional to the pulse width of the pulse signal Pθ.
, a counter circuit CT that counts the number of clock pulses of the clock sg, a second latch circuit LA2 that holds the output signal d1 of the counter circuit CT, and an output signal d2 of the second latch circuit LA2 (i.e.,
A memory ME in which one cycle of a sine wave waveform signal with a predetermined cycle is stored, which is addressed by the output signal d1) of the counter circuit CT;
It consists of a D/A (digital-to-analog converter) DA that converts the ME output signal d3 into an analog signal.

Here, the counter circuit CT clocks sg every time the excitation voltage Vα of the resolver 12 crosses zero.
Count the number of clock pulses. Also, the second
The second rectangular wave output from the waveform shaping circuit W2 of
Sθ is input to the clear terminal via the inverter circuit IN, and the counter circuit CT is initialized every time the detection voltage Vθ of the resolver 12 crosses zero. Also, the second latch circuit LA
2 is for synchronizing the timing of reading data from the memory ME, and the output signal d2 of the second latch circuit LA2 is used for addressing the memory ME.

Next, the operations of the resolver position detection circuit 13 and the signal processing circuit 14 will be explained with reference to FIGS. 3 and 4.

The excitation voltage Vα and the detection voltage Vθ of the resolver 12 are converted into first and second rectangular waves Sα and Sθ by first and second waveform shaping circuits W1 and W2, respectively (see a to d in the figure). First latch circuit LA
1 is latched at the rising edge of the first rectangular wave Sα,
Since it is cleared by the second rectangular wave Sθ, a pulse signal Pθ having a pulse width proportional to the phase difference θ between the excitation voltage Vα of the resolver 12 and the detection voltage Vθ is output from the first latch circuit LA1 (the same Figure e). Therefore, by calculating the AND of the pulse signal Pθ and the clock pulse CP using the gate circuit GT, a clock sg having a number of clock pulses proportional to the pulse width (phase difference θ) of the pulse signal Pθ can be obtained (see f in the same figure). ). Since the counter circuit CT counts the number of clock pulses of the clock sg after being cleared at the fall of the second rectangular wave Sθ, its counting state becomes as shown in g in the figure. The output signal d1 of the counter circuit CT is held in the second latch circuit LA2 at the rise of the second rectangular wave Sθ (h in the figure). The sine wave waveform signal stored in the memory ME is read out at the timing of a read permission signal RE (i in the figure) generated from the first rectangular wave Sα by a necessary circuit (not shown).

Here, the excitation frequency of the resolver 12 is 2.5KHz,
Set the clock frequency of clock pulse CP to 2.56MHz
and the counter circuit CT and the second latch circuit
Let the number of bits of LA2 be 10 bits each. Now, the excitation voltage Vα of the resolver 12 and (0.400ms=
1/2.5KHz), the pulse width of pulse signal Pθ is 0.400ms, so the number of clock pulses of clock sg is "1023" (=2.56MHz/2.5Hz).
becomes. At this time, the count number of the counter circuit CT also becomes "1023". In other words, if the phase difference θ is from 0°
When the angle changes to 360°, the count number of the counter circuit CT also changes from "0" to "1023" as shown by the straight line in Figure 4b, so a one-period sine wave as shown by the curve in Figure 4c By dividing the waveform signal into 1024 parts and storing them in each address of the memory ME, the output signal d1 of the counter circuit CT
If you specify an address and read data from the memory ME, you can obtain a one-cycle sine wave waveform signal.

Furthermore, by doubling the clock frequency of the clock pulse CP to 5.12MHz, when the phase difference θ changes from 0° to 360°, the counter circuit CT changes from “0” to 360°, as shown by the straight line in Figure 4b. “1023”
In order to count up to 2 times, the counter circuit CT
The address is specified using the output signal d1 of the memory ME.
If data is read out from , a two-cycle sine wave waveform signal can be obtained, as shown by the curve c in the same figure. Therefore, in this case, it can be made compatible with a four-pole synchronous motor.

Furthermore, by increasing the clock frequency of the clock pulse CP to 7.68MHz, the phase difference θ
When the angle changes from 0° to 360°, the counter circuit CT counts from “0” to “1023” three times as shown by the broken line in Figure 4b, so the address is specified by the output signal d1 of the counter circuit CT. By reading the data from the memory ME, it is possible to obtain a three-cycle sine wave waveform signal, as shown by the broken line in FIG. Therefore, in this case, 6
It can be made compatible with pole synchronous motors.

Similarly, by increasing the clock frequency of the clock pulse CP by N times, a sine wave waveform signal with N periods can be obtained. Therefore, it can be applied to a synchronous motor with any number of poles.

Digital field pole position detection device 2 explained above
0, a clock pulse generator CPA (variable clock pulse generator) that generates a clock pulse CP with a period corresponding to the number of field poles of the synchronous motor 11;
A sine wave waveform signal with a period corresponding to the number of field poles of the synchronous motor 11 was obtained using the memory ME in which one cycle of a sine wave waveform signal with a predetermined period was stored. However, instead of the clock pulse generator CPA, a fixed clock pulse generator that generates clock pulses CP' of a predetermined period is used, and instead of the memory ME, a synchronous motor is used which is addressed by the output signal d1 of the counter circuit CT. 1
Even if a memory ME′ in which a plurality of sine wave waveform signals with a period corresponding to the number of field poles of 1 is stored for one period each, a sine wave with a period corresponding to the number of field poles of the synchronous motor 11 is used. A waveform signal can be obtained.

That is, in the memory ME', the curve ~
The waveform signals of one cycle of sine waves shown by the curves are stored respectively, and when the number of field poles of the synchronous motor 11 is 2, the waveform signals shown by the curves are stored according to the output signal d2 of the second latch circuit LA2. A sine wave waveform signal is output from memory ME', and the synchronous motor 1
When the number of field poles of synchronous motor 11 is 4 poles, a sine wave waveform signal shown by a curve is output from memory ME', and when the number of field poles of synchronous motor 11 is 6 poles, a sine wave waveform signal shown by a curve is output. the memory
By outputting from ME', the count number of the clock sg counter circuit CT generated using the clock pulse CP' of a predetermined period can be changed from "0" to "1023".
Synchronous motor 1
A sine wave waveform signal with a period corresponding to one field pole number can be obtained.

Furthermore, the phase angle error due to speed may be preset in the counter circuit CT by software processing.

〔Effect of the invention〕

Since the present invention is configured as described above,
The following effects are achieved.

In vector control of synchronous motors, digital field pole position detection is possible, and the controller can be digitalized using a microcomputer, resulting in highly accurate vector control of synchronous motors.

Furthermore, since the field pole position of a multi-pole synchronous motor can be detected using a two-pole resolver, it is only necessary to prepare one model of two-pole resolver as a position detector. A resolver with a number of poles becomes unnecessary.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining vector control of a synchronous motor using an embodiment of the digital field pole position detection device of the present invention, in which a is a schematic block diagram of the entire system, and b is an induced electromotive force Eemf. , armature current reference signal waveform Sθ, and first armature command signal S
It is a graph showing the phase relationship with the first or second armature command signal S2. FIG. 2 is a schematic block diagram showing an example of the configuration of the digital field pole position detection device shown in FIG. 1. FIG. 3 is a timing chart for explaining the operation of the digital field pole position detection device shown in FIG. 2, and FIG. 4 is a timing chart for explaining the specific operation of the signal processing circuit shown in FIG. 2. , where a is a schematic block diagram, b is a graph showing the relationship between the counter output and the resolver phase difference, and c is a graph showing the relationship between the D/A output waveform signal and the resolver phase difference. . 10...Inverter, 11...Synchronous motor, 1
2... Resolver, 13... Resolver position detection circuit, 14... Signal processing circuit, 15... Resolver excitation circuit, 16a... First multiplier, 16b... Second multiplier, 17... Current control Circuit, 18... Pulse width modulation and drive circuit (PWM and base driver), 20... Digital field pole position detection device,
W1...first waveform shaping circuit, W2...second waveform shaping circuit, LA1...first latch circuit, CPA
...Clock pulse generator, GT...gate circuit, CT...counter circuit, LA2...second latch circuit, ME...memory, DA...D/A (digital-to-analog converter), IN...inverter circuit ,
t0... Torque command signal, S1... First armature command signal, S2... Second armature command signal,
Eemf...Induced electromotive force, Vα...Exciting voltage, Vθ...
...detection voltage, Sα...first rectangular wave, Sθ...second
rectangular wave, θ...phase difference, Sθ...pulse signal,
CP...clock pulse, sg...clock, d1,
d2...Output signal.

Claims (1)

[Claims] 1. A two-pole resolver 12 that detects the position of a field pole of a synchronous motor, and a pulse signal having a pulse width proportional to the phase difference θ between the excitation voltage Vα of the resolver 12 and the detection voltage Vθ.
Pulse generating means W1, W2, LA1 that generates Pθ
, a clock pulse generating means CPA that generates a clock pulse CP, and the pulse signal Pθ and the clock pulse.
gate means GT for calculating the AND of CP and generating a clock sg having a number of clock pulses proportional to the pulse width of the pulse signal Pθ; a counting means CT for counting the number of clock pulses of the clock sg; and a sine wave waveform generating means for outputting a sine wave waveform signal having a period corresponding to the number of field poles of the synchronous motor when the count number increases by one. 2. The clock pulse generating means CPA is a variable clock pulse generating means that generates a clock pulse with a period corresponding to the number of field poles of the synchronous motor, and the sine wave waveform generating means is a variable clock pulse generating means that generates a clock pulse having a period corresponding to the number of field poles of the synchronous motor, and the sine wave waveform generating means
Addressed by the output signal d1 of the CT,
Claim 1 includes a memory ME in which one cycle of a sine wave waveform signal with a predetermined cycle is stored, and digital-to-analog conversion means DA for converting the output signal d3 of the memory ME into an analog signal. Digital field pole position detection device. 3. The clock pulse generating means CPA is a fixed clock pulse generating means that generates a clock pulse of a predetermined period, and the sine wave waveform generating means is a fixed clock pulse generating means that generates a clock pulse of a predetermined period, and the sine wave waveform generating means is a fixed clock pulse generating means that generates a clock pulse of a predetermined period.
addressed by the output signal d1 of CP,
It includes a memory in which one cycle of a plurality of sine wave waveform signals each having a period corresponding to the number of field poles of the synchronous motor is stored, and a digital-to-analog conversion means for converting the output signal of the memory into an analog signal. A digital field pole position detection device according to claim 1.