JPH0481221B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a channel device that controls access to main storage devices of multiple channels and data transfer between channels and main storage devices, memory access requests from channels, memory addresses, stores, etc. A channel control device characterized in that data, a completion report from a main storage device, and load data are in a stack structure, and the next memory access request is issued without confirming the completion of memory access. According to
Throughput can be significantly improved.

[Industrial Application Field] The present invention relates to memory access to a main storage device (hereinafter abbreviated as memory) of a channel control device.

[Prior Art] A channel control device receives requests for access to a main memory device from a plurality of channels one by one, and accesses the memory and transfers data.

FIG. 5 is a time chart showing an example of a memory interface, in which FIG. 5a shows the operation at the time of "store" and FIG. 5b shows the operation at the time of "load".

In FIG. 5, RQ is a memory access request signal from the channel control device, and STR is the access type; "1" indicates "store" and "0" indicates "load."

ACK is a permission signal from the memory, and the channel controller continues to raise the RQ signal until it receives the ACK signal.

When the channel control device receives the ACK signal, it puts the address and store data on the memory bus when it is a "store", and only the address when it "loads". In the example shown in the figure, the data width of the memory bus is half the data width of the memory, and the store data is divided into two transfers: upper data U and lower data L.

END is the end signal for accessing from memory, and when "loading", the load data is placed on the memory bus.

The period from the ACK signal to the END signal is a memory access time, during which time other channel control devices are kept waiting.

The memory can recognize the next memory access request by the RQ shown by the broken line in FIGS. 4a and 4b, and the response to this is the ACK shown by the broken line.

FIG. 6 is a block diagram showing a conventional example of a channel control device.

In Figure 6, MAR is an address register,
SDR is a store data register and LDR is a load data register.

Conventionally, in order to prevent the contents of the address register (MAR), store data register (SDR), and load data register (LDR) from being overwritten, there was a
Responses and confirmations were performed both between the channel control device and the channel.

Therefore, the channel control device can accept a memory access request from the next channel only when the termination control of the previous access request is completed.

[Problems to be Solved by the Invention] As explained above, in the past, both the communication between the memory and the channel control device and between the channel control device and the channel were carried out by response/confirmation, so the control circuit required a large amount of space. In addition, there was a problem that there was a gap between the next memory access and the RQ could not be issued at the timing shown by the broken line in FIG.

The present invention aims to provide a novel channel control device that solves these problems.

[Means for Solving the Problems] FIG. 1 shows a principle block diagram of a channel control device according to the present invention.

In FIG. 1, 1 is an access request stack that stores access request data from a channel on a first-come, first-served basis, 2 is an address stack that stores a memory address sent together with access request data from a channel, and 3 is an access This is a store data stack that stores store data sent from a channel when the type is store.

4 is an end report stack that stores end reports (END) sent from the memory in the order in which they are received, and 5, when the access type is load, stores the load data that the memory places on the memory bus together with the end report in the order in which they are received. Load data stack.

Each stack 1, 2, 3, 4, 5 is a first-in, first-out stack.

When a memory access request is received from a channel, the access request data, the memory address, and, if the access type is store, the store data are stacked in stacks 1, 2, and 3, respectively, on a first-come, first-served basis.

The access request data includes data such as the access type and the channel number that issued the access request.

These stacked access requests are
It is controlled by the control circuit 6, and sends the RQ signal and STR signal to the memory from the first one in the stack 1.

The ACK signal from the memory is input to the RQ control circuit 6, which outputs the memory address of the first-arriving one in stack 2 to the memory bus. If the access type is store, the first-arriving store data from stack 3 is output to the memory bus. Output to bus. At the same time, stacks 1, 2, and 3 are shifted by one.

When the end report (END) from memory arrives,
Under the control of the END control circuit 7, the end report stack 4 is stacked with the channel number, and if the access type is load, the load data on the memory bus is stacked into the load data stack 5.

The data stacked in stacks 4 and 5 are sequentially sent to predetermined channels.

[Function] As explained above, in the channel control device, the memory access request, memory address, and store data from each channel are controlled by the RQ control circuit as a stack structure, and the completion report and load data from the memory are controlled by the RQ control circuit. are also controlled by the END control circuit as a stack structure, so that they operate independently, and the completion report is not a condition for starting the next memory access.

As a result, the channel control device is expected to have a significant throughput improvement, and the logic of the control circuit is also very simple.

[Example] The present invention will be described in more detail below with reference to Examples shown in FIGS. 2 to 4.

FIG. 2 shows a block diagram of an embodiment of the invention,
FIG. 3 shows an embodiment of an RQ control circuit and an END control circuit according to the invention, and FIG. 4 shows an embodiment of a stack circuit according to the invention.

In FIG. 2, 1 (MABU) is a stack that stores control information, and 2 (MABL) is a stack that stores memory addresses. The control information includes store/load information, channel address, and other information indicating the type of access (for example, the number of words transferred by burst transfer).

A memory access request from a channel is sent to MABU as a pair of control information and memory address.
They are stacked in MABL on a first-come, first-served basis, and at that time the V bit of the validity indicator is set to "on".

31 (SDBU) and 32 (SDBL) are store data stacks, and when the access type is store, upper and lower store data are stacked, respectively.

The memory access reception circuit from this channel is very simple because it only needs to concentrate on stack operations and does not need to be aware of the response on the memory side as in the conventional case.

MABU1, MABL2, SDBU31, SDBL3
The access requests stacked in number 2 are sent to the memory by the RQ control circuit shown in FIG.

Immediately, the “ON” of the V bit of MABU1 is AND
It becomes an RQ signal through gate 61, and the output of MABU1 is set in register 62, and a part of it is
It becomes an STR signal.

The ACK signal from the memory is sequentially shifted to D-type flip-flops 63-1, 63-2, and 63-3, whose outputs are sent to the stacks MABU1 and MABU1, respectively.
This is a +1 condition for the read pointer (RP) of MABL2, SDBU31, and SDBL32.

Therefore, upon receipt of ACK from the memory, a memory address is sent to the memory bus, one clock later the upper part of the store data is sent out, and one clock later the lower part of the store data is sent out.

However, the STR bit of register 62 is “off”.
In this case, the AND gates 65-1 and 65-2 do not open, and the stacks SDBU and SDBL are not incremented by +1.

The V bits of stack MABU1 and MABL2 are turned off by the output of flip-flop 63-1.
The outputs of the flip-flops 63-1 to 63-3 pass through a NOR gate 64 to an AND gate 61.
In addition, as an "off" condition for the RQ signal, it suppresses the interference noise that occurs when the read pointer of the stack MABU is +1, stops the clock of the register 62, and suppresses the update of control information.

Flip-flop 63-1, 63-2, 63-
3 are both "off", that is, 3 clocks after the ACK signal, the V bit of the next word of the stack MABU becomes the RQ signal, and the register 62
information is also updated and waits for ACK from memory.
In this way, the RQ control circuit is dedicated to transferring information to memory.

The output of flip-flop 63-3 is used as a clock enable for register 71 to set the contents of register 62 into register 71.

In this state, report completion (END) from memory.
returns, the D-type flip-flops 72-1, 72
-2, and its output becomes the write condition of stack ENDB, LDBU, and LUBL, and the +1 condition of write pointer (WP), respectively.

However, the STR bit of register 71 is “on”.
In this case, the stack LDBU,
Not stacked in LDBL.

The stack ENDB is provided with a V bit to indicate validity, and the V bit is turned "on" by the output of flip-flop 72-1.

In this way, the END set circuit uses the END signal from the memory as a trigger to set the stack.
Concentrate on stacking operations to ENDB, LDBU, and LDBL.

The output of stack ENDB, LDBU, LDBL is V
Used to report END to the channel and transfer load data using the bit as a trigger.

The above explanation shows an example of using the V bit as a trigger, but it is also possible to use the difference between the write pointer (WP) and read pointer (RP) as a trigger even without the V bit. .

Each of the above stacks is almost a static circuit, and can be easily integrated into an LSI.
can be applied to all stacks.

[Effects of the Invention] As explained above, according to the present invention, throughput can be greatly improved by issuing the next memory access request without checking the completion report from the memory, and this has practical advantages. The effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a circuit diagram of an embodiment of the RQ control circuit and END control circuit according to the present invention, and FIG. 4 is a block diagram of the embodiment of the present invention. FIG. 5 is a circuit diagram of an embodiment of the stack circuit according to the invention, FIG. 5 is a time chart showing an example of a memory interface, and FIG. 6 is a block diagram of a conventional example. In the drawing, 1 is an access request (control information)
Stack (MABU), 2 is memory address stack (MABL), 3 is store data stack (SDBU), (SDBL), 4 is completion report stack (ENDB), 5 is load data stack (LDBU), (LDBL). ), 6 is RQ control circuit, 7 is
END control circuit, 61, 65-1, 65-2, 7
4-1, 74-2 are AND gates, 63-1, 6
3-2, 63-3, 74-1, 74-2 are flip-flops, 62, 71 are registers, and 64 is a flip-flop.
73 represents a NOR gate, and 73 represents an inverter.

Claims (1)

[Scope of Claims] 1. A channel control device that controls access to a main storage device from a plurality of channels and data transfer between the channels and the main storage device, comprising: memory access from the channel to the main storage device; First-in, first-out access request stack 1 that stores request signals on a first-come, first-served basis
a first-in/first-out memory address stack 2 that stores memory addresses added to the memory access request on a first-come, first-served basis; and a first-in first-out memory address stack 2 that stores store data added when the memory access request is a write on a first-come, first-served basis. - a first-out store data stack 3; a first-in/first-out completion report stack 4 that stores, on a first-come-first-served basis, a report on the completion of access to the channel from the main memory; a first-in/first-out load data stack 5 that stores load data on a first-come, first-served basis; 1. RQ control circuit 6 that controls the shifting of the memory address stack 2 and store data stack 3 and controls the sending of the memory access request signal, memory address, and store data to the main storage device.
and END control, which controls the shift of the completion report stack 4 and load data stack 5 based on the access completion report from the main storage device, and controls the sending of the load data and access completion report to the channel that issued the access request. In the response confirmation type memory interface, which is equipped with circuit 7,
A channel control device characterized in that it is configured to issue a next memory access request without confirming completion of memory access.