JPH0481316B2 - - Google Patents
Info
- Publication number
- JPH0481316B2 JPH0481316B2 JP60169892A JP16989285A JPH0481316B2 JP H0481316 B2 JPH0481316 B2 JP H0481316B2 JP 60169892 A JP60169892 A JP 60169892A JP 16989285 A JP16989285 A JP 16989285A JP H0481316 B2 JPH0481316 B2 JP H0481316B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- front electrode
- elements
- light emitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 239000010408 film Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はEL(エレクトロルミネツセンス)表示
パネルに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an EL (electroluminescence) display panel.
一般に薄膜EL素子は、カードエツジ部に電極
の引き出し部を形成するため、第4図に示すよう
に絶縁基板1上に形成した前面電極2の引き出し
部を基板ホルダ3によつて隠した状態でスパツタ
リング、蒸着等により絶縁層や発光層等の薄膜4
を順次形成し、前面電極2の引き出しは第5図に
示すようにその薄膜4から絶縁基板1端部に露出
した部分で行なつている。なお、図中5は第2絶
縁層、6は発光層、7は第1絶縁層、8は背面電
極、9はボンデイングワイヤ、10は蒸発源であ
り、2Aは前面電極引き出し部である(例えば特
開昭59−27497号公報(第1図)、特開昭59−5594
号公報(第2,4図)、特開昭60−91595号公報な
ど)。
In general, thin film EL elements are formed by sputtering with the lead-out part of the front electrode 2 formed on the insulating substrate 1 hidden by the substrate holder 3, as shown in FIG. , thin film 4 such as an insulating layer or a light emitting layer by vapor deposition etc.
are successively formed, and the front electrode 2 is drawn out from the portion exposed from the thin film 4 to the end of the insulating substrate 1, as shown in FIG. In the figure, 5 is a second insulating layer, 6 is a light emitting layer, 7 is a first insulating layer, 8 is a back electrode, 9 is a bonding wire, 10 is an evaporation source, and 2A is a front electrode extension part (for example, JP-A-59-27497 (Figure 1), JP-A-59-5594
(Figures 2 and 4), Japanese Unexamined Patent Publication No. 1983-91595, etc.).
しかし、このように形成したXYマトリツクス
タイプのチツプ状のEL素子11を第6図に示す
ように複数つなぎ合せて大面積化をはかろうとす
る場合、上述した構造では接続に用いられるエツ
ジ部のスペースがかなり大きくなり、線間が例え
ば数mm以下のXYマトリツクスEL素子のチツプ相
互を、電極間のピツチがチツプ間のつなぎめでも
他と等しく維持されるように接続することは困難
である。
However, when attempting to increase the area by connecting multiple XY matrix type chip-shaped EL elements 11 formed in this way as shown in FIG. It is difficult to connect the chips of an XY matrix EL element, where the line spacing is, for example, several mm or less, in such a way that the pitch between the electrodes is maintained equal to other chips even when connecting the chips. .
このような問題点を解決するために、本発明
は、EL素子間の前面電極相互の接続を背面電極
と同一面上に形成しスルホールを介して前面電極
に接続した引き出し用電極間で行なつたものであ
る。
In order to solve these problems, the present invention connects the front electrodes of the EL elements to each other between extraction electrodes that are formed on the same surface as the back electrode and connected to the front electrode via a through hole. It is something that
各素子端部に前面電極相互の接続部を特に設け
る必要がなくなる。
There is no need to provide a connecting portion between the front electrodes at each element end.
第1図aは本発明の一実施例を示す断面図、同
図bはその平面図(第1図aは同図bのa−a断
面図)である。
FIG. 1a is a sectional view showing one embodiment of the present invention, and FIG. 1b is a plan view thereof (FIG. 1a is a sectional view taken along the line a-a in FIG. 1b).
次に第2図および第3図を用いてその製造方法
を説明する。まず、従来と同様の工程でコーニン
グ#7059ガラス(コーニング社)のような無アル
カリガラスからなる絶縁基板1上にストライプ状
のITO,SnO2などからなる透明前面電極2,Al2
O3,Si3N4などからなる第1絶縁層5、ZnS:
Mn,ZnS:TbF2などからなる発光層6、第1絶
縁層と同じ材料からなる第2絶縁層7を、電子ビ
ーム(EB)蒸着法あるいはスパツタリング法な
どの膜形成技術を用いて順次形成する。 Next, the manufacturing method will be explained using FIGS. 2 and 3. First, in the same process as before, a striped transparent front electrode 2 made of ITO, SnO 2 , etc., and Al 2
First insulating layer 5 made of O 3 , Si 3 N 4 , etc., ZnS:
A light emitting layer 6 made of Mn, ZnS:TbF 2 or the like and a second insulating layer 7 made of the same material as the first insulating layer are sequentially formed using a film forming technique such as electron beam (EB) evaporation or sputtering. .
次に、従来であれば背面電極を形成するのであ
るが、本実施例ではそれに先立ち、ドライエツチ
ング法を用いてチツプ端部の、前面電極2上では
あるが、発光ドツト以外部分にスルホール12を
形成する(第2図)。この場合、リアクテイブイ
オンエツチング法もしくはスパツタエツチング法
または両者を併用することにより、前面電極2と
第1絶縁層5との界面に達する孔を形成できる。 Next, conventionally, a back electrode is formed, but in this embodiment, prior to that, a through hole 12 is formed on the front electrode 2 at the end of the chip, except for the light emitting dots, using a dry etching method. form (Figure 2). In this case, a hole reaching the interface between the front electrode 2 and the first insulating layer 5 can be formed by using a reactive ion etching method, a sputter etching method, or a combination of both.
次にスパツタリング法などにより電極用Al薄
膜をスルホール12内を含めて全面に形成し、フ
オトリングラフイにより前面電極2に直交する背
面電極8およびスルホール12上には前面電極引
き出し用ボンデイングパツド13を同時形成す
る。前面電極2と背面電極8との交差部(第1図
b上で斜線を付した範囲)が発光ドツトとなる。
最後に、このチツプ状の薄膜EL素子の端部を第
2図に破線で示したように端部電極の中心位置か
らの距離dがチツプ上の電極ピツチPの1/2以下
となるような面で切断する(第3図)。 Next, a thin Al film for electrodes is formed on the entire surface including the inside of the through-hole 12 by a sputtering method, and a bonding pad 13 for leading out the front electrode is formed on the back electrode 8 perpendicular to the front electrode 2 and on the through-hole 12 by photolithography. are formed simultaneously. The intersection between the front electrode 2 and the back electrode 8 (the shaded area in FIG. 1b) becomes a light emitting dot.
Finally, the end of this chip-shaped thin film EL element is arranged so that the distance d from the center of the end electrode is less than 1/2 of the electrode pitch P on the chip, as shown by the broken line in Figure 2. Cut along the plane (Figure 3).
このような構造にすることにより、前面電極2
の引き出しがボンデイングパツド13により、背
面電極8と同一面上で行なえるようになつて、従
来必要であつたカードエツジ部の電極露出部(引
き出し部)が不要となるため、絶縁層、発光層な
どの薄膜の形成部分を予め広めにとつておき、後
で所定の寸法にカツテイングすることによつて、
エツジ部まで均一な特性のEL素子が得られる。
つまり、一般に前述したような方法で薄膜を形成
すると、どうしてもエツジ部で膜厚が薄くなり、
発光層にかかる電界強度が不均一となつて輝度む
らや絶縁破壊等による絵素欠けなどが発生すると
いう問題があるが、予めこの部分を見込んで大き
く形成し、当該部分を切除することにより全体に
均一な特性が得られる。また、上述したようにd
≦Pとしたことにより、チツプ相互のつなぎめに
おいても電極相互間の間隔がチツプ上の電極ピツ
チと等しくなるようにチツプ相互を配列接続する
ことができる。 With this structure, the front electrode 2
By using the bonding pad 13, the electrode can be drawn out on the same surface as the back electrode 8, and the electrode exposed part (drawing part) at the card edge part, which was necessary in the past, is no longer necessary. By preparing a wide area in advance for forming a thin film such as, and later cutting it to a predetermined size,
An EL element with uniform characteristics up to the edges can be obtained.
In other words, when forming a thin film using the method described above, the film inevitably becomes thinner at the edges.
There is a problem that the electric field strength applied to the light emitting layer becomes non-uniform, resulting in uneven brightness and pixel defects due to dielectric breakdown. Uniform characteristics can be obtained. Also, as mentioned above, d
By setting ≦P, the chips can be arranged and connected to each other so that the spacing between the electrodes is equal to the electrode pitch on the chip even when the chips are connected to each other.
次に、このようなチツプ状のEL素子21を、
共通の透明な基板22上に多数縦横に配列固定
し、電極相互をボンデイングワイヤ9によつて接
続するが、その場合、発光ドツト上でワイヤボン
デイングを行なうと、ボンデイングミスなどによ
る電極の損傷で絵素欠けの発生につながる可能性
があるため、接続はすべて発光ドツト部以外、つ
まり前面電極2と背面電極8との非交差部分で行
なう。また、エツジ部の上記非交差部分は面積が
エツジ部以外に比較して1/2以下であるため、一
般にはエツジ部を避けて接続を行なうが、第1図
bに示したように1点Aを中心に4個のチツプを
相互接続する場合には、縦方向のボンデイングワ
イヤと横方向のボンデイングワイヤとが交差し接
触するのを避けるため、その中心部に限つて、い
ずれか一方向の接続をエツジ部で行なう。第1図
中ボンデイングワイヤ9Aによる接続がこれに当
る。 Next, such a chip-shaped EL element 21 is
A large number of light emitting dots are arranged and fixed in rows and columns on a common transparent substrate 22, and the electrodes are connected to each other by bonding wires 9. However, in this case, if wire bonding is performed on the light emitting dots, the electrodes may be damaged due to bonding mistakes, etc. Since this may lead to the occurrence of chipping, all connections are made at areas other than the light emitting dots, that is, at non-intersecting areas between the front electrode 2 and the back electrode 8. In addition, since the area of the above-mentioned non-intersecting portion of the edge portion is less than 1/2 of the area other than the edge portion, the connection is generally made while avoiding the edge portion, but as shown in Figure 1b, When interconnecting four chips around point A, in order to avoid the vertical bonding wires and the horizontal bonding wires from crossing and contacting each other, connect only one direction at the center. Make the connection at the edge. This corresponds to the connection by the bonding wire 9A in FIG.
以上、発光層が第1および第2の絶縁層で挾ま
れた構造の薄膜EL素子を用いた例について説明
したが、本発明はこれに限定されるものではな
く、少なくとも発光層を挾んで前面電極と背面電
極とを交差させた構造のEL素子を用いたすべて
の場合に適用できる。 Although an example using a thin film EL element having a structure in which the light emitting layer is sandwiched between the first and second insulating layers has been described above, the present invention is not limited to this. It can be applied to all cases using an EL element with a structure in which an electrode and a back electrode are crossed.
以上説明したように、本発明によれば、EL素
子間の前面電極相互の接続を背面電極と同一面上
に形成しかつスルホールを介して前面電極に接続
した引き出し用電極間で行なうようにしたことに
より、EL素子相互を、EL素子間の電極間隔が各
EL素子上の電極ピツチに等しくなるように配列
接続することが可能となり、また、各素子端部を
切除して均一部のみ使用することが可能となり、
つなぎ合せ方式による大面積・高解像度のXYマ
トリツクスEL表示パネルの実現が可能となる。
As explained above, according to the present invention, the front electrodes of the EL elements are connected to each other between the extraction electrodes formed on the same surface as the back electrodes and connected to the front electrodes through the through holes. By doing this, the electrode spacing between the EL elements can be
It is now possible to arrange and connect the electrodes so that they are equal to the electrode pitch on the EL element, and it is also possible to cut off the ends of each element and use only the uniform part.
It becomes possible to realize a large-area, high-resolution XY matrix EL display panel using the piecing method.
第1図ないし第3図は本発明の一実施例を示
し、第1図aはその断面図、同図bは平面図、第
2図および第3図は製造途中の断面図、第4図な
いし第6図は従来例を示す断面図である。
1……絶縁基板、2……前面電極、6……発光
層、8……背面電極、9……ボンデイングワイ
ヤ、12……スルホール、13……前面電極引き
出し用ボンデイングパツド、21……EL素子、
22……透明基板。
1 to 3 show one embodiment of the present invention, FIG. 1a is a sectional view thereof, FIG. 1b is a plan view, FIGS. 2 and 3 are sectional views in the middle of manufacturing, and FIG. 4 6 to 6 are cross-sectional views showing conventional examples. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Front electrode, 6... Light emitting layer, 8... Back electrode, 9... Bonding wire, 12... Through hole, 13... Bonding pad for leading out front electrode, 21... EL element,
22...Transparent substrate.
Claims (1)
EL発光層を介して、前面電極に対向する背面電
極とを備えたEL素子を複数個同一の透明基板上
に前面電極側を透明基板側にして並べ、EL素子
相互の対応する電極間をワイヤボンデイングによ
り接続してなるEL表示パネルにおいて、EL素子
間の前面電極相互の接続を、背面電極と同一面上
に形成しスルホールを介して前面電極に接続した
引き出し用電極間で行ない、かつ背面電極相互の
接続は、当該背面電極の前面電極と交差しない部
分間で行なつたことを特徴とするEL表示パネル。 2 前面電極間を接続するボンデイングワイヤ
と、背面電極間を接続するボンデイングワイヤと
を相互に立体的に交差しないように配置したこと
を特持とする特特請求の範囲第1項記載のEL表
示パネル。[Claims] 1. A front electrode formed on a transparent insulating substrate;
A plurality of EL elements each having a back electrode facing a front electrode through an EL light emitting layer are arranged on the same transparent substrate with the front electrode side facing the transparent substrate, and a wire is connected between the corresponding electrodes of the EL elements. In an EL display panel that is connected by bonding, the front electrodes between the EL elements are connected between the extraction electrodes formed on the same surface as the back electrode and connected to the front electrode via a through hole, and the back electrode An EL display panel characterized in that mutual connections are made between parts of the back electrode that do not intersect with the front electrode. 2. The EL display according to claim 1, characterized in that the bonding wires connecting between the front electrodes and the bonding wires connecting between the back electrodes are arranged so as not to intersect with each other three-dimensionally. panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60169892A JPS6231989A (en) | 1985-08-02 | 1985-08-02 | El display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60169892A JPS6231989A (en) | 1985-08-02 | 1985-08-02 | El display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6231989A JPS6231989A (en) | 1987-02-10 |
| JPH0481316B2 true JPH0481316B2 (en) | 1992-12-22 |
Family
ID=15894893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60169892A Granted JPS6231989A (en) | 1985-08-02 | 1985-08-02 | El display panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6231989A (en) |
-
1985
- 1985-08-02 JP JP60169892A patent/JPS6231989A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6231989A (en) | 1987-02-10 |
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